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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / cdbc848b03414c75b7badccd8ada29deba7ec6e4 / . / drivers / pinctrl / sh-pfc / pfc-r8a7796.c
blob: 3a6d21d871070b925fe779bd9a314ab9d61bcb03 [file] [log] [blame]
Kuninori Morimoto63b6d7e2018-09-07 02:13:29 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]2/*
3 * R8A7796 processor support - PFC hardware block.
4 *
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]12 */
13
14#include <linux/kernel.h>
15
16#include "core.h"
17#include "sh_pfc.h"
18
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]19#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
20 SH_PFC_PIN_CFG_PULL_UP | \
21 SH_PFC_PIN_CFG_PULL_DOWN)
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]22
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]23#define CPU_ALL_PORT(fn, sfx) \
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]36/*
37 * F_() : just information
38 * FM() : macro for FN_xxx / xxx_MARK
39 */
40
41/* GPSR0 */
42#define GPSR0_15 F_(D15, IP7_11_8)
43#define GPSR0_14 F_(D14, IP7_7_4)
44#define GPSR0_13 F_(D13, IP7_3_0)
45#define GPSR0_12 F_(D12, IP6_31_28)
46#define GPSR0_11 F_(D11, IP6_27_24)
47#define GPSR0_10 F_(D10, IP6_23_20)
48#define GPSR0_9 F_(D9, IP6_19_16)
49#define GPSR0_8 F_(D8, IP6_15_12)
50#define GPSR0_7 F_(D7, IP6_11_8)
51#define GPSR0_6 F_(D6, IP6_7_4)
52#define GPSR0_5 F_(D5, IP6_3_0)
53#define GPSR0_4 F_(D4, IP5_31_28)
54#define GPSR0_3 F_(D3, IP5_27_24)
55#define GPSR0_2 F_(D2, IP5_23_20)
56#define GPSR0_1 F_(D1, IP5_19_16)
57#define GPSR0_0 F_(D0, IP5_15_12)
58
59/* GPSR1 */
60#define GPSR1_28 FM(CLKOUT)
61#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
62#define GPSR1_26 F_(WE1_N, IP5_7_4)
63#define GPSR1_25 F_(WE0_N, IP5_3_0)
64#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
65#define GPSR1_23 F_(RD_N, IP4_27_24)
66#define GPSR1_22 F_(BS_N, IP4_23_20)
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]67#define GPSR1_21 F_(CS1_N, IP4_19_16)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]68#define GPSR1_20 F_(CS0_N, IP4_15_12)
69#define GPSR1_19 F_(A19, IP4_11_8)
70#define GPSR1_18 F_(A18, IP4_7_4)
71#define GPSR1_17 F_(A17, IP4_3_0)
72#define GPSR1_16 F_(A16, IP3_31_28)
73#define GPSR1_15 F_(A15, IP3_27_24)
74#define GPSR1_14 F_(A14, IP3_23_20)
75#define GPSR1_13 F_(A13, IP3_19_16)
76#define GPSR1_12 F_(A12, IP3_15_12)
77#define GPSR1_11 F_(A11, IP3_11_8)
78#define GPSR1_10 F_(A10, IP3_7_4)
79#define GPSR1_9 F_(A9, IP3_3_0)
80#define GPSR1_8 F_(A8, IP2_31_28)
81#define GPSR1_7 F_(A7, IP2_27_24)
82#define GPSR1_6 F_(A6, IP2_23_20)
83#define GPSR1_5 F_(A5, IP2_19_16)
84#define GPSR1_4 F_(A4, IP2_15_12)
85#define GPSR1_3 F_(A3, IP2_11_8)
86#define GPSR1_2 F_(A2, IP2_7_4)
87#define GPSR1_1 F_(A1, IP2_3_0)
88#define GPSR1_0 F_(A0, IP1_31_28)
89
90/* GPSR2 */
91#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
92#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
93#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
94#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
95#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
96#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
97#define GPSR2_8 F_(PWM2_A, IP1_27_24)
98#define GPSR2_7 F_(PWM1_A, IP1_23_20)
99#define GPSR2_6 F_(PWM0, IP1_19_16)
100#define GPSR2_5 F_(IRQ5, IP1_15_12)
101#define GPSR2_4 F_(IRQ4, IP1_11_8)
102#define GPSR2_3 F_(IRQ3, IP1_7_4)
103#define GPSR2_2 F_(IRQ2, IP1_3_0)
104#define GPSR2_1 F_(IRQ1, IP0_31_28)
105#define GPSR2_0 F_(IRQ0, IP0_27_24)
106
107/* GPSR3 */
108#define GPSR3_15 F_(SD1_WP, IP11_23_20)
109#define GPSR3_14 F_(SD1_CD, IP11_19_16)
110#define GPSR3_13 F_(SD0_WP, IP11_15_12)
111#define GPSR3_12 F_(SD0_CD, IP11_11_8)
112#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
113#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
114#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
115#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
116#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
117#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
118#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
119#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
120#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
121#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
122#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
123#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
124
125/* GPSR4 */
Geert Uytterhoeven0f866a92016-10-21 17:30:59 +0200[diff] [blame]126#define GPSR4_17 F_(SD3_DS, IP11_7_4)
127#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
128#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
129#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
130#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]131#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
132#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
133#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
134#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
135#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
136#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
Geert Uytterhoeven0f866a92016-10-21 17:30:59 +0200[diff] [blame]137#define GPSR4_6 F_(SD2_DS, IP9_27_24)
138#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
139#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
140#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
141#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]142#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
143#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
144
145/* GPSR5 */
146#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
147#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
148#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
149#define GPSR5_22 FM(MSIOF0_RXD)
150#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
151#define GPSR5_20 FM(MSIOF0_TXD)
152#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
153#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
154#define GPSR5_17 FM(MSIOF0_SCK)
155#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
156#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
157#define GPSR5_14 F_(HTX0, IP13_19_16)
158#define GPSR5_13 F_(HRX0, IP13_15_12)
159#define GPSR5_12 F_(HSCK0, IP13_11_8)
160#define GPSR5_11 F_(RX2_A, IP13_7_4)
161#define GPSR5_10 F_(TX2_A, IP13_3_0)
162#define GPSR5_9 F_(SCK2, IP12_31_28)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]163#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]164#define GPSR5_7 F_(CTS1_N, IP12_23_20)
165#define GPSR5_6 F_(TX1_A, IP12_19_16)
166#define GPSR5_5 F_(RX1_A, IP12_15_12)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]167#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]168#define GPSR5_3 F_(CTS0_N, IP12_7_4)
169#define GPSR5_2 F_(TX0, IP12_3_0)
170#define GPSR5_1 F_(RX0, IP11_31_28)
171#define GPSR5_0 F_(SCK0, IP11_27_24)
172
173/* GPSR6 */
174#define GPSR6_31 F_(GP6_31, IP18_7_4)
175#define GPSR6_30 F_(GP6_30, IP18_3_0)
176#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
177#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
178#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
179#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
180#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
181#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
182#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
183#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
184#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
185#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
186#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
187#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
188#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
189#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
190#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
191#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
192#define GPSR6_13 FM(SSI_SDATA5)
193#define GPSR6_12 FM(SSI_WS5)
194#define GPSR6_11 FM(SSI_SCK5)
195#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
196#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
197#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
198#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]199#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
200#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]201#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
202#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
203#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]204#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
205#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]206
207/* GPSR7 */
208#define GPSR7_3 FM(GP7_03)
209#define GPSR7_2 FM(HDMI0_CEC)
210#define GPSR7_1 FM(AVS2)
211#define GPSR7_0 FM(AVS1)
212
213
214/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
215#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]220#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara70070192017-06-01 22:37:24 +0900[diff] [blame]221#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]223#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharafbd81e32017-11-16 12:17:18 +0900[diff] [blame]224#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]230#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]240#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]241#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242
243/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
244#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]253#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]254#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]258#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]259#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]271#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]272#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273
274/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
275#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]278#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara6fb18702017-07-13 01:55:40 +0900[diff] [blame]290#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0a5e7372017-07-13 01:55:44 +0900[diff] [blame]296#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara6fb18702017-07-13 01:55:40 +0900[diff] [blame]297#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]308#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309
310/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
311#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]318#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]319#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]322#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]323#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]324#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]326#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
332#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]337#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]339
340/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
341#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]344#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]346#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
361#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
362#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
363#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
364#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]365#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
367#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]368
369#define PINMUX_GPSR \
370\
371 GPSR6_31 \
372 GPSR6_30 \
373 GPSR6_29 \
374 GPSR1_28 GPSR6_28 \
375 GPSR1_27 GPSR6_27 \
376 GPSR1_26 GPSR6_26 \
377 GPSR1_25 GPSR5_25 GPSR6_25 \
378 GPSR1_24 GPSR5_24 GPSR6_24 \
379 GPSR1_23 GPSR5_23 GPSR6_23 \
380 GPSR1_22 GPSR5_22 GPSR6_22 \
381 GPSR1_21 GPSR5_21 GPSR6_21 \
382 GPSR1_20 GPSR5_20 GPSR6_20 \
383 GPSR1_19 GPSR5_19 GPSR6_19 \
384 GPSR1_18 GPSR5_18 GPSR6_18 \
385 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
386 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
387GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
388GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
389GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
390GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
391GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
392GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
393GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
394GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
395GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
396GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
397GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
398GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
399GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
400GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
401GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
402GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
403
404#define PINMUX_IPSR \
405\
406FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
407FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
408FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
409FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
410FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
411FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
412FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
413FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
414\
415FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
416FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
417FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
Takeshi Kihara89217782017-07-13 01:55:43 +0900[diff] [blame]418FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]419FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
420FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
421FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
422FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
423\
424FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
425FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
426FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
427FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
428FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
429FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
430FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
431FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
432\
433FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
434FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
435FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
436FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
437FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
438FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
439FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
440FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
441\
442FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
443FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
444FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
445FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
446FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
447FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
448FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
449FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
450
451/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
452#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
453#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
454#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
455#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
456#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
457#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
458#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
459#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
460#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
461#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]462#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
463#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
464#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
465#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
466#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
467#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
468#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
469#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]470
471/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
472#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
473#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
475#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
476#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]477#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]478#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
479#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
480#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
481#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
482#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
483#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
484#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]485#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]486#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
487#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
488#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
489#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
490#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
491#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
492#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
493#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
494
Wolfram Sang94888a42017-10-09 10:37:25 +0200[diff] [blame]495/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]496#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
497#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
498#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
499#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
500#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
501#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]502#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]503#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
504#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
505#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
506#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
507#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
508#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
509
510#define PINMUX_MOD_SELS \
511\
512MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
513 MOD_SEL2_30 \
514 MOD_SEL1_29_28_27 MOD_SEL2_29 \
515MOD_SEL0_28_27 MOD_SEL2_28_27 \
516MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
517 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
518MOD_SEL0_23 MOD_SEL1_23_22_21 \
519MOD_SEL0_22 MOD_SEL2_22 \
520MOD_SEL0_21 MOD_SEL2_21 \
521MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
522MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
523MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
524 MOD_SEL2_17 \
525MOD_SEL0_16 MOD_SEL1_16 \
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]526 MOD_SEL1_15_14 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]527MOD_SEL0_14_13 \
528 MOD_SEL1_13 \
529MOD_SEL0_12 MOD_SEL1_12 \
530MOD_SEL0_11 MOD_SEL1_11 \
531MOD_SEL0_10 MOD_SEL1_10 \
532MOD_SEL0_9_8 MOD_SEL1_9 \
533MOD_SEL0_7_6 \
534 MOD_SEL1_6 \
535MOD_SEL0_5 MOD_SEL1_5 \
536MOD_SEL0_4_3 MOD_SEL1_4 \
537 MOD_SEL1_3 \
Takeshi Kiharae56c5132017-07-13 01:55:45 +0900[diff] [blame]538 MOD_SEL1_2 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]539 MOD_SEL1_1 \
540 MOD_SEL1_0 MOD_SEL2_0
541
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]542/*
543 * These pins are not able to be muxed but have other properties
544 * that can be set, such as drive-strength or pull-up/pull-down enable.
545 */
546#define PINMUX_STATIC \
547 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
548 FM(QSPI0_IO2) FM(QSPI0_IO3) \
549 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
550 FM(QSPI1_IO2) FM(QSPI1_IO3) \
551 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
552 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
553 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
554 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
555 FM(PRESETOUT) \
556 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]557 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]558
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]559enum {
560 PINMUX_RESERVED = 0,
561
562 PINMUX_DATA_BEGIN,
563 GP_ALL(DATA),
564 PINMUX_DATA_END,
565
566#define F_(x, y)
567#define FM(x) FN_##x,
568 PINMUX_FUNCTION_BEGIN,
569 GP_ALL(FN),
570 PINMUX_GPSR
571 PINMUX_IPSR
572 PINMUX_MOD_SELS
573 PINMUX_FUNCTION_END,
574#undef F_
575#undef FM
576
577#define F_(x, y)
578#define FM(x) x##_MARK,
579 PINMUX_MARK_BEGIN,
580 PINMUX_GPSR
581 PINMUX_IPSR
582 PINMUX_MOD_SELS
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]583 PINMUX_STATIC
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]584 PINMUX_MARK_END,
585#undef F_
586#undef FM
587};
588
589static const u16 pinmux_data[] = {
590 PINMUX_DATA_GP_ALL(),
591
592 PINMUX_SINGLE(AVS1),
593 PINMUX_SINGLE(AVS2),
594 PINMUX_SINGLE(CLKOUT),
595 PINMUX_SINGLE(GP7_03),
596 PINMUX_SINGLE(HDMI0_CEC),
597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
604 /* IPSR0 */
605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
623
624 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
625 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]626 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]627
628 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
629 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
630 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
631 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
635
636 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
637 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
638 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
639 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
Takeshi Kihara1554b982017-06-01 22:25:30 +0900[diff] [blame]642 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]643
644 /* IPSR1 */
645 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
646 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
647 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
648 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
649 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
651
652 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
653 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
658
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]661 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
662 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
663 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
665
666 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
667 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]668 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
669 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
670 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
671 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
672
673 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
674 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]675 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
676 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
677
678 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]679 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
680 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
681 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
682
683 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]684 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
686
687 PINMUX_IPSR_GPSR(IP1_31_28, A0),
688 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
689 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
690 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
691 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
692 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
693
694 /* IPSR2 */
695 PINMUX_IPSR_GPSR(IP2_3_0, A1),
696 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
697 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
699 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
700 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
701
702 PINMUX_IPSR_GPSR(IP2_7_4, A2),
703 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
704 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
705 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
706 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
707 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
708
709 PINMUX_IPSR_GPSR(IP2_11_8, A3),
710 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
711 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
712 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
713 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
714 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
715
716 PINMUX_IPSR_GPSR(IP2_15_12, A4),
717 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
718 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
719 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
720 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
721 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
722
723 PINMUX_IPSR_GPSR(IP2_19_16, A5),
724 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
725 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
726 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
727 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
728 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
729 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
730
731 PINMUX_IPSR_GPSR(IP2_23_20, A6),
732 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
733 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
734 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
735 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
736 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
737 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
738
739 PINMUX_IPSR_GPSR(IP2_27_24, A7),
740 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
741 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
743 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
744 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
745 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
746
747 PINMUX_IPSR_GPSR(IP2_31_28, A8),
748 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
749 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
751 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
752 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
753 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
754
755 /* IPSR3 */
756 PINMUX_IPSR_GPSR(IP3_3_0, A9),
757 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
759 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
760
761 PINMUX_IPSR_GPSR(IP3_7_4, A10),
762 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]763 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]764 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
765
766 PINMUX_IPSR_GPSR(IP3_11_8, A11),
767 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
768 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
771 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
772 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
773 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
775
776 PINMUX_IPSR_GPSR(IP3_15_12, A12),
777 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
778 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
779 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
780 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
781 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
782
783 PINMUX_IPSR_GPSR(IP3_19_16, A13),
784 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
785 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
786 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
787 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
788 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
789
790 PINMUX_IPSR_GPSR(IP3_23_20, A14),
791 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
792 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
793 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
794 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
795 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
796
797 PINMUX_IPSR_GPSR(IP3_27_24, A15),
798 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
799 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
800 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
801 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
802 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
803
804 PINMUX_IPSR_GPSR(IP3_31_28, A16),
805 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
806 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
807 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
808
809 /* IPSR4 */
810 PINMUX_IPSR_GPSR(IP4_3_0, A17),
811 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
812 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
813 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
814
815 PINMUX_IPSR_GPSR(IP4_7_4, A18),
816 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
817 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
818 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
819
820 PINMUX_IPSR_GPSR(IP4_11_8, A19),
821 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
822 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
823 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
824
825 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
826 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
827
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]828 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]829 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
830 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
831
832 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
833 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
834 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
835 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
836 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
837 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
838 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
839 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
840
841 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
842 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
843 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
844 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
845 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
846 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
847
848 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
849 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
850 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
853 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
854
855 /* IPSR5 */
856 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
857 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
859 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
861 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
862 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
863
864 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
865 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]866 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]867 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
869 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
870 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
871 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
872
873 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
874 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
875 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
876 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
877
878 PINMUX_IPSR_GPSR(IP5_15_12, D0),
879 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
880 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
881 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
882 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
883
884 PINMUX_IPSR_GPSR(IP5_19_16, D1),
885 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
888 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
889
890 PINMUX_IPSR_GPSR(IP5_23_20, D2),
891 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
892 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
893 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
894
895 PINMUX_IPSR_GPSR(IP5_27_24, D3),
896 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
897 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
898 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
899
900 PINMUX_IPSR_GPSR(IP5_31_28, D4),
901 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
902 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
903 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
904
905 /* IPSR6 */
906 PINMUX_IPSR_GPSR(IP6_3_0, D5),
907 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
909 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
910
911 PINMUX_IPSR_GPSR(IP6_7_4, D6),
912 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
913 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
914 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
915
916 PINMUX_IPSR_GPSR(IP6_11_8, D7),
917 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
918 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
919 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
920
921 PINMUX_IPSR_GPSR(IP6_15_12, D8),
922 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
923 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
924 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
925 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
926 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
927
928 PINMUX_IPSR_GPSR(IP6_19_16, D9),
929 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
930 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
931 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
933
934 PINMUX_IPSR_GPSR(IP6_23_20, D10),
935 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
936 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
938 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
939 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
940 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
941
942 PINMUX_IPSR_GPSR(IP6_27_24, D11),
943 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
944 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]947 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]948 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
949
950 PINMUX_IPSR_GPSR(IP6_31_28, D12),
951 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
952 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
954 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
955 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
956
957 /* IPSR7 */
958 PINMUX_IPSR_GPSR(IP7_3_0, D13),
959 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
960 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
963 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
964
965 PINMUX_IPSR_GPSR(IP7_7_4, D14),
966 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
967 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
968 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
969 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
970 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
971 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
972
973 PINMUX_IPSR_GPSR(IP7_11_8, D15),
974 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
975 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
979 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
980
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]981 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
982 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
984
985 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
986 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
987 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
988
989 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
990 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
991 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
992 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
993
994 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
995 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
996 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
997 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
998
999 /* IPSR8 */
1000 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1001 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1004
1005 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1006 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1007 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1008 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1009
1010 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1011 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1012 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1013
1014 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1015 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1016 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1017 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1018 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1019
1020 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1021 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1022 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1023 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1024 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1025 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1026
1027 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1028 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1029 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1030 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1031 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1032 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1033
1034 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1035 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1036 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1037 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1038 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1039 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1040
1041 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1042 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1043 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1044 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1045 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1046 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1047
1048 /* IPSR9 */
1049 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1050 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1051
1052 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1053 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1054
1055 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1056 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1057
1058 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1059 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1060
1061 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1062 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1063
1064 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1065 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1066
1067 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1068 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1069
1070 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1071 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1072
1073 /* IPSR10 */
1074 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1075 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1076
1077 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1078 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1079
1080 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1081 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1082
1083 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1084 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1085
1086 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1087 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1088
1089 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1090 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1091 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1092
1093 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1094 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1095 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1096
1097 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1098 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1099 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1100
1101 /* IPSR11 */
1102 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1103 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1104 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1105
1106 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1107 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1108
1109 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1110 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1111 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1112 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1113
1114 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1115 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1116 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1117
1118 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1119 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1120 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1123 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1124 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1127 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1129 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1130 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1133 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1134 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1136
1137 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1138 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1139 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1140 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1141 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1142
1143 /* IPSR12 */
1144 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1145 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1149
1150 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1151 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1152 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1153 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1154 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1155 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1156 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1157 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1158
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]1159 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1160 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1162 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1163 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1164 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1165 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1166 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1167
1168 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1169 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1170 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1171 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1172 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1173
1174 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1177 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1178 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1179
1180 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1181 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1183 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1184 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1185 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1186 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1187
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]1188 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1189 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1190 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1191 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1192 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1193 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1194 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1195
1196 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]1197 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1198 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1199 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1201 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1202 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1203
1204 /* IPSR13 */
1205 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1206 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1207 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1208 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1210 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1211
1212 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1217 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1218
1219 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1220 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1221 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1222 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1223 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1226 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1227
1228 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1229 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1230 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1231 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1232 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1234
1235 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1236 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1237 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1238 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1241
1242 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1243 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1244 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1245 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1246 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1247 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1249 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1250
1251 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1252 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1253 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1254 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1255 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1256 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1257 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1258
1259 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1260 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1261 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1262 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1263
1264 /* IPSR14 */
1265 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1266 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1267 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1268 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1269 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1270 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1271 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1272 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1273
1274 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1275 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1276 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1277 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1278 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1279 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1280 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1282
1283 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1284 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1285 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1288 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1289 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1290 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1291
1292 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1293 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1294 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1295
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]1296 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1297 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1298
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]1299 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1300 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1303 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1304
1305 /* IPSR15 */
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1306 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1307
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1308 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1309 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1310
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]1311 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1312 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1313 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1314
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]1315 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1316 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1317 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1318 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1319
1320 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1321 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1322 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1323 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1324 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1327
1328 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1329 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1330 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1331 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1332 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1335
1336 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1337 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1338 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1339 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1340 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1343
1344 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1345 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1346 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1348 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1351
1352 /* IPSR16 */
1353 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1354 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1355
1356 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1357 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1358
1359 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1360 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1363 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1364 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1365 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1366 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1367 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1368 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1369
1370 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1371 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1379 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
Takeshi Kiharaf21b4fc2017-07-13 01:55:42 +0900[diff] [blame]1385 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1386
1387 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1388 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1389 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1390 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1391 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1392 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1393 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1394
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1395 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1396 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1399 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1400 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1401 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
Takeshi Kihara04ee2ab2017-07-13 01:55:36 +0900[diff] [blame]1402 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1403
1404 /* IPSR17 */
1405 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1406 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1407
1408 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]1409 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1410 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1411 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1412 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1413
1414 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1415 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1416 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1417 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1418 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1419 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1420 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1421
1422 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1423 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1424 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1425 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1426 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1427 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1428
1429 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1430 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1431 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1432 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1433 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1434 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1435 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1440 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1441 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1442 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1448
1449 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1450 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1451 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1452 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
Takeshi Kihara7aa36a32017-07-13 01:55:34 +0900[diff] [blame]1453 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1454 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1455 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
Takeshi Kiharaf21b4fc2017-07-13 01:55:42 +0900[diff] [blame]1456 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1457 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1458 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1459 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1460
1461 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1462 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1463 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1464 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1465 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1466 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1467 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1468 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1469 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1470
1471 /* IPSR18 */
1472 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1473 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1474 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1475 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1476 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1478 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1479 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1480 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1481
1482 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1483 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1484 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1485 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1489 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1491
1492 /* I2C */
1493 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1494 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1495 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1496
1497/*
1498 * Static pins can not be muxed between different functions but
Geert Uytterhoevendb701f42018-05-14 21:30:02 +0200[diff] [blame]1499 * still need mark entries in the pinmux list. Add each static
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1500 * pin to the list without an associated function. The sh-pfc
Geert Uytterhoevendb701f42018-05-14 21:30:02 +0200[diff] [blame]1501 * core will do the right thing and skip trying to mux the pin
1502 * while still applying configuration to it.
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1503 */
1504#define FM(x) PINMUX_DATA(x##_MARK, 0),
1505 PINMUX_STATIC
1506#undef FM
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1507};
1508
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1509/*
1510 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1511 * Physical layout rows: A - AW, cols: 1 - 39.
1512 */
1513#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1514#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1515#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]1516#define PIN_NONE U16_MAX
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1517
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1518static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1520
1521 /*
1522 * Pins not associated with a GPIO port.
1523 *
1524 * The pin positions are different between different r8a7796
1525 * packages, all that is needed for the pfc driver is a unique
1526 * number for each pin. To this end use the pin layout from
1527 * R-Car M3SiP to calculate a unique number for each pin.
1528 */
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]1529 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1571};
1572
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]1573/* - AUDIO CLOCK ------------------------------------------------------------ */
1574static const unsigned int audio_clk_a_a_pins[] = {
1575 /* CLK A */
1576 RCAR_GP_PIN(6, 22),
1577};
1578static const unsigned int audio_clk_a_a_mux[] = {
1579 AUDIO_CLKA_A_MARK,
1580};
1581static const unsigned int audio_clk_a_b_pins[] = {
1582 /* CLK A */
1583 RCAR_GP_PIN(5, 4),
1584};
1585static const unsigned int audio_clk_a_b_mux[] = {
1586 AUDIO_CLKA_B_MARK,
1587};
1588static const unsigned int audio_clk_a_c_pins[] = {
1589 /* CLK A */
1590 RCAR_GP_PIN(5, 19),
1591};
1592static const unsigned int audio_clk_a_c_mux[] = {
1593 AUDIO_CLKA_C_MARK,
1594};
1595static const unsigned int audio_clk_b_a_pins[] = {
1596 /* CLK B */
1597 RCAR_GP_PIN(5, 12),
1598};
1599static const unsigned int audio_clk_b_a_mux[] = {
1600 AUDIO_CLKB_A_MARK,
1601};
1602static const unsigned int audio_clk_b_b_pins[] = {
1603 /* CLK B */
1604 RCAR_GP_PIN(6, 23),
1605};
1606static const unsigned int audio_clk_b_b_mux[] = {
1607 AUDIO_CLKB_B_MARK,
1608};
1609static const unsigned int audio_clk_c_a_pins[] = {
1610 /* CLK C */
1611 RCAR_GP_PIN(5, 21),
1612};
1613static const unsigned int audio_clk_c_a_mux[] = {
1614 AUDIO_CLKC_A_MARK,
1615};
1616static const unsigned int audio_clk_c_b_pins[] = {
1617 /* CLK C */
1618 RCAR_GP_PIN(5, 0),
1619};
1620static const unsigned int audio_clk_c_b_mux[] = {
1621 AUDIO_CLKC_B_MARK,
1622};
1623static const unsigned int audio_clkout_a_pins[] = {
1624 /* CLKOUT */
1625 RCAR_GP_PIN(5, 18),
1626};
1627static const unsigned int audio_clkout_a_mux[] = {
1628 AUDIO_CLKOUT_A_MARK,
1629};
1630static const unsigned int audio_clkout_b_pins[] = {
1631 /* CLKOUT */
1632 RCAR_GP_PIN(6, 28),
1633};
1634static const unsigned int audio_clkout_b_mux[] = {
1635 AUDIO_CLKOUT_B_MARK,
1636};
1637static const unsigned int audio_clkout_c_pins[] = {
1638 /* CLKOUT */
1639 RCAR_GP_PIN(5, 3),
1640};
1641static const unsigned int audio_clkout_c_mux[] = {
1642 AUDIO_CLKOUT_C_MARK,
1643};
1644static const unsigned int audio_clkout_d_pins[] = {
1645 /* CLKOUT */
1646 RCAR_GP_PIN(5, 21),
1647};
1648static const unsigned int audio_clkout_d_mux[] = {
1649 AUDIO_CLKOUT_D_MARK,
1650};
1651static const unsigned int audio_clkout1_a_pins[] = {
1652 /* CLKOUT1 */
1653 RCAR_GP_PIN(5, 15),
1654};
1655static const unsigned int audio_clkout1_a_mux[] = {
1656 AUDIO_CLKOUT1_A_MARK,
1657};
1658static const unsigned int audio_clkout1_b_pins[] = {
1659 /* CLKOUT1 */
1660 RCAR_GP_PIN(6, 29),
1661};
1662static const unsigned int audio_clkout1_b_mux[] = {
1663 AUDIO_CLKOUT1_B_MARK,
1664};
1665static const unsigned int audio_clkout2_a_pins[] = {
1666 /* CLKOUT2 */
1667 RCAR_GP_PIN(5, 16),
1668};
1669static const unsigned int audio_clkout2_a_mux[] = {
1670 AUDIO_CLKOUT2_A_MARK,
1671};
1672static const unsigned int audio_clkout2_b_pins[] = {
1673 /* CLKOUT2 */
1674 RCAR_GP_PIN(6, 30),
1675};
1676static const unsigned int audio_clkout2_b_mux[] = {
1677 AUDIO_CLKOUT2_B_MARK,
1678};
1679
1680static const unsigned int audio_clkout3_a_pins[] = {
1681 /* CLKOUT3 */
1682 RCAR_GP_PIN(5, 19),
1683};
1684static const unsigned int audio_clkout3_a_mux[] = {
1685 AUDIO_CLKOUT3_A_MARK,
1686};
1687static const unsigned int audio_clkout3_b_pins[] = {
1688 /* CLKOUT3 */
1689 RCAR_GP_PIN(6, 31),
1690};
1691static const unsigned int audio_clkout3_b_mux[] = {
1692 AUDIO_CLKOUT3_B_MARK,
1693};
1694
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1695/* - EtherAVB --------------------------------------------------------------- */
1696static const unsigned int avb_link_pins[] = {
1697 /* AVB_LINK */
1698 RCAR_GP_PIN(2, 12),
1699};
1700static const unsigned int avb_link_mux[] = {
1701 AVB_LINK_MARK,
1702};
1703static const unsigned int avb_magic_pins[] = {
1704 /* AVB_MAGIC_ */
1705 RCAR_GP_PIN(2, 10),
1706};
1707static const unsigned int avb_magic_mux[] = {
1708 AVB_MAGIC_MARK,
1709};
1710static const unsigned int avb_phy_int_pins[] = {
1711 /* AVB_PHY_INT */
1712 RCAR_GP_PIN(2, 11),
1713};
1714static const unsigned int avb_phy_int_mux[] = {
1715 AVB_PHY_INT_MARK,
1716};
Geert Uytterhoeven350aba92018-03-12 14:53:13 +0100[diff] [blame]1717static const unsigned int avb_mdio_pins[] = {
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]1718 /* AVB_MDC, AVB_MDIO */
1719 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1720};
Geert Uytterhoeven350aba92018-03-12 14:53:13 +0100[diff] [blame]1721static const unsigned int avb_mdio_mux[] = {
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]1722 AVB_MDC_MARK, AVB_MDIO_MARK,
1723};
1724static const unsigned int avb_mii_pins[] = {
1725 /*
1726 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1727 * AVB_TD1, AVB_TD2, AVB_TD3,
1728 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1729 * AVB_RD1, AVB_RD2, AVB_RD3,
1730 * AVB_TXCREFCLK
1731 */
1732 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1733 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1734 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1735 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1736 PIN_NUMBER('A', 12),
1737
1738};
1739static const unsigned int avb_mii_mux[] = {
1740 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1741 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1742 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1743 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1744 AVB_TXCREFCLK_MARK,
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1745};
1746static const unsigned int avb_avtp_pps_pins[] = {
1747 /* AVB_AVTP_PPS */
1748 RCAR_GP_PIN(2, 6),
1749};
1750static const unsigned int avb_avtp_pps_mux[] = {
1751 AVB_AVTP_PPS_MARK,
1752};
1753static const unsigned int avb_avtp_match_a_pins[] = {
1754 /* AVB_AVTP_MATCH_A */
1755 RCAR_GP_PIN(2, 13),
1756};
1757static const unsigned int avb_avtp_match_a_mux[] = {
1758 AVB_AVTP_MATCH_A_MARK,
1759};
1760static const unsigned int avb_avtp_capture_a_pins[] = {
1761 /* AVB_AVTP_CAPTURE_A */
1762 RCAR_GP_PIN(2, 14),
1763};
1764static const unsigned int avb_avtp_capture_a_mux[] = {
1765 AVB_AVTP_CAPTURE_A_MARK,
1766};
1767static const unsigned int avb_avtp_match_b_pins[] = {
1768 /* AVB_AVTP_MATCH_B */
1769 RCAR_GP_PIN(1, 8),
1770};
1771static const unsigned int avb_avtp_match_b_mux[] = {
1772 AVB_AVTP_MATCH_B_MARK,
1773};
1774static const unsigned int avb_avtp_capture_b_pins[] = {
1775 /* AVB_AVTP_CAPTURE_B */
1776 RCAR_GP_PIN(1, 11),
1777};
1778static const unsigned int avb_avtp_capture_b_mux[] = {
1779 AVB_AVTP_CAPTURE_B_MARK,
1780};
1781
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]1782/* - CAN ------------------------------------------------------------------ */
1783static const unsigned int can0_data_a_pins[] = {
1784 /* TX, RX */
1785 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1786};
1787static const unsigned int can0_data_a_mux[] = {
1788 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1789};
1790static const unsigned int can0_data_b_pins[] = {
1791 /* TX, RX */
1792 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1793};
1794static const unsigned int can0_data_b_mux[] = {
1795 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1796};
1797static const unsigned int can1_data_pins[] = {
1798 /* TX, RX */
1799 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1800};
1801static const unsigned int can1_data_mux[] = {
1802 CAN1_TX_MARK, CAN1_RX_MARK,
1803};
1804
1805/* - CAN Clock -------------------------------------------------------------- */
1806static const unsigned int can_clk_pins[] = {
1807 /* CLK */
1808 RCAR_GP_PIN(1, 25),
1809};
1810static const unsigned int can_clk_mux[] = {
1811 CAN_CLK_MARK,
1812};
1813
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]1814/* - CAN FD --------------------------------------------------------------- */
1815static const unsigned int canfd0_data_a_pins[] = {
1816 /* TX, RX */
1817 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1818};
1819static const unsigned int canfd0_data_a_mux[] = {
1820 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1821};
1822static const unsigned int canfd0_data_b_pins[] = {
1823 /* TX, RX */
1824 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1825};
1826static const unsigned int canfd0_data_b_mux[] = {
1827 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1828};
1829static const unsigned int canfd1_data_pins[] = {
1830 /* TX, RX */
1831 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1832};
1833static const unsigned int canfd1_data_mux[] = {
1834 CANFD1_TX_MARK, CANFD1_RX_MARK,
1835};
1836
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]1837/* - DRIF0 --------------------------------------------------------------- */
1838static const unsigned int drif0_ctrl_a_pins[] = {
1839 /* CLK, SYNC */
1840 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1841};
1842static const unsigned int drif0_ctrl_a_mux[] = {
1843 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1844};
1845static const unsigned int drif0_data0_a_pins[] = {
1846 /* D0 */
1847 RCAR_GP_PIN(6, 10),
1848};
1849static const unsigned int drif0_data0_a_mux[] = {
1850 RIF0_D0_A_MARK,
1851};
1852static const unsigned int drif0_data1_a_pins[] = {
1853 /* D1 */
1854 RCAR_GP_PIN(6, 7),
1855};
1856static const unsigned int drif0_data1_a_mux[] = {
1857 RIF0_D1_A_MARK,
1858};
1859static const unsigned int drif0_ctrl_b_pins[] = {
1860 /* CLK, SYNC */
1861 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1862};
1863static const unsigned int drif0_ctrl_b_mux[] = {
1864 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1865};
1866static const unsigned int drif0_data0_b_pins[] = {
1867 /* D0 */
1868 RCAR_GP_PIN(5, 1),
1869};
1870static const unsigned int drif0_data0_b_mux[] = {
1871 RIF0_D0_B_MARK,
1872};
1873static const unsigned int drif0_data1_b_pins[] = {
1874 /* D1 */
1875 RCAR_GP_PIN(5, 2),
1876};
1877static const unsigned int drif0_data1_b_mux[] = {
1878 RIF0_D1_B_MARK,
1879};
1880static const unsigned int drif0_ctrl_c_pins[] = {
1881 /* CLK, SYNC */
1882 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1883};
1884static const unsigned int drif0_ctrl_c_mux[] = {
1885 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1886};
1887static const unsigned int drif0_data0_c_pins[] = {
1888 /* D0 */
1889 RCAR_GP_PIN(5, 13),
1890};
1891static const unsigned int drif0_data0_c_mux[] = {
1892 RIF0_D0_C_MARK,
1893};
1894static const unsigned int drif0_data1_c_pins[] = {
1895 /* D1 */
1896 RCAR_GP_PIN(5, 14),
1897};
1898static const unsigned int drif0_data1_c_mux[] = {
1899 RIF0_D1_C_MARK,
1900};
1901/* - DRIF1 --------------------------------------------------------------- */
1902static const unsigned int drif1_ctrl_a_pins[] = {
1903 /* CLK, SYNC */
1904 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1905};
1906static const unsigned int drif1_ctrl_a_mux[] = {
1907 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1908};
1909static const unsigned int drif1_data0_a_pins[] = {
1910 /* D0 */
1911 RCAR_GP_PIN(6, 19),
1912};
1913static const unsigned int drif1_data0_a_mux[] = {
1914 RIF1_D0_A_MARK,
1915};
1916static const unsigned int drif1_data1_a_pins[] = {
1917 /* D1 */
1918 RCAR_GP_PIN(6, 20),
1919};
1920static const unsigned int drif1_data1_a_mux[] = {
1921 RIF1_D1_A_MARK,
1922};
1923static const unsigned int drif1_ctrl_b_pins[] = {
1924 /* CLK, SYNC */
1925 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1926};
1927static const unsigned int drif1_ctrl_b_mux[] = {
1928 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1929};
1930static const unsigned int drif1_data0_b_pins[] = {
1931 /* D0 */
1932 RCAR_GP_PIN(5, 7),
1933};
1934static const unsigned int drif1_data0_b_mux[] = {
1935 RIF1_D0_B_MARK,
1936};
1937static const unsigned int drif1_data1_b_pins[] = {
1938 /* D1 */
1939 RCAR_GP_PIN(5, 8),
1940};
1941static const unsigned int drif1_data1_b_mux[] = {
1942 RIF1_D1_B_MARK,
1943};
1944static const unsigned int drif1_ctrl_c_pins[] = {
1945 /* CLK, SYNC */
1946 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1947};
1948static const unsigned int drif1_ctrl_c_mux[] = {
1949 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1950};
1951static const unsigned int drif1_data0_c_pins[] = {
1952 /* D0 */
1953 RCAR_GP_PIN(5, 6),
1954};
1955static const unsigned int drif1_data0_c_mux[] = {
1956 RIF1_D0_C_MARK,
1957};
1958static const unsigned int drif1_data1_c_pins[] = {
1959 /* D1 */
1960 RCAR_GP_PIN(5, 10),
1961};
1962static const unsigned int drif1_data1_c_mux[] = {
1963 RIF1_D1_C_MARK,
1964};
1965/* - DRIF2 --------------------------------------------------------------- */
1966static const unsigned int drif2_ctrl_a_pins[] = {
1967 /* CLK, SYNC */
1968 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1969};
1970static const unsigned int drif2_ctrl_a_mux[] = {
1971 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1972};
1973static const unsigned int drif2_data0_a_pins[] = {
1974 /* D0 */
1975 RCAR_GP_PIN(6, 7),
1976};
1977static const unsigned int drif2_data0_a_mux[] = {
1978 RIF2_D0_A_MARK,
1979};
1980static const unsigned int drif2_data1_a_pins[] = {
1981 /* D1 */
1982 RCAR_GP_PIN(6, 10),
1983};
1984static const unsigned int drif2_data1_a_mux[] = {
1985 RIF2_D1_A_MARK,
1986};
1987static const unsigned int drif2_ctrl_b_pins[] = {
1988 /* CLK, SYNC */
1989 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1990};
1991static const unsigned int drif2_ctrl_b_mux[] = {
1992 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1993};
1994static const unsigned int drif2_data0_b_pins[] = {
1995 /* D0 */
1996 RCAR_GP_PIN(6, 30),
1997};
1998static const unsigned int drif2_data0_b_mux[] = {
1999 RIF2_D0_B_MARK,
2000};
2001static const unsigned int drif2_data1_b_pins[] = {
2002 /* D1 */
2003 RCAR_GP_PIN(6, 31),
2004};
2005static const unsigned int drif2_data1_b_mux[] = {
2006 RIF2_D1_B_MARK,
2007};
2008/* - DRIF3 --------------------------------------------------------------- */
2009static const unsigned int drif3_ctrl_a_pins[] = {
2010 /* CLK, SYNC */
2011 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2012};
2013static const unsigned int drif3_ctrl_a_mux[] = {
2014 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2015};
2016static const unsigned int drif3_data0_a_pins[] = {
2017 /* D0 */
2018 RCAR_GP_PIN(6, 19),
2019};
2020static const unsigned int drif3_data0_a_mux[] = {
2021 RIF3_D0_A_MARK,
2022};
2023static const unsigned int drif3_data1_a_pins[] = {
2024 /* D1 */
2025 RCAR_GP_PIN(6, 20),
2026};
2027static const unsigned int drif3_data1_a_mux[] = {
2028 RIF3_D1_A_MARK,
2029};
2030static const unsigned int drif3_ctrl_b_pins[] = {
2031 /* CLK, SYNC */
2032 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2033};
2034static const unsigned int drif3_ctrl_b_mux[] = {
2035 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2036};
2037static const unsigned int drif3_data0_b_pins[] = {
2038 /* D0 */
2039 RCAR_GP_PIN(6, 28),
2040};
2041static const unsigned int drif3_data0_b_mux[] = {
2042 RIF3_D0_B_MARK,
2043};
2044static const unsigned int drif3_data1_b_pins[] = {
2045 /* D1 */
2046 RCAR_GP_PIN(6, 29),
2047};
2048static const unsigned int drif3_data1_b_mux[] = {
2049 RIF3_D1_B_MARK,
2050};
2051
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]2052/* - DU --------------------------------------------------------------------- */
2053static const unsigned int du_rgb666_pins[] = {
2054 /* R[7:2], G[7:2], B[7:2] */
2055 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2056 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2057 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2058 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2059 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2060 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2061};
2062static const unsigned int du_rgb666_mux[] = {
2063 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2064 DU_DR3_MARK, DU_DR2_MARK,
2065 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2066 DU_DG3_MARK, DU_DG2_MARK,
2067 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2068 DU_DB3_MARK, DU_DB2_MARK,
2069};
2070static const unsigned int du_rgb888_pins[] = {
2071 /* R[7:0], G[7:0], B[7:0] */
2072 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2073 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2074 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2075 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2076 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2077 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2078 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2079 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2080 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2081};
2082static const unsigned int du_rgb888_mux[] = {
2083 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2084 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2085 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2086 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2087 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2088 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2089};
2090static const unsigned int du_clk_out_0_pins[] = {
2091 /* CLKOUT */
2092 RCAR_GP_PIN(1, 27),
2093};
2094static const unsigned int du_clk_out_0_mux[] = {
2095 DU_DOTCLKOUT0_MARK
2096};
2097static const unsigned int du_clk_out_1_pins[] = {
2098 /* CLKOUT */
2099 RCAR_GP_PIN(2, 3),
2100};
2101static const unsigned int du_clk_out_1_mux[] = {
2102 DU_DOTCLKOUT1_MARK
2103};
2104static const unsigned int du_sync_pins[] = {
2105 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2106 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2107};
2108static const unsigned int du_sync_mux[] = {
2109 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2110};
2111static const unsigned int du_oddf_pins[] = {
2112 /* EXDISP/EXODDF/EXCDE */
2113 RCAR_GP_PIN(2, 2),
2114};
2115static const unsigned int du_oddf_mux[] = {
2116 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2117};
2118static const unsigned int du_cde_pins[] = {
2119 /* CDE */
2120 RCAR_GP_PIN(2, 0),
2121};
2122static const unsigned int du_cde_mux[] = {
2123 DU_CDE_MARK,
2124};
2125static const unsigned int du_disp_pins[] = {
2126 /* DISP */
2127 RCAR_GP_PIN(2, 1),
2128};
2129static const unsigned int du_disp_mux[] = {
2130 DU_DISP_MARK,
2131};
2132
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame]2133/* - HDMI ------------------------------------------------------------------- */
2134static const unsigned int hdmi0_cec_pins[] = {
2135 /* HDMI0_CEC */
2136 RCAR_GP_PIN(7, 2),
2137};
2138static const unsigned int hdmi0_cec_mux[] = {
2139 HDMI0_CEC_MARK,
2140};
2141
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]2142/* - HSCIF0 ----------------------------------------------------------------- */
2143static const unsigned int hscif0_data_pins[] = {
2144 /* RX, TX */
2145 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2146};
2147static const unsigned int hscif0_data_mux[] = {
2148 HRX0_MARK, HTX0_MARK,
2149};
2150static const unsigned int hscif0_clk_pins[] = {
2151 /* SCK */
2152 RCAR_GP_PIN(5, 12),
2153};
2154static const unsigned int hscif0_clk_mux[] = {
2155 HSCK0_MARK,
2156};
2157static const unsigned int hscif0_ctrl_pins[] = {
2158 /* RTS, CTS */
2159 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2160};
2161static const unsigned int hscif0_ctrl_mux[] = {
2162 HRTS0_N_MARK, HCTS0_N_MARK,
2163};
2164/* - HSCIF1 ----------------------------------------------------------------- */
2165static const unsigned int hscif1_data_a_pins[] = {
2166 /* RX, TX */
2167 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2168};
2169static const unsigned int hscif1_data_a_mux[] = {
2170 HRX1_A_MARK, HTX1_A_MARK,
2171};
2172static const unsigned int hscif1_clk_a_pins[] = {
2173 /* SCK */
2174 RCAR_GP_PIN(6, 21),
2175};
2176static const unsigned int hscif1_clk_a_mux[] = {
2177 HSCK1_A_MARK,
2178};
2179static const unsigned int hscif1_ctrl_a_pins[] = {
2180 /* RTS, CTS */
2181 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2182};
2183static const unsigned int hscif1_ctrl_a_mux[] = {
2184 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2185};
2186
2187static const unsigned int hscif1_data_b_pins[] = {
2188 /* RX, TX */
2189 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2190};
2191static const unsigned int hscif1_data_b_mux[] = {
2192 HRX1_B_MARK, HTX1_B_MARK,
2193};
2194static const unsigned int hscif1_clk_b_pins[] = {
2195 /* SCK */
2196 RCAR_GP_PIN(5, 0),
2197};
2198static const unsigned int hscif1_clk_b_mux[] = {
2199 HSCK1_B_MARK,
2200};
2201static const unsigned int hscif1_ctrl_b_pins[] = {
2202 /* RTS, CTS */
2203 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2204};
2205static const unsigned int hscif1_ctrl_b_mux[] = {
2206 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2207};
2208/* - HSCIF2 ----------------------------------------------------------------- */
2209static const unsigned int hscif2_data_a_pins[] = {
2210 /* RX, TX */
2211 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2212};
2213static const unsigned int hscif2_data_a_mux[] = {
2214 HRX2_A_MARK, HTX2_A_MARK,
2215};
2216static const unsigned int hscif2_clk_a_pins[] = {
2217 /* SCK */
2218 RCAR_GP_PIN(6, 10),
2219};
2220static const unsigned int hscif2_clk_a_mux[] = {
2221 HSCK2_A_MARK,
2222};
2223static const unsigned int hscif2_ctrl_a_pins[] = {
2224 /* RTS, CTS */
2225 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2226};
2227static const unsigned int hscif2_ctrl_a_mux[] = {
2228 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2229};
2230
2231static const unsigned int hscif2_data_b_pins[] = {
2232 /* RX, TX */
2233 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2234};
2235static const unsigned int hscif2_data_b_mux[] = {
2236 HRX2_B_MARK, HTX2_B_MARK,
2237};
2238static const unsigned int hscif2_clk_b_pins[] = {
2239 /* SCK */
2240 RCAR_GP_PIN(6, 21),
2241};
2242static const unsigned int hscif2_clk_b_mux[] = {
2243 HSCK2_B_MARK,
2244};
2245static const unsigned int hscif2_ctrl_b_pins[] = {
2246 /* RTS, CTS */
2247 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2248};
2249static const unsigned int hscif2_ctrl_b_mux[] = {
2250 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2251};
2252
2253static const unsigned int hscif2_data_c_pins[] = {
2254 /* RX, TX */
2255 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2256};
2257static const unsigned int hscif2_data_c_mux[] = {
2258 HRX2_C_MARK, HTX2_C_MARK,
2259};
2260static const unsigned int hscif2_clk_c_pins[] = {
2261 /* SCK */
2262 RCAR_GP_PIN(6, 24),
2263};
2264static const unsigned int hscif2_clk_c_mux[] = {
2265 HSCK2_C_MARK,
2266};
2267static const unsigned int hscif2_ctrl_c_pins[] = {
2268 /* RTS, CTS */
2269 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2270};
2271static const unsigned int hscif2_ctrl_c_mux[] = {
2272 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2273};
2274/* - HSCIF3 ----------------------------------------------------------------- */
2275static const unsigned int hscif3_data_a_pins[] = {
2276 /* RX, TX */
2277 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2278};
2279static const unsigned int hscif3_data_a_mux[] = {
2280 HRX3_A_MARK, HTX3_A_MARK,
2281};
2282static const unsigned int hscif3_clk_pins[] = {
2283 /* SCK */
2284 RCAR_GP_PIN(1, 22),
2285};
2286static const unsigned int hscif3_clk_mux[] = {
2287 HSCK3_MARK,
2288};
2289static const unsigned int hscif3_ctrl_pins[] = {
2290 /* RTS, CTS */
2291 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2292};
2293static const unsigned int hscif3_ctrl_mux[] = {
2294 HRTS3_N_MARK, HCTS3_N_MARK,
2295};
2296
2297static const unsigned int hscif3_data_b_pins[] = {
2298 /* RX, TX */
2299 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2300};
2301static const unsigned int hscif3_data_b_mux[] = {
2302 HRX3_B_MARK, HTX3_B_MARK,
2303};
2304static const unsigned int hscif3_data_c_pins[] = {
2305 /* RX, TX */
2306 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2307};
2308static const unsigned int hscif3_data_c_mux[] = {
2309 HRX3_C_MARK, HTX3_C_MARK,
2310};
2311static const unsigned int hscif3_data_d_pins[] = {
2312 /* RX, TX */
2313 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2314};
2315static const unsigned int hscif3_data_d_mux[] = {
2316 HRX3_D_MARK, HTX3_D_MARK,
2317};
2318/* - HSCIF4 ----------------------------------------------------------------- */
2319static const unsigned int hscif4_data_a_pins[] = {
2320 /* RX, TX */
2321 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2322};
2323static const unsigned int hscif4_data_a_mux[] = {
2324 HRX4_A_MARK, HTX4_A_MARK,
2325};
2326static const unsigned int hscif4_clk_pins[] = {
2327 /* SCK */
2328 RCAR_GP_PIN(1, 11),
2329};
2330static const unsigned int hscif4_clk_mux[] = {
2331 HSCK4_MARK,
2332};
2333static const unsigned int hscif4_ctrl_pins[] = {
2334 /* RTS, CTS */
2335 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2336};
2337static const unsigned int hscif4_ctrl_mux[] = {
2338 HRTS4_N_MARK, HCTS4_N_MARK,
2339};
2340
2341static const unsigned int hscif4_data_b_pins[] = {
2342 /* RX, TX */
2343 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2344};
2345static const unsigned int hscif4_data_b_mux[] = {
2346 HRX4_B_MARK, HTX4_B_MARK,
2347};
2348
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]2349/* - I2C -------------------------------------------------------------------- */
2350static const unsigned int i2c1_a_pins[] = {
2351 /* SDA, SCL */
2352 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2353};
2354static const unsigned int i2c1_a_mux[] = {
2355 SDA1_A_MARK, SCL1_A_MARK,
2356};
2357static const unsigned int i2c1_b_pins[] = {
2358 /* SDA, SCL */
2359 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2360};
2361static const unsigned int i2c1_b_mux[] = {
2362 SDA1_B_MARK, SCL1_B_MARK,
2363};
2364static const unsigned int i2c2_a_pins[] = {
2365 /* SDA, SCL */
2366 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2367};
2368static const unsigned int i2c2_a_mux[] = {
2369 SDA2_A_MARK, SCL2_A_MARK,
2370};
2371static const unsigned int i2c2_b_pins[] = {
2372 /* SDA, SCL */
2373 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2374};
2375static const unsigned int i2c2_b_mux[] = {
2376 SDA2_B_MARK, SCL2_B_MARK,
2377};
2378static const unsigned int i2c6_a_pins[] = {
2379 /* SDA, SCL */
2380 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2381};
2382static const unsigned int i2c6_a_mux[] = {
2383 SDA6_A_MARK, SCL6_A_MARK,
2384};
2385static const unsigned int i2c6_b_pins[] = {
2386 /* SDA, SCL */
2387 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2388};
2389static const unsigned int i2c6_b_mux[] = {
2390 SDA6_B_MARK, SCL6_B_MARK,
2391};
2392static const unsigned int i2c6_c_pins[] = {
2393 /* SDA, SCL */
2394 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2395};
2396static const unsigned int i2c6_c_mux[] = {
2397 SDA6_C_MARK, SCL6_C_MARK,
2398};
2399
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]2400/* - INTC-EX ---------------------------------------------------------------- */
2401static const unsigned int intc_ex_irq0_pins[] = {
2402 /* IRQ0 */
2403 RCAR_GP_PIN(2, 0),
2404};
2405static const unsigned int intc_ex_irq0_mux[] = {
2406 IRQ0_MARK,
2407};
2408static const unsigned int intc_ex_irq1_pins[] = {
2409 /* IRQ1 */
2410 RCAR_GP_PIN(2, 1),
2411};
2412static const unsigned int intc_ex_irq1_mux[] = {
2413 IRQ1_MARK,
2414};
2415static const unsigned int intc_ex_irq2_pins[] = {
2416 /* IRQ2 */
2417 RCAR_GP_PIN(2, 2),
2418};
2419static const unsigned int intc_ex_irq2_mux[] = {
2420 IRQ2_MARK,
2421};
2422static const unsigned int intc_ex_irq3_pins[] = {
2423 /* IRQ3 */
2424 RCAR_GP_PIN(2, 3),
2425};
2426static const unsigned int intc_ex_irq3_mux[] = {
2427 IRQ3_MARK,
2428};
2429static const unsigned int intc_ex_irq4_pins[] = {
2430 /* IRQ4 */
2431 RCAR_GP_PIN(2, 4),
2432};
2433static const unsigned int intc_ex_irq4_mux[] = {
2434 IRQ4_MARK,
2435};
2436static const unsigned int intc_ex_irq5_pins[] = {
2437 /* IRQ5 */
2438 RCAR_GP_PIN(2, 5),
2439};
2440static const unsigned int intc_ex_irq5_mux[] = {
2441 IRQ5_MARK,
2442};
2443
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]2444/* - MSIOF0 ----------------------------------------------------------------- */
2445static const unsigned int msiof0_clk_pins[] = {
2446 /* SCK */
2447 RCAR_GP_PIN(5, 17),
2448};
2449static const unsigned int msiof0_clk_mux[] = {
2450 MSIOF0_SCK_MARK,
2451};
2452static const unsigned int msiof0_sync_pins[] = {
2453 /* SYNC */
2454 RCAR_GP_PIN(5, 18),
2455};
2456static const unsigned int msiof0_sync_mux[] = {
2457 MSIOF0_SYNC_MARK,
2458};
2459static const unsigned int msiof0_ss1_pins[] = {
2460 /* SS1 */
2461 RCAR_GP_PIN(5, 19),
2462};
2463static const unsigned int msiof0_ss1_mux[] = {
2464 MSIOF0_SS1_MARK,
2465};
2466static const unsigned int msiof0_ss2_pins[] = {
2467 /* SS2 */
2468 RCAR_GP_PIN(5, 21),
2469};
2470static const unsigned int msiof0_ss2_mux[] = {
2471 MSIOF0_SS2_MARK,
2472};
2473static const unsigned int msiof0_txd_pins[] = {
2474 /* TXD */
2475 RCAR_GP_PIN(5, 20),
2476};
2477static const unsigned int msiof0_txd_mux[] = {
2478 MSIOF0_TXD_MARK,
2479};
2480static const unsigned int msiof0_rxd_pins[] = {
2481 /* RXD */
2482 RCAR_GP_PIN(5, 22),
2483};
2484static const unsigned int msiof0_rxd_mux[] = {
2485 MSIOF0_RXD_MARK,
2486};
2487/* - MSIOF1 ----------------------------------------------------------------- */
2488static const unsigned int msiof1_clk_a_pins[] = {
2489 /* SCK */
2490 RCAR_GP_PIN(6, 8),
2491};
2492static const unsigned int msiof1_clk_a_mux[] = {
2493 MSIOF1_SCK_A_MARK,
2494};
2495static const unsigned int msiof1_sync_a_pins[] = {
2496 /* SYNC */
2497 RCAR_GP_PIN(6, 9),
2498};
2499static const unsigned int msiof1_sync_a_mux[] = {
2500 MSIOF1_SYNC_A_MARK,
2501};
2502static const unsigned int msiof1_ss1_a_pins[] = {
2503 /* SS1 */
2504 RCAR_GP_PIN(6, 5),
2505};
2506static const unsigned int msiof1_ss1_a_mux[] = {
2507 MSIOF1_SS1_A_MARK,
2508};
2509static const unsigned int msiof1_ss2_a_pins[] = {
2510 /* SS2 */
2511 RCAR_GP_PIN(6, 6),
2512};
2513static const unsigned int msiof1_ss2_a_mux[] = {
2514 MSIOF1_SS2_A_MARK,
2515};
2516static const unsigned int msiof1_txd_a_pins[] = {
2517 /* TXD */
2518 RCAR_GP_PIN(6, 7),
2519};
2520static const unsigned int msiof1_txd_a_mux[] = {
2521 MSIOF1_TXD_A_MARK,
2522};
2523static const unsigned int msiof1_rxd_a_pins[] = {
2524 /* RXD */
2525 RCAR_GP_PIN(6, 10),
2526};
2527static const unsigned int msiof1_rxd_a_mux[] = {
2528 MSIOF1_RXD_A_MARK,
2529};
2530static const unsigned int msiof1_clk_b_pins[] = {
2531 /* SCK */
2532 RCAR_GP_PIN(5, 9),
2533};
2534static const unsigned int msiof1_clk_b_mux[] = {
2535 MSIOF1_SCK_B_MARK,
2536};
2537static const unsigned int msiof1_sync_b_pins[] = {
2538 /* SYNC */
2539 RCAR_GP_PIN(5, 3),
2540};
2541static const unsigned int msiof1_sync_b_mux[] = {
2542 MSIOF1_SYNC_B_MARK,
2543};
2544static const unsigned int msiof1_ss1_b_pins[] = {
2545 /* SS1 */
2546 RCAR_GP_PIN(5, 4),
2547};
2548static const unsigned int msiof1_ss1_b_mux[] = {
2549 MSIOF1_SS1_B_MARK,
2550};
2551static const unsigned int msiof1_ss2_b_pins[] = {
2552 /* SS2 */
2553 RCAR_GP_PIN(5, 0),
2554};
2555static const unsigned int msiof1_ss2_b_mux[] = {
2556 MSIOF1_SS2_B_MARK,
2557};
2558static const unsigned int msiof1_txd_b_pins[] = {
2559 /* TXD */
2560 RCAR_GP_PIN(5, 8),
2561};
2562static const unsigned int msiof1_txd_b_mux[] = {
2563 MSIOF1_TXD_B_MARK,
2564};
2565static const unsigned int msiof1_rxd_b_pins[] = {
2566 /* RXD */
2567 RCAR_GP_PIN(5, 7),
2568};
2569static const unsigned int msiof1_rxd_b_mux[] = {
2570 MSIOF1_RXD_B_MARK,
2571};
2572static const unsigned int msiof1_clk_c_pins[] = {
2573 /* SCK */
2574 RCAR_GP_PIN(6, 17),
2575};
2576static const unsigned int msiof1_clk_c_mux[] = {
2577 MSIOF1_SCK_C_MARK,
2578};
2579static const unsigned int msiof1_sync_c_pins[] = {
2580 /* SYNC */
2581 RCAR_GP_PIN(6, 18),
2582};
2583static const unsigned int msiof1_sync_c_mux[] = {
2584 MSIOF1_SYNC_C_MARK,
2585};
2586static const unsigned int msiof1_ss1_c_pins[] = {
2587 /* SS1 */
2588 RCAR_GP_PIN(6, 21),
2589};
2590static const unsigned int msiof1_ss1_c_mux[] = {
2591 MSIOF1_SS1_C_MARK,
2592};
2593static const unsigned int msiof1_ss2_c_pins[] = {
2594 /* SS2 */
2595 RCAR_GP_PIN(6, 27),
2596};
2597static const unsigned int msiof1_ss2_c_mux[] = {
2598 MSIOF1_SS2_C_MARK,
2599};
2600static const unsigned int msiof1_txd_c_pins[] = {
2601 /* TXD */
2602 RCAR_GP_PIN(6, 20),
2603};
2604static const unsigned int msiof1_txd_c_mux[] = {
2605 MSIOF1_TXD_C_MARK,
2606};
2607static const unsigned int msiof1_rxd_c_pins[] = {
2608 /* RXD */
2609 RCAR_GP_PIN(6, 19),
2610};
2611static const unsigned int msiof1_rxd_c_mux[] = {
2612 MSIOF1_RXD_C_MARK,
2613};
2614static const unsigned int msiof1_clk_d_pins[] = {
2615 /* SCK */
2616 RCAR_GP_PIN(5, 12),
2617};
2618static const unsigned int msiof1_clk_d_mux[] = {
2619 MSIOF1_SCK_D_MARK,
2620};
2621static const unsigned int msiof1_sync_d_pins[] = {
2622 /* SYNC */
2623 RCAR_GP_PIN(5, 15),
2624};
2625static const unsigned int msiof1_sync_d_mux[] = {
2626 MSIOF1_SYNC_D_MARK,
2627};
2628static const unsigned int msiof1_ss1_d_pins[] = {
2629 /* SS1 */
2630 RCAR_GP_PIN(5, 16),
2631};
2632static const unsigned int msiof1_ss1_d_mux[] = {
2633 MSIOF1_SS1_D_MARK,
2634};
2635static const unsigned int msiof1_ss2_d_pins[] = {
2636 /* SS2 */
2637 RCAR_GP_PIN(5, 21),
2638};
2639static const unsigned int msiof1_ss2_d_mux[] = {
2640 MSIOF1_SS2_D_MARK,
2641};
2642static const unsigned int msiof1_txd_d_pins[] = {
2643 /* TXD */
2644 RCAR_GP_PIN(5, 14),
2645};
2646static const unsigned int msiof1_txd_d_mux[] = {
2647 MSIOF1_TXD_D_MARK,
2648};
2649static const unsigned int msiof1_rxd_d_pins[] = {
2650 /* RXD */
2651 RCAR_GP_PIN(5, 13),
2652};
2653static const unsigned int msiof1_rxd_d_mux[] = {
2654 MSIOF1_RXD_D_MARK,
2655};
2656static const unsigned int msiof1_clk_e_pins[] = {
2657 /* SCK */
2658 RCAR_GP_PIN(3, 0),
2659};
2660static const unsigned int msiof1_clk_e_mux[] = {
2661 MSIOF1_SCK_E_MARK,
2662};
2663static const unsigned int msiof1_sync_e_pins[] = {
2664 /* SYNC */
2665 RCAR_GP_PIN(3, 1),
2666};
2667static const unsigned int msiof1_sync_e_mux[] = {
2668 MSIOF1_SYNC_E_MARK,
2669};
2670static const unsigned int msiof1_ss1_e_pins[] = {
2671 /* SS1 */
2672 RCAR_GP_PIN(3, 4),
2673};
2674static const unsigned int msiof1_ss1_e_mux[] = {
2675 MSIOF1_SS1_E_MARK,
2676};
2677static const unsigned int msiof1_ss2_e_pins[] = {
2678 /* SS2 */
2679 RCAR_GP_PIN(3, 5),
2680};
2681static const unsigned int msiof1_ss2_e_mux[] = {
2682 MSIOF1_SS2_E_MARK,
2683};
2684static const unsigned int msiof1_txd_e_pins[] = {
2685 /* TXD */
2686 RCAR_GP_PIN(3, 3),
2687};
2688static const unsigned int msiof1_txd_e_mux[] = {
2689 MSIOF1_TXD_E_MARK,
2690};
2691static const unsigned int msiof1_rxd_e_pins[] = {
2692 /* RXD */
2693 RCAR_GP_PIN(3, 2),
2694};
2695static const unsigned int msiof1_rxd_e_mux[] = {
2696 MSIOF1_RXD_E_MARK,
2697};
2698static const unsigned int msiof1_clk_f_pins[] = {
2699 /* SCK */
2700 RCAR_GP_PIN(5, 23),
2701};
2702static const unsigned int msiof1_clk_f_mux[] = {
2703 MSIOF1_SCK_F_MARK,
2704};
2705static const unsigned int msiof1_sync_f_pins[] = {
2706 /* SYNC */
2707 RCAR_GP_PIN(5, 24),
2708};
2709static const unsigned int msiof1_sync_f_mux[] = {
2710 MSIOF1_SYNC_F_MARK,
2711};
2712static const unsigned int msiof1_ss1_f_pins[] = {
2713 /* SS1 */
2714 RCAR_GP_PIN(6, 1),
2715};
2716static const unsigned int msiof1_ss1_f_mux[] = {
2717 MSIOF1_SS1_F_MARK,
2718};
2719static const unsigned int msiof1_ss2_f_pins[] = {
2720 /* SS2 */
2721 RCAR_GP_PIN(6, 2),
2722};
2723static const unsigned int msiof1_ss2_f_mux[] = {
2724 MSIOF1_SS2_F_MARK,
2725};
2726static const unsigned int msiof1_txd_f_pins[] = {
2727 /* TXD */
2728 RCAR_GP_PIN(6, 0),
2729};
2730static const unsigned int msiof1_txd_f_mux[] = {
2731 MSIOF1_TXD_F_MARK,
2732};
2733static const unsigned int msiof1_rxd_f_pins[] = {
2734 /* RXD */
2735 RCAR_GP_PIN(5, 25),
2736};
2737static const unsigned int msiof1_rxd_f_mux[] = {
2738 MSIOF1_RXD_F_MARK,
2739};
2740static const unsigned int msiof1_clk_g_pins[] = {
2741 /* SCK */
2742 RCAR_GP_PIN(3, 6),
2743};
2744static const unsigned int msiof1_clk_g_mux[] = {
2745 MSIOF1_SCK_G_MARK,
2746};
2747static const unsigned int msiof1_sync_g_pins[] = {
2748 /* SYNC */
2749 RCAR_GP_PIN(3, 7),
2750};
2751static const unsigned int msiof1_sync_g_mux[] = {
2752 MSIOF1_SYNC_G_MARK,
2753};
2754static const unsigned int msiof1_ss1_g_pins[] = {
2755 /* SS1 */
2756 RCAR_GP_PIN(3, 10),
2757};
2758static const unsigned int msiof1_ss1_g_mux[] = {
2759 MSIOF1_SS1_G_MARK,
2760};
2761static const unsigned int msiof1_ss2_g_pins[] = {
2762 /* SS2 */
2763 RCAR_GP_PIN(3, 11),
2764};
2765static const unsigned int msiof1_ss2_g_mux[] = {
2766 MSIOF1_SS2_G_MARK,
2767};
2768static const unsigned int msiof1_txd_g_pins[] = {
2769 /* TXD */
2770 RCAR_GP_PIN(3, 9),
2771};
2772static const unsigned int msiof1_txd_g_mux[] = {
2773 MSIOF1_TXD_G_MARK,
2774};
2775static const unsigned int msiof1_rxd_g_pins[] = {
2776 /* RXD */
2777 RCAR_GP_PIN(3, 8),
2778};
2779static const unsigned int msiof1_rxd_g_mux[] = {
2780 MSIOF1_RXD_G_MARK,
2781};
2782/* - MSIOF2 ----------------------------------------------------------------- */
2783static const unsigned int msiof2_clk_a_pins[] = {
2784 /* SCK */
2785 RCAR_GP_PIN(1, 9),
2786};
2787static const unsigned int msiof2_clk_a_mux[] = {
2788 MSIOF2_SCK_A_MARK,
2789};
2790static const unsigned int msiof2_sync_a_pins[] = {
2791 /* SYNC */
2792 RCAR_GP_PIN(1, 8),
2793};
2794static const unsigned int msiof2_sync_a_mux[] = {
2795 MSIOF2_SYNC_A_MARK,
2796};
2797static const unsigned int msiof2_ss1_a_pins[] = {
2798 /* SS1 */
2799 RCAR_GP_PIN(1, 6),
2800};
2801static const unsigned int msiof2_ss1_a_mux[] = {
2802 MSIOF2_SS1_A_MARK,
2803};
2804static const unsigned int msiof2_ss2_a_pins[] = {
2805 /* SS2 */
2806 RCAR_GP_PIN(1, 7),
2807};
2808static const unsigned int msiof2_ss2_a_mux[] = {
2809 MSIOF2_SS2_A_MARK,
2810};
2811static const unsigned int msiof2_txd_a_pins[] = {
2812 /* TXD */
2813 RCAR_GP_PIN(1, 11),
2814};
2815static const unsigned int msiof2_txd_a_mux[] = {
2816 MSIOF2_TXD_A_MARK,
2817};
2818static const unsigned int msiof2_rxd_a_pins[] = {
2819 /* RXD */
2820 RCAR_GP_PIN(1, 10),
2821};
2822static const unsigned int msiof2_rxd_a_mux[] = {
2823 MSIOF2_RXD_A_MARK,
2824};
2825static const unsigned int msiof2_clk_b_pins[] = {
2826 /* SCK */
2827 RCAR_GP_PIN(0, 4),
2828};
2829static const unsigned int msiof2_clk_b_mux[] = {
2830 MSIOF2_SCK_B_MARK,
2831};
2832static const unsigned int msiof2_sync_b_pins[] = {
2833 /* SYNC */
2834 RCAR_GP_PIN(0, 5),
2835};
2836static const unsigned int msiof2_sync_b_mux[] = {
2837 MSIOF2_SYNC_B_MARK,
2838};
2839static const unsigned int msiof2_ss1_b_pins[] = {
2840 /* SS1 */
2841 RCAR_GP_PIN(0, 0),
2842};
2843static const unsigned int msiof2_ss1_b_mux[] = {
2844 MSIOF2_SS1_B_MARK,
2845};
2846static const unsigned int msiof2_ss2_b_pins[] = {
2847 /* SS2 */
2848 RCAR_GP_PIN(0, 1),
2849};
2850static const unsigned int msiof2_ss2_b_mux[] = {
2851 MSIOF2_SS2_B_MARK,
2852};
2853static const unsigned int msiof2_txd_b_pins[] = {
2854 /* TXD */
2855 RCAR_GP_PIN(0, 7),
2856};
2857static const unsigned int msiof2_txd_b_mux[] = {
2858 MSIOF2_TXD_B_MARK,
2859};
2860static const unsigned int msiof2_rxd_b_pins[] = {
2861 /* RXD */
2862 RCAR_GP_PIN(0, 6),
2863};
2864static const unsigned int msiof2_rxd_b_mux[] = {
2865 MSIOF2_RXD_B_MARK,
2866};
2867static const unsigned int msiof2_clk_c_pins[] = {
2868 /* SCK */
2869 RCAR_GP_PIN(2, 12),
2870};
2871static const unsigned int msiof2_clk_c_mux[] = {
2872 MSIOF2_SCK_C_MARK,
2873};
2874static const unsigned int msiof2_sync_c_pins[] = {
2875 /* SYNC */
2876 RCAR_GP_PIN(2, 11),
2877};
2878static const unsigned int msiof2_sync_c_mux[] = {
2879 MSIOF2_SYNC_C_MARK,
2880};
2881static const unsigned int msiof2_ss1_c_pins[] = {
2882 /* SS1 */
2883 RCAR_GP_PIN(2, 10),
2884};
2885static const unsigned int msiof2_ss1_c_mux[] = {
2886 MSIOF2_SS1_C_MARK,
2887};
2888static const unsigned int msiof2_ss2_c_pins[] = {
2889 /* SS2 */
2890 RCAR_GP_PIN(2, 9),
2891};
2892static const unsigned int msiof2_ss2_c_mux[] = {
2893 MSIOF2_SS2_C_MARK,
2894};
2895static const unsigned int msiof2_txd_c_pins[] = {
2896 /* TXD */
2897 RCAR_GP_PIN(2, 14),
2898};
2899static const unsigned int msiof2_txd_c_mux[] = {
2900 MSIOF2_TXD_C_MARK,
2901};
2902static const unsigned int msiof2_rxd_c_pins[] = {
2903 /* RXD */
2904 RCAR_GP_PIN(2, 13),
2905};
2906static const unsigned int msiof2_rxd_c_mux[] = {
2907 MSIOF2_RXD_C_MARK,
2908};
2909static const unsigned int msiof2_clk_d_pins[] = {
2910 /* SCK */
2911 RCAR_GP_PIN(0, 8),
2912};
2913static const unsigned int msiof2_clk_d_mux[] = {
2914 MSIOF2_SCK_D_MARK,
2915};
2916static const unsigned int msiof2_sync_d_pins[] = {
2917 /* SYNC */
2918 RCAR_GP_PIN(0, 9),
2919};
2920static const unsigned int msiof2_sync_d_mux[] = {
2921 MSIOF2_SYNC_D_MARK,
2922};
2923static const unsigned int msiof2_ss1_d_pins[] = {
2924 /* SS1 */
2925 RCAR_GP_PIN(0, 12),
2926};
2927static const unsigned int msiof2_ss1_d_mux[] = {
2928 MSIOF2_SS1_D_MARK,
2929};
2930static const unsigned int msiof2_ss2_d_pins[] = {
2931 /* SS2 */
2932 RCAR_GP_PIN(0, 13),
2933};
2934static const unsigned int msiof2_ss2_d_mux[] = {
2935 MSIOF2_SS2_D_MARK,
2936};
2937static const unsigned int msiof2_txd_d_pins[] = {
2938 /* TXD */
2939 RCAR_GP_PIN(0, 11),
2940};
2941static const unsigned int msiof2_txd_d_mux[] = {
2942 MSIOF2_TXD_D_MARK,
2943};
2944static const unsigned int msiof2_rxd_d_pins[] = {
2945 /* RXD */
2946 RCAR_GP_PIN(0, 10),
2947};
2948static const unsigned int msiof2_rxd_d_mux[] = {
2949 MSIOF2_RXD_D_MARK,
2950};
2951/* - MSIOF3 ----------------------------------------------------------------- */
2952static const unsigned int msiof3_clk_a_pins[] = {
2953 /* SCK */
2954 RCAR_GP_PIN(0, 0),
2955};
2956static const unsigned int msiof3_clk_a_mux[] = {
2957 MSIOF3_SCK_A_MARK,
2958};
2959static const unsigned int msiof3_sync_a_pins[] = {
2960 /* SYNC */
2961 RCAR_GP_PIN(0, 1),
2962};
2963static const unsigned int msiof3_sync_a_mux[] = {
2964 MSIOF3_SYNC_A_MARK,
2965};
2966static const unsigned int msiof3_ss1_a_pins[] = {
2967 /* SS1 */
2968 RCAR_GP_PIN(0, 14),
2969};
2970static const unsigned int msiof3_ss1_a_mux[] = {
2971 MSIOF3_SS1_A_MARK,
2972};
2973static const unsigned int msiof3_ss2_a_pins[] = {
2974 /* SS2 */
2975 RCAR_GP_PIN(0, 15),
2976};
2977static const unsigned int msiof3_ss2_a_mux[] = {
2978 MSIOF3_SS2_A_MARK,
2979};
2980static const unsigned int msiof3_txd_a_pins[] = {
2981 /* TXD */
2982 RCAR_GP_PIN(0, 3),
2983};
2984static const unsigned int msiof3_txd_a_mux[] = {
2985 MSIOF3_TXD_A_MARK,
2986};
2987static const unsigned int msiof3_rxd_a_pins[] = {
2988 /* RXD */
2989 RCAR_GP_PIN(0, 2),
2990};
2991static const unsigned int msiof3_rxd_a_mux[] = {
2992 MSIOF3_RXD_A_MARK,
2993};
2994static const unsigned int msiof3_clk_b_pins[] = {
2995 /* SCK */
2996 RCAR_GP_PIN(1, 2),
2997};
2998static const unsigned int msiof3_clk_b_mux[] = {
2999 MSIOF3_SCK_B_MARK,
3000};
3001static const unsigned int msiof3_sync_b_pins[] = {
3002 /* SYNC */
3003 RCAR_GP_PIN(1, 0),
3004};
3005static const unsigned int msiof3_sync_b_mux[] = {
3006 MSIOF3_SYNC_B_MARK,
3007};
3008static const unsigned int msiof3_ss1_b_pins[] = {
3009 /* SS1 */
3010 RCAR_GP_PIN(1, 4),
3011};
3012static const unsigned int msiof3_ss1_b_mux[] = {
3013 MSIOF3_SS1_B_MARK,
3014};
3015static const unsigned int msiof3_ss2_b_pins[] = {
3016 /* SS2 */
3017 RCAR_GP_PIN(1, 5),
3018};
3019static const unsigned int msiof3_ss2_b_mux[] = {
3020 MSIOF3_SS2_B_MARK,
3021};
3022static const unsigned int msiof3_txd_b_pins[] = {
3023 /* TXD */
3024 RCAR_GP_PIN(1, 1),
3025};
3026static const unsigned int msiof3_txd_b_mux[] = {
3027 MSIOF3_TXD_B_MARK,
3028};
3029static const unsigned int msiof3_rxd_b_pins[] = {
3030 /* RXD */
3031 RCAR_GP_PIN(1, 3),
3032};
3033static const unsigned int msiof3_rxd_b_mux[] = {
3034 MSIOF3_RXD_B_MARK,
3035};
3036static const unsigned int msiof3_clk_c_pins[] = {
3037 /* SCK */
3038 RCAR_GP_PIN(1, 12),
3039};
3040static const unsigned int msiof3_clk_c_mux[] = {
3041 MSIOF3_SCK_C_MARK,
3042};
3043static const unsigned int msiof3_sync_c_pins[] = {
3044 /* SYNC */
3045 RCAR_GP_PIN(1, 13),
3046};
3047static const unsigned int msiof3_sync_c_mux[] = {
3048 MSIOF3_SYNC_C_MARK,
3049};
3050static const unsigned int msiof3_txd_c_pins[] = {
3051 /* TXD */
3052 RCAR_GP_PIN(1, 15),
3053};
3054static const unsigned int msiof3_txd_c_mux[] = {
3055 MSIOF3_TXD_C_MARK,
3056};
3057static const unsigned int msiof3_rxd_c_pins[] = {
3058 /* RXD */
3059 RCAR_GP_PIN(1, 14),
3060};
3061static const unsigned int msiof3_rxd_c_mux[] = {
3062 MSIOF3_RXD_C_MARK,
3063};
3064static const unsigned int msiof3_clk_d_pins[] = {
3065 /* SCK */
3066 RCAR_GP_PIN(1, 22),
3067};
3068static const unsigned int msiof3_clk_d_mux[] = {
3069 MSIOF3_SCK_D_MARK,
3070};
3071static const unsigned int msiof3_sync_d_pins[] = {
3072 /* SYNC */
3073 RCAR_GP_PIN(1, 23),
3074};
3075static const unsigned int msiof3_sync_d_mux[] = {
3076 MSIOF3_SYNC_D_MARK,
3077};
3078static const unsigned int msiof3_ss1_d_pins[] = {
3079 /* SS1 */
3080 RCAR_GP_PIN(1, 26),
3081};
3082static const unsigned int msiof3_ss1_d_mux[] = {
3083 MSIOF3_SS1_D_MARK,
3084};
3085static const unsigned int msiof3_txd_d_pins[] = {
3086 /* TXD */
3087 RCAR_GP_PIN(1, 25),
3088};
3089static const unsigned int msiof3_txd_d_mux[] = {
3090 MSIOF3_TXD_D_MARK,
3091};
3092static const unsigned int msiof3_rxd_d_pins[] = {
3093 /* RXD */
3094 RCAR_GP_PIN(1, 24),
3095};
3096static const unsigned int msiof3_rxd_d_mux[] = {
3097 MSIOF3_RXD_D_MARK,
3098};
3099
3100static const unsigned int msiof3_clk_e_pins[] = {
3101 /* SCK */
3102 RCAR_GP_PIN(2, 3),
3103};
3104static const unsigned int msiof3_clk_e_mux[] = {
3105 MSIOF3_SCK_E_MARK,
3106};
3107static const unsigned int msiof3_sync_e_pins[] = {
3108 /* SYNC */
3109 RCAR_GP_PIN(2, 2),
3110};
3111static const unsigned int msiof3_sync_e_mux[] = {
3112 MSIOF3_SYNC_E_MARK,
3113};
3114static const unsigned int msiof3_ss1_e_pins[] = {
3115 /* SS1 */
3116 RCAR_GP_PIN(2, 1),
3117};
3118static const unsigned int msiof3_ss1_e_mux[] = {
3119 MSIOF3_SS1_E_MARK,
3120};
3121static const unsigned int msiof3_ss2_e_pins[] = {
Geert Uytterhoevenfff8e332018-03-22 15:01:53 +0100[diff] [blame]3122 /* SS2 */
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]3123 RCAR_GP_PIN(2, 0),
3124};
3125static const unsigned int msiof3_ss2_e_mux[] = {
Geert Uytterhoevenb6db6bf2017-07-11 11:56:24 +0200[diff] [blame]3126 MSIOF3_SS2_E_MARK,
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]3127};
3128static const unsigned int msiof3_txd_e_pins[] = {
3129 /* TXD */
3130 RCAR_GP_PIN(2, 5),
3131};
3132static const unsigned int msiof3_txd_e_mux[] = {
3133 MSIOF3_TXD_E_MARK,
3134};
3135static const unsigned int msiof3_rxd_e_pins[] = {
3136 /* RXD */
3137 RCAR_GP_PIN(2, 4),
3138};
3139static const unsigned int msiof3_rxd_e_mux[] = {
3140 MSIOF3_RXD_E_MARK,
3141};
3142
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]3143/* - PWM0 --------------------------------------------------------------------*/
3144static const unsigned int pwm0_pins[] = {
3145 /* PWM */
3146 RCAR_GP_PIN(2, 6),
3147};
3148static const unsigned int pwm0_mux[] = {
3149 PWM0_MARK,
3150};
3151/* - PWM1 --------------------------------------------------------------------*/
3152static const unsigned int pwm1_a_pins[] = {
3153 /* PWM */
3154 RCAR_GP_PIN(2, 7),
3155};
3156static const unsigned int pwm1_a_mux[] = {
3157 PWM1_A_MARK,
3158};
3159static const unsigned int pwm1_b_pins[] = {
3160 /* PWM */
3161 RCAR_GP_PIN(1, 8),
3162};
3163static const unsigned int pwm1_b_mux[] = {
3164 PWM1_B_MARK,
3165};
3166/* - PWM2 --------------------------------------------------------------------*/
3167static const unsigned int pwm2_a_pins[] = {
3168 /* PWM */
3169 RCAR_GP_PIN(2, 8),
3170};
3171static const unsigned int pwm2_a_mux[] = {
3172 PWM2_A_MARK,
3173};
3174static const unsigned int pwm2_b_pins[] = {
3175 /* PWM */
3176 RCAR_GP_PIN(1, 11),
3177};
3178static const unsigned int pwm2_b_mux[] = {
3179 PWM2_B_MARK,
3180};
3181/* - PWM3 --------------------------------------------------------------------*/
3182static const unsigned int pwm3_a_pins[] = {
3183 /* PWM */
3184 RCAR_GP_PIN(1, 0),
3185};
3186static const unsigned int pwm3_a_mux[] = {
3187 PWM3_A_MARK,
3188};
3189static const unsigned int pwm3_b_pins[] = {
3190 /* PWM */
3191 RCAR_GP_PIN(2, 2),
3192};
3193static const unsigned int pwm3_b_mux[] = {
3194 PWM3_B_MARK,
3195};
3196/* - PWM4 --------------------------------------------------------------------*/
3197static const unsigned int pwm4_a_pins[] = {
3198 /* PWM */
3199 RCAR_GP_PIN(1, 1),
3200};
3201static const unsigned int pwm4_a_mux[] = {
3202 PWM4_A_MARK,
3203};
3204static const unsigned int pwm4_b_pins[] = {
3205 /* PWM */
3206 RCAR_GP_PIN(2, 3),
3207};
3208static const unsigned int pwm4_b_mux[] = {
3209 PWM4_B_MARK,
3210};
3211/* - PWM5 --------------------------------------------------------------------*/
3212static const unsigned int pwm5_a_pins[] = {
3213 /* PWM */
3214 RCAR_GP_PIN(1, 2),
3215};
3216static const unsigned int pwm5_a_mux[] = {
3217 PWM5_A_MARK,
3218};
3219static const unsigned int pwm5_b_pins[] = {
3220 /* PWM */
3221 RCAR_GP_PIN(2, 4),
3222};
3223static const unsigned int pwm5_b_mux[] = {
3224 PWM5_B_MARK,
3225};
3226/* - PWM6 --------------------------------------------------------------------*/
3227static const unsigned int pwm6_a_pins[] = {
3228 /* PWM */
3229 RCAR_GP_PIN(1, 3),
3230};
3231static const unsigned int pwm6_a_mux[] = {
3232 PWM6_A_MARK,
3233};
3234static const unsigned int pwm6_b_pins[] = {
3235 /* PWM */
3236 RCAR_GP_PIN(2, 5),
3237};
3238static const unsigned int pwm6_b_mux[] = {
3239 PWM6_B_MARK,
3240};
3241
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3242/* - SCIF0 ------------------------------------------------------------------ */
3243static const unsigned int scif0_data_pins[] = {
3244 /* RX, TX */
3245 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3246};
3247static const unsigned int scif0_data_mux[] = {
3248 RX0_MARK, TX0_MARK,
3249};
3250static const unsigned int scif0_clk_pins[] = {
3251 /* SCK */
3252 RCAR_GP_PIN(5, 0),
3253};
3254static const unsigned int scif0_clk_mux[] = {
3255 SCK0_MARK,
3256};
3257static const unsigned int scif0_ctrl_pins[] = {
3258 /* RTS, CTS */
3259 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3260};
3261static const unsigned int scif0_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3262 RTS0_N_MARK, CTS0_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3263};
3264/* - SCIF1 ------------------------------------------------------------------ */
3265static const unsigned int scif1_data_a_pins[] = {
3266 /* RX, TX */
3267 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3268};
3269static const unsigned int scif1_data_a_mux[] = {
3270 RX1_A_MARK, TX1_A_MARK,
3271};
3272static const unsigned int scif1_clk_pins[] = {
3273 /* SCK */
3274 RCAR_GP_PIN(6, 21),
3275};
3276static const unsigned int scif1_clk_mux[] = {
3277 SCK1_MARK,
3278};
3279static const unsigned int scif1_ctrl_pins[] = {
3280 /* RTS, CTS */
3281 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3282};
3283static const unsigned int scif1_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3284 RTS1_N_MARK, CTS1_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3285};
3286
3287static const unsigned int scif1_data_b_pins[] = {
3288 /* RX, TX */
3289 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3290};
3291static const unsigned int scif1_data_b_mux[] = {
3292 RX1_B_MARK, TX1_B_MARK,
3293};
3294/* - SCIF2 ------------------------------------------------------------------ */
3295static const unsigned int scif2_data_a_pins[] = {
3296 /* RX, TX */
3297 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3298};
3299static const unsigned int scif2_data_a_mux[] = {
3300 RX2_A_MARK, TX2_A_MARK,
3301};
3302static const unsigned int scif2_clk_pins[] = {
3303 /* SCK */
3304 RCAR_GP_PIN(5, 9),
3305};
3306static const unsigned int scif2_clk_mux[] = {
3307 SCK2_MARK,
3308};
3309static const unsigned int scif2_data_b_pins[] = {
3310 /* RX, TX */
3311 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3312};
3313static const unsigned int scif2_data_b_mux[] = {
3314 RX2_B_MARK, TX2_B_MARK,
3315};
3316/* - SCIF3 ------------------------------------------------------------------ */
3317static const unsigned int scif3_data_a_pins[] = {
3318 /* RX, TX */
3319 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3320};
3321static const unsigned int scif3_data_a_mux[] = {
3322 RX3_A_MARK, TX3_A_MARK,
3323};
3324static const unsigned int scif3_clk_pins[] = {
3325 /* SCK */
3326 RCAR_GP_PIN(1, 22),
3327};
3328static const unsigned int scif3_clk_mux[] = {
3329 SCK3_MARK,
3330};
3331static const unsigned int scif3_ctrl_pins[] = {
3332 /* RTS, CTS */
3333 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3334};
3335static const unsigned int scif3_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3336 RTS3_N_MARK, CTS3_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3337};
3338static const unsigned int scif3_data_b_pins[] = {
3339 /* RX, TX */
3340 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3341};
3342static const unsigned int scif3_data_b_mux[] = {
3343 RX3_B_MARK, TX3_B_MARK,
3344};
3345/* - SCIF4 ------------------------------------------------------------------ */
3346static const unsigned int scif4_data_a_pins[] = {
3347 /* RX, TX */
3348 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3349};
3350static const unsigned int scif4_data_a_mux[] = {
3351 RX4_A_MARK, TX4_A_MARK,
3352};
3353static const unsigned int scif4_clk_a_pins[] = {
3354 /* SCK */
3355 RCAR_GP_PIN(2, 10),
3356};
3357static const unsigned int scif4_clk_a_mux[] = {
3358 SCK4_A_MARK,
3359};
3360static const unsigned int scif4_ctrl_a_pins[] = {
3361 /* RTS, CTS */
3362 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3363};
3364static const unsigned int scif4_ctrl_a_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3365 RTS4_N_A_MARK, CTS4_N_A_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3366};
3367static const unsigned int scif4_data_b_pins[] = {
3368 /* RX, TX */
3369 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3370};
3371static const unsigned int scif4_data_b_mux[] = {
3372 RX4_B_MARK, TX4_B_MARK,
3373};
3374static const unsigned int scif4_clk_b_pins[] = {
3375 /* SCK */
3376 RCAR_GP_PIN(1, 5),
3377};
3378static const unsigned int scif4_clk_b_mux[] = {
3379 SCK4_B_MARK,
3380};
3381static const unsigned int scif4_ctrl_b_pins[] = {
3382 /* RTS, CTS */
3383 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3384};
3385static const unsigned int scif4_ctrl_b_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3386 RTS4_N_B_MARK, CTS4_N_B_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3387};
3388static const unsigned int scif4_data_c_pins[] = {
3389 /* RX, TX */
3390 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3391};
3392static const unsigned int scif4_data_c_mux[] = {
3393 RX4_C_MARK, TX4_C_MARK,
3394};
3395static const unsigned int scif4_clk_c_pins[] = {
3396 /* SCK */
3397 RCAR_GP_PIN(0, 8),
3398};
3399static const unsigned int scif4_clk_c_mux[] = {
3400 SCK4_C_MARK,
3401};
3402static const unsigned int scif4_ctrl_c_pins[] = {
3403 /* RTS, CTS */
3404 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3405};
3406static const unsigned int scif4_ctrl_c_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3407 RTS4_N_C_MARK, CTS4_N_C_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3408};
3409/* - SCIF5 ------------------------------------------------------------------ */
3410static const unsigned int scif5_data_a_pins[] = {
3411 /* RX, TX */
3412 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3413};
3414static const unsigned int scif5_data_a_mux[] = {
3415 RX5_A_MARK, TX5_A_MARK,
3416};
3417static const unsigned int scif5_clk_a_pins[] = {
3418 /* SCK */
3419 RCAR_GP_PIN(6, 21),
3420};
3421static const unsigned int scif5_clk_a_mux[] = {
3422 SCK5_A_MARK,
3423};
3424
3425static const unsigned int scif5_data_b_pins[] = {
3426 /* RX, TX */
3427 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3428};
3429static const unsigned int scif5_data_b_mux[] = {
3430 RX5_B_MARK, TX5_B_MARK,
3431};
3432static const unsigned int scif5_clk_b_pins[] = {
3433 /* SCK */
3434 RCAR_GP_PIN(5, 0),
3435};
3436static const unsigned int scif5_clk_b_mux[] = {
3437 SCK5_B_MARK,
3438};
3439
3440/* - SCIF Clock ------------------------------------------------------------- */
3441static const unsigned int scif_clk_a_pins[] = {
3442 /* SCIF_CLK */
3443 RCAR_GP_PIN(6, 23),
3444};
3445static const unsigned int scif_clk_a_mux[] = {
3446 SCIF_CLK_A_MARK,
3447};
3448static const unsigned int scif_clk_b_pins[] = {
3449 /* SCIF_CLK */
3450 RCAR_GP_PIN(5, 9),
3451};
3452static const unsigned int scif_clk_b_mux[] = {
3453 SCIF_CLK_B_MARK,
3454};
3455
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]3456/* - SDHI0 ------------------------------------------------------------------ */
3457static const unsigned int sdhi0_data1_pins[] = {
3458 /* D0 */
3459 RCAR_GP_PIN(3, 2),
3460};
3461static const unsigned int sdhi0_data1_mux[] = {
3462 SD0_DAT0_MARK,
3463};
3464static const unsigned int sdhi0_data4_pins[] = {
3465 /* D[0:3] */
3466 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3467 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3468};
3469static const unsigned int sdhi0_data4_mux[] = {
3470 SD0_DAT0_MARK, SD0_DAT1_MARK,
3471 SD0_DAT2_MARK, SD0_DAT3_MARK,
3472};
3473static const unsigned int sdhi0_ctrl_pins[] = {
3474 /* CLK, CMD */
3475 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3476};
3477static const unsigned int sdhi0_ctrl_mux[] = {
3478 SD0_CLK_MARK, SD0_CMD_MARK,
3479};
3480static const unsigned int sdhi0_cd_pins[] = {
3481 /* CD */
3482 RCAR_GP_PIN(3, 12),
3483};
3484static const unsigned int sdhi0_cd_mux[] = {
3485 SD0_CD_MARK,
3486};
3487static const unsigned int sdhi0_wp_pins[] = {
3488 /* WP */
3489 RCAR_GP_PIN(3, 13),
3490};
3491static const unsigned int sdhi0_wp_mux[] = {
3492 SD0_WP_MARK,
3493};
3494/* - SDHI1 ------------------------------------------------------------------ */
3495static const unsigned int sdhi1_data1_pins[] = {
3496 /* D0 */
3497 RCAR_GP_PIN(3, 8),
3498};
3499static const unsigned int sdhi1_data1_mux[] = {
3500 SD1_DAT0_MARK,
3501};
3502static const unsigned int sdhi1_data4_pins[] = {
3503 /* D[0:3] */
3504 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3505 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3506};
3507static const unsigned int sdhi1_data4_mux[] = {
3508 SD1_DAT0_MARK, SD1_DAT1_MARK,
3509 SD1_DAT2_MARK, SD1_DAT3_MARK,
3510};
3511static const unsigned int sdhi1_ctrl_pins[] = {
3512 /* CLK, CMD */
3513 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3514};
3515static const unsigned int sdhi1_ctrl_mux[] = {
3516 SD1_CLK_MARK, SD1_CMD_MARK,
3517};
3518static const unsigned int sdhi1_cd_pins[] = {
3519 /* CD */
3520 RCAR_GP_PIN(3, 14),
3521};
3522static const unsigned int sdhi1_cd_mux[] = {
3523 SD1_CD_MARK,
3524};
3525static const unsigned int sdhi1_wp_pins[] = {
3526 /* WP */
3527 RCAR_GP_PIN(3, 15),
3528};
3529static const unsigned int sdhi1_wp_mux[] = {
3530 SD1_WP_MARK,
3531};
3532/* - SDHI2 ------------------------------------------------------------------ */
3533static const unsigned int sdhi2_data1_pins[] = {
3534 /* D0 */
3535 RCAR_GP_PIN(4, 2),
3536};
3537static const unsigned int sdhi2_data1_mux[] = {
3538 SD2_DAT0_MARK,
3539};
3540static const unsigned int sdhi2_data4_pins[] = {
3541 /* D[0:3] */
3542 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3543 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3544};
3545static const unsigned int sdhi2_data4_mux[] = {
3546 SD2_DAT0_MARK, SD2_DAT1_MARK,
3547 SD2_DAT2_MARK, SD2_DAT3_MARK,
3548};
3549static const unsigned int sdhi2_data8_pins[] = {
3550 /* D[0:7] */
3551 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3552 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3553 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3554 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3555};
3556static const unsigned int sdhi2_data8_mux[] = {
3557 SD2_DAT0_MARK, SD2_DAT1_MARK,
3558 SD2_DAT2_MARK, SD2_DAT3_MARK,
3559 SD2_DAT4_MARK, SD2_DAT5_MARK,
3560 SD2_DAT6_MARK, SD2_DAT7_MARK,
3561};
3562static const unsigned int sdhi2_ctrl_pins[] = {
3563 /* CLK, CMD */
3564 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3565};
3566static const unsigned int sdhi2_ctrl_mux[] = {
3567 SD2_CLK_MARK, SD2_CMD_MARK,
3568};
3569static const unsigned int sdhi2_cd_a_pins[] = {
3570 /* CD */
3571 RCAR_GP_PIN(4, 13),
3572};
3573static const unsigned int sdhi2_cd_a_mux[] = {
3574 SD2_CD_A_MARK,
3575};
3576static const unsigned int sdhi2_cd_b_pins[] = {
3577 /* CD */
3578 RCAR_GP_PIN(5, 10),
3579};
3580static const unsigned int sdhi2_cd_b_mux[] = {
3581 SD2_CD_B_MARK,
3582};
3583static const unsigned int sdhi2_wp_a_pins[] = {
3584 /* WP */
3585 RCAR_GP_PIN(4, 14),
3586};
3587static const unsigned int sdhi2_wp_a_mux[] = {
3588 SD2_WP_A_MARK,
3589};
3590static const unsigned int sdhi2_wp_b_pins[] = {
3591 /* WP */
3592 RCAR_GP_PIN(5, 11),
3593};
3594static const unsigned int sdhi2_wp_b_mux[] = {
3595 SD2_WP_B_MARK,
3596};
3597static const unsigned int sdhi2_ds_pins[] = {
3598 /* DS */
3599 RCAR_GP_PIN(4, 6),
3600};
3601static const unsigned int sdhi2_ds_mux[] = {
3602 SD2_DS_MARK,
3603};
3604/* - SDHI3 ------------------------------------------------------------------ */
3605static const unsigned int sdhi3_data1_pins[] = {
3606 /* D0 */
3607 RCAR_GP_PIN(4, 9),
3608};
3609static const unsigned int sdhi3_data1_mux[] = {
3610 SD3_DAT0_MARK,
3611};
3612static const unsigned int sdhi3_data4_pins[] = {
3613 /* D[0:3] */
3614 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3615 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3616};
3617static const unsigned int sdhi3_data4_mux[] = {
3618 SD3_DAT0_MARK, SD3_DAT1_MARK,
3619 SD3_DAT2_MARK, SD3_DAT3_MARK,
3620};
3621static const unsigned int sdhi3_data8_pins[] = {
3622 /* D[0:7] */
3623 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3624 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3625 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3626 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3627};
3628static const unsigned int sdhi3_data8_mux[] = {
3629 SD3_DAT0_MARK, SD3_DAT1_MARK,
3630 SD3_DAT2_MARK, SD3_DAT3_MARK,
3631 SD3_DAT4_MARK, SD3_DAT5_MARK,
3632 SD3_DAT6_MARK, SD3_DAT7_MARK,
3633};
3634static const unsigned int sdhi3_ctrl_pins[] = {
3635 /* CLK, CMD */
3636 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3637};
3638static const unsigned int sdhi3_ctrl_mux[] = {
3639 SD3_CLK_MARK, SD3_CMD_MARK,
3640};
3641static const unsigned int sdhi3_cd_pins[] = {
3642 /* CD */
3643 RCAR_GP_PIN(4, 15),
3644};
3645static const unsigned int sdhi3_cd_mux[] = {
3646 SD3_CD_MARK,
3647};
3648static const unsigned int sdhi3_wp_pins[] = {
3649 /* WP */
3650 RCAR_GP_PIN(4, 16),
3651};
3652static const unsigned int sdhi3_wp_mux[] = {
3653 SD3_WP_MARK,
3654};
3655static const unsigned int sdhi3_ds_pins[] = {
3656 /* DS */
3657 RCAR_GP_PIN(4, 17),
3658};
3659static const unsigned int sdhi3_ds_mux[] = {
3660 SD3_DS_MARK,
3661};
3662
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]3663/* - SSI -------------------------------------------------------------------- */
3664static const unsigned int ssi0_data_pins[] = {
3665 /* SDATA */
3666 RCAR_GP_PIN(6, 2),
3667};
3668static const unsigned int ssi0_data_mux[] = {
3669 SSI_SDATA0_MARK,
3670};
3671static const unsigned int ssi01239_ctrl_pins[] = {
3672 /* SCK, WS */
3673 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3674};
3675static const unsigned int ssi01239_ctrl_mux[] = {
3676 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3677};
3678static const unsigned int ssi1_data_a_pins[] = {
3679 /* SDATA */
3680 RCAR_GP_PIN(6, 3),
3681};
3682static const unsigned int ssi1_data_a_mux[] = {
3683 SSI_SDATA1_A_MARK,
3684};
3685static const unsigned int ssi1_data_b_pins[] = {
3686 /* SDATA */
3687 RCAR_GP_PIN(5, 12),
3688};
3689static const unsigned int ssi1_data_b_mux[] = {
3690 SSI_SDATA1_B_MARK,
3691};
3692static const unsigned int ssi1_ctrl_a_pins[] = {
3693 /* SCK, WS */
3694 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3695};
3696static const unsigned int ssi1_ctrl_a_mux[] = {
3697 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3698};
3699static const unsigned int ssi1_ctrl_b_pins[] = {
3700 /* SCK, WS */
3701 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3702};
3703static const unsigned int ssi1_ctrl_b_mux[] = {
3704 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3705};
3706static const unsigned int ssi2_data_a_pins[] = {
3707 /* SDATA */
3708 RCAR_GP_PIN(6, 4),
3709};
3710static const unsigned int ssi2_data_a_mux[] = {
3711 SSI_SDATA2_A_MARK,
3712};
3713static const unsigned int ssi2_data_b_pins[] = {
3714 /* SDATA */
3715 RCAR_GP_PIN(5, 13),
3716};
3717static const unsigned int ssi2_data_b_mux[] = {
3718 SSI_SDATA2_B_MARK,
3719};
3720static const unsigned int ssi2_ctrl_a_pins[] = {
3721 /* SCK, WS */
3722 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3723};
3724static const unsigned int ssi2_ctrl_a_mux[] = {
3725 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3726};
3727static const unsigned int ssi2_ctrl_b_pins[] = {
3728 /* SCK, WS */
3729 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3730};
3731static const unsigned int ssi2_ctrl_b_mux[] = {
3732 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3733};
3734static const unsigned int ssi3_data_pins[] = {
3735 /* SDATA */
3736 RCAR_GP_PIN(6, 7),
3737};
3738static const unsigned int ssi3_data_mux[] = {
3739 SSI_SDATA3_MARK,
3740};
3741static const unsigned int ssi349_ctrl_pins[] = {
3742 /* SCK, WS */
3743 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3744};
3745static const unsigned int ssi349_ctrl_mux[] = {
3746 SSI_SCK349_MARK, SSI_WS349_MARK,
3747};
3748static const unsigned int ssi4_data_pins[] = {
3749 /* SDATA */
3750 RCAR_GP_PIN(6, 10),
3751};
3752static const unsigned int ssi4_data_mux[] = {
3753 SSI_SDATA4_MARK,
3754};
3755static const unsigned int ssi4_ctrl_pins[] = {
3756 /* SCK, WS */
3757 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3758};
3759static const unsigned int ssi4_ctrl_mux[] = {
3760 SSI_SCK4_MARK, SSI_WS4_MARK,
3761};
3762static const unsigned int ssi5_data_pins[] = {
3763 /* SDATA */
3764 RCAR_GP_PIN(6, 13),
3765};
3766static const unsigned int ssi5_data_mux[] = {
3767 SSI_SDATA5_MARK,
3768};
3769static const unsigned int ssi5_ctrl_pins[] = {
3770 /* SCK, WS */
3771 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3772};
3773static const unsigned int ssi5_ctrl_mux[] = {
3774 SSI_SCK5_MARK, SSI_WS5_MARK,
3775};
3776static const unsigned int ssi6_data_pins[] = {
3777 /* SDATA */
3778 RCAR_GP_PIN(6, 16),
3779};
3780static const unsigned int ssi6_data_mux[] = {
3781 SSI_SDATA6_MARK,
3782};
3783static const unsigned int ssi6_ctrl_pins[] = {
3784 /* SCK, WS */
3785 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3786};
3787static const unsigned int ssi6_ctrl_mux[] = {
3788 SSI_SCK6_MARK, SSI_WS6_MARK,
3789};
3790static const unsigned int ssi7_data_pins[] = {
3791 /* SDATA */
3792 RCAR_GP_PIN(6, 19),
3793};
3794static const unsigned int ssi7_data_mux[] = {
3795 SSI_SDATA7_MARK,
3796};
3797static const unsigned int ssi78_ctrl_pins[] = {
3798 /* SCK, WS */
3799 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3800};
3801static const unsigned int ssi78_ctrl_mux[] = {
3802 SSI_SCK78_MARK, SSI_WS78_MARK,
3803};
3804static const unsigned int ssi8_data_pins[] = {
3805 /* SDATA */
3806 RCAR_GP_PIN(6, 20),
3807};
3808static const unsigned int ssi8_data_mux[] = {
3809 SSI_SDATA8_MARK,
3810};
3811static const unsigned int ssi9_data_a_pins[] = {
3812 /* SDATA */
3813 RCAR_GP_PIN(6, 21),
3814};
3815static const unsigned int ssi9_data_a_mux[] = {
3816 SSI_SDATA9_A_MARK,
3817};
3818static const unsigned int ssi9_data_b_pins[] = {
3819 /* SDATA */
3820 RCAR_GP_PIN(5, 14),
3821};
3822static const unsigned int ssi9_data_b_mux[] = {
3823 SSI_SDATA9_B_MARK,
3824};
3825static const unsigned int ssi9_ctrl_a_pins[] = {
3826 /* SCK, WS */
3827 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3828};
3829static const unsigned int ssi9_ctrl_a_mux[] = {
3830 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3831};
3832static const unsigned int ssi9_ctrl_b_pins[] = {
3833 /* SCK, WS */
3834 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3835};
3836static const unsigned int ssi9_ctrl_b_mux[] = {
3837 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3838};
3839
Takeshi Kihara74965de2018-02-16 15:26:11 +0100[diff] [blame]3840/* - TMU -------------------------------------------------------------------- */
3841static const unsigned int tmu_tclk1_a_pins[] = {
3842 /* TCLK */
3843 RCAR_GP_PIN(6, 23),
3844};
3845static const unsigned int tmu_tclk1_a_mux[] = {
3846 TCLK1_A_MARK,
3847};
3848static const unsigned int tmu_tclk1_b_pins[] = {
3849 /* TCLK */
3850 RCAR_GP_PIN(5, 19),
3851};
3852static const unsigned int tmu_tclk1_b_mux[] = {
3853 TCLK1_B_MARK,
3854};
3855static const unsigned int tmu_tclk2_a_pins[] = {
3856 /* TCLK */
3857 RCAR_GP_PIN(6, 19),
3858};
3859static const unsigned int tmu_tclk2_a_mux[] = {
3860 TCLK2_A_MARK,
3861};
3862static const unsigned int tmu_tclk2_b_pins[] = {
3863 /* TCLK */
3864 RCAR_GP_PIN(6, 28),
3865};
3866static const unsigned int tmu_tclk2_b_mux[] = {
3867 TCLK2_B_MARK,
3868};
3869
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]3870/* - USB0 ------------------------------------------------------------------- */
3871static const unsigned int usb0_pins[] = {
3872 /* PWEN, OVC */
3873 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3874};
3875static const unsigned int usb0_mux[] = {
3876 USB0_PWEN_MARK, USB0_OVC_MARK,
3877};
3878/* - USB1 ------------------------------------------------------------------- */
3879static const unsigned int usb1_pins[] = {
3880 /* PWEN, OVC */
3881 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3882};
3883static const unsigned int usb1_mux[] = {
3884 USB1_PWEN_MARK, USB1_OVC_MARK,
3885};
3886
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]3887/* - USB30 ------------------------------------------------------------------ */
3888static const unsigned int usb30_pins[] = {
3889 /* PWEN, OVC */
3890 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3891};
3892static const unsigned int usb30_mux[] = {
3893 USB30_PWEN_MARK, USB30_OVC_MARK,
3894};
3895
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3896/* - VIN4 ------------------------------------------------------------------- */
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3897static const unsigned int vin4_data18_a_pins[] = {
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3898 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3899 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3900 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3901 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3902 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3903 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Ulrich Hechta66b68b2018-03-19 17:37:19 +0100[diff] [blame]3904 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3905 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3906 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3907};
3908static const unsigned int vin4_data18_a_mux[] = {
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3909 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3910 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3911 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3912 VI4_DATA10_MARK, VI4_DATA11_MARK,
3913 VI4_DATA12_MARK, VI4_DATA13_MARK,
3914 VI4_DATA14_MARK, VI4_DATA15_MARK,
Ulrich Hechta66b68b2018-03-19 17:37:19 +0100[diff] [blame]3915 VI4_DATA18_MARK, VI4_DATA19_MARK,
3916 VI4_DATA20_MARK, VI4_DATA21_MARK,
3917 VI4_DATA22_MARK, VI4_DATA23_MARK,
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3918};
3919static const unsigned int vin4_data18_b_pins[] = {
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3920 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3921 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3922 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3923 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3924 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3925 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Ulrich Hechta66b68b2018-03-19 17:37:19 +0100[diff] [blame]3926 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3927 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3928 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3929};
3930static const unsigned int vin4_data18_b_mux[] = {
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3931 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3932 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3933 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3934 VI4_DATA10_MARK, VI4_DATA11_MARK,
3935 VI4_DATA12_MARK, VI4_DATA13_MARK,
3936 VI4_DATA14_MARK, VI4_DATA15_MARK,
Ulrich Hechta66b68b2018-03-19 17:37:19 +0100[diff] [blame]3937 VI4_DATA18_MARK, VI4_DATA19_MARK,
3938 VI4_DATA20_MARK, VI4_DATA21_MARK,
3939 VI4_DATA22_MARK, VI4_DATA23_MARK,
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3940};
Ulrich Hechta5c29492018-03-19 17:37:44 +0100[diff] [blame]3941static const union vin_data vin4_data_a_pins = {
3942 .data24 = {
3943 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3944 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3945 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3946 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3947 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3948 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3949 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3950 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3951 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3952 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3953 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3954 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3955 },
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3956};
Ulrich Hechta5c29492018-03-19 17:37:44 +0100[diff] [blame]3957static const union vin_data vin4_data_a_mux = {
3958 .data24 = {
3959 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3960 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3961 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3962 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3963 VI4_DATA8_MARK, VI4_DATA9_MARK,
3964 VI4_DATA10_MARK, VI4_DATA11_MARK,
3965 VI4_DATA12_MARK, VI4_DATA13_MARK,
3966 VI4_DATA14_MARK, VI4_DATA15_MARK,
3967 VI4_DATA16_MARK, VI4_DATA17_MARK,
3968 VI4_DATA18_MARK, VI4_DATA19_MARK,
3969 VI4_DATA20_MARK, VI4_DATA21_MARK,
3970 VI4_DATA22_MARK, VI4_DATA23_MARK,
3971 },
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3972};
Ulrich Hechta5c29492018-03-19 17:37:44 +0100[diff] [blame]3973static const union vin_data vin4_data_b_pins = {
3974 .data24 = {
3975 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3976 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3977 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3978 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3979 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3980 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3981 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3982 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3983 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3984 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3985 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3986 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3987 },
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]3988};
Ulrich Hechta5c29492018-03-19 17:37:44 +0100[diff] [blame]3989static const union vin_data vin4_data_b_mux = {
3990 .data24 = {
3991 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3992 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3993 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3994 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3995 VI4_DATA8_MARK, VI4_DATA9_MARK,
3996 VI4_DATA10_MARK, VI4_DATA11_MARK,
3997 VI4_DATA12_MARK, VI4_DATA13_MARK,
3998 VI4_DATA14_MARK, VI4_DATA15_MARK,
3999 VI4_DATA16_MARK, VI4_DATA17_MARK,
4000 VI4_DATA18_MARK, VI4_DATA19_MARK,
4001 VI4_DATA20_MARK, VI4_DATA21_MARK,
4002 VI4_DATA22_MARK, VI4_DATA23_MARK,
4003 },
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]4004};
4005static const unsigned int vin4_sync_pins[] = {
4006 /* HSYNC#, VSYNC# */
4007 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4008};
4009static const unsigned int vin4_sync_mux[] = {
4010 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4011};
4012static const unsigned int vin4_field_pins[] = {
4013 /* FIELD */
4014 RCAR_GP_PIN(1, 16),
4015};
4016static const unsigned int vin4_field_mux[] = {
4017 VI4_FIELD_MARK,
4018};
4019static const unsigned int vin4_clkenb_pins[] = {
4020 /* CLKENB */
4021 RCAR_GP_PIN(1, 19),
4022};
4023static const unsigned int vin4_clkenb_mux[] = {
4024 VI4_CLKENB_MARK,
4025};
4026static const unsigned int vin4_clk_pins[] = {
4027 /* CLK */
4028 RCAR_GP_PIN(1, 27),
4029};
4030static const unsigned int vin4_clk_mux[] = {
4031 VI4_CLK_MARK,
4032};
4033
4034/* - VIN5 ------------------------------------------------------------------- */
4035static const unsigned int vin5_data8_pins[] = {
4036 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4037 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4038 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4039 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4040};
4041static const unsigned int vin5_data8_mux[] = {
4042 VI5_DATA0_MARK, VI5_DATA1_MARK,
4043 VI5_DATA2_MARK, VI5_DATA3_MARK,
4044 VI5_DATA4_MARK, VI5_DATA5_MARK,
4045 VI5_DATA6_MARK, VI5_DATA7_MARK,
4046};
4047static const unsigned int vin5_data10_pins[] = {
4048 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4049 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4050 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4051 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4052 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4053};
4054static const unsigned int vin5_data10_mux[] = {
4055 VI5_DATA0_MARK, VI5_DATA1_MARK,
4056 VI5_DATA2_MARK, VI5_DATA3_MARK,
4057 VI5_DATA4_MARK, VI5_DATA5_MARK,
4058 VI5_DATA6_MARK, VI5_DATA7_MARK,
4059 VI5_DATA8_MARK, VI5_DATA9_MARK,
4060};
4061static const unsigned int vin5_data12_pins[] = {
4062 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4063 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4064 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4065 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4066 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4067 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4068};
4069static const unsigned int vin5_data12_mux[] = {
4070 VI5_DATA0_MARK, VI5_DATA1_MARK,
4071 VI5_DATA2_MARK, VI5_DATA3_MARK,
4072 VI5_DATA4_MARK, VI5_DATA5_MARK,
4073 VI5_DATA6_MARK, VI5_DATA7_MARK,
4074 VI5_DATA8_MARK, VI5_DATA9_MARK,
4075 VI5_DATA10_MARK, VI5_DATA11_MARK,
4076};
4077static const unsigned int vin5_data16_pins[] = {
4078 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4079 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4080 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4081 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4082 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4083 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4084 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4085 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4086};
4087static const unsigned int vin5_data16_mux[] = {
4088 VI5_DATA0_MARK, VI5_DATA1_MARK,
4089 VI5_DATA2_MARK, VI5_DATA3_MARK,
4090 VI5_DATA4_MARK, VI5_DATA5_MARK,
4091 VI5_DATA6_MARK, VI5_DATA7_MARK,
4092 VI5_DATA8_MARK, VI5_DATA9_MARK,
4093 VI5_DATA10_MARK, VI5_DATA11_MARK,
4094 VI5_DATA12_MARK, VI5_DATA13_MARK,
4095 VI5_DATA14_MARK, VI5_DATA15_MARK,
4096};
4097static const unsigned int vin5_sync_pins[] = {
4098 /* HSYNC#, VSYNC# */
4099 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4100};
4101static const unsigned int vin5_sync_mux[] = {
4102 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4103};
4104static const unsigned int vin5_field_pins[] = {
4105 RCAR_GP_PIN(1, 11),
4106};
4107static const unsigned int vin5_field_mux[] = {
4108 /* FIELD */
4109 VI5_FIELD_MARK,
4110};
4111static const unsigned int vin5_clkenb_pins[] = {
4112 RCAR_GP_PIN(1, 20),
4113};
4114static const unsigned int vin5_clkenb_mux[] = {
4115 /* CLKENB */
4116 VI5_CLKENB_MARK,
4117};
4118static const unsigned int vin5_clk_pins[] = {
4119 RCAR_GP_PIN(1, 21),
4120};
4121static const unsigned int vin5_clk_mux[] = {
4122 /* CLK */
4123 VI5_CLK_MARK,
4124};
4125
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]4126static const struct {
4127 struct sh_pfc_pin_group common[307];
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]4128 struct sh_pfc_pin_group automotive[33];
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]4129} pinmux_groups = {
4130 .common = {
4131 SH_PFC_PIN_GROUP(audio_clk_a_a),
4132 SH_PFC_PIN_GROUP(audio_clk_a_b),
4133 SH_PFC_PIN_GROUP(audio_clk_a_c),
4134 SH_PFC_PIN_GROUP(audio_clk_b_a),
4135 SH_PFC_PIN_GROUP(audio_clk_b_b),
4136 SH_PFC_PIN_GROUP(audio_clk_c_a),
4137 SH_PFC_PIN_GROUP(audio_clk_c_b),
4138 SH_PFC_PIN_GROUP(audio_clkout_a),
4139 SH_PFC_PIN_GROUP(audio_clkout_b),
4140 SH_PFC_PIN_GROUP(audio_clkout_c),
4141 SH_PFC_PIN_GROUP(audio_clkout_d),
4142 SH_PFC_PIN_GROUP(audio_clkout1_a),
4143 SH_PFC_PIN_GROUP(audio_clkout1_b),
4144 SH_PFC_PIN_GROUP(audio_clkout2_a),
4145 SH_PFC_PIN_GROUP(audio_clkout2_b),
4146 SH_PFC_PIN_GROUP(audio_clkout3_a),
4147 SH_PFC_PIN_GROUP(audio_clkout3_b),
4148 SH_PFC_PIN_GROUP(avb_link),
4149 SH_PFC_PIN_GROUP(avb_magic),
4150 SH_PFC_PIN_GROUP(avb_phy_int),
4151 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4152 SH_PFC_PIN_GROUP(avb_mdio),
4153 SH_PFC_PIN_GROUP(avb_mii),
4154 SH_PFC_PIN_GROUP(avb_avtp_pps),
4155 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4156 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4157 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4158 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4159 SH_PFC_PIN_GROUP(can0_data_a),
4160 SH_PFC_PIN_GROUP(can0_data_b),
4161 SH_PFC_PIN_GROUP(can1_data),
4162 SH_PFC_PIN_GROUP(can_clk),
4163 SH_PFC_PIN_GROUP(du_rgb666),
4164 SH_PFC_PIN_GROUP(du_rgb888),
4165 SH_PFC_PIN_GROUP(du_clk_out_0),
4166 SH_PFC_PIN_GROUP(du_clk_out_1),
4167 SH_PFC_PIN_GROUP(du_sync),
4168 SH_PFC_PIN_GROUP(du_oddf),
4169 SH_PFC_PIN_GROUP(du_cde),
4170 SH_PFC_PIN_GROUP(du_disp),
4171 SH_PFC_PIN_GROUP(hdmi0_cec),
4172 SH_PFC_PIN_GROUP(hscif0_data),
4173 SH_PFC_PIN_GROUP(hscif0_clk),
4174 SH_PFC_PIN_GROUP(hscif0_ctrl),
4175 SH_PFC_PIN_GROUP(hscif1_data_a),
4176 SH_PFC_PIN_GROUP(hscif1_clk_a),
4177 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4178 SH_PFC_PIN_GROUP(hscif1_data_b),
4179 SH_PFC_PIN_GROUP(hscif1_clk_b),
4180 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4181 SH_PFC_PIN_GROUP(hscif2_data_a),
4182 SH_PFC_PIN_GROUP(hscif2_clk_a),
4183 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4184 SH_PFC_PIN_GROUP(hscif2_data_b),
4185 SH_PFC_PIN_GROUP(hscif2_clk_b),
4186 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4187 SH_PFC_PIN_GROUP(hscif2_data_c),
4188 SH_PFC_PIN_GROUP(hscif2_clk_c),
4189 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4190 SH_PFC_PIN_GROUP(hscif3_data_a),
4191 SH_PFC_PIN_GROUP(hscif3_clk),
4192 SH_PFC_PIN_GROUP(hscif3_ctrl),
4193 SH_PFC_PIN_GROUP(hscif3_data_b),
4194 SH_PFC_PIN_GROUP(hscif3_data_c),
4195 SH_PFC_PIN_GROUP(hscif3_data_d),
4196 SH_PFC_PIN_GROUP(hscif4_data_a),
4197 SH_PFC_PIN_GROUP(hscif4_clk),
4198 SH_PFC_PIN_GROUP(hscif4_ctrl),
4199 SH_PFC_PIN_GROUP(hscif4_data_b),
4200 SH_PFC_PIN_GROUP(i2c1_a),
4201 SH_PFC_PIN_GROUP(i2c1_b),
4202 SH_PFC_PIN_GROUP(i2c2_a),
4203 SH_PFC_PIN_GROUP(i2c2_b),
4204 SH_PFC_PIN_GROUP(i2c6_a),
4205 SH_PFC_PIN_GROUP(i2c6_b),
4206 SH_PFC_PIN_GROUP(i2c6_c),
4207 SH_PFC_PIN_GROUP(intc_ex_irq0),
4208 SH_PFC_PIN_GROUP(intc_ex_irq1),
4209 SH_PFC_PIN_GROUP(intc_ex_irq2),
4210 SH_PFC_PIN_GROUP(intc_ex_irq3),
4211 SH_PFC_PIN_GROUP(intc_ex_irq4),
4212 SH_PFC_PIN_GROUP(intc_ex_irq5),
4213 SH_PFC_PIN_GROUP(msiof0_clk),
4214 SH_PFC_PIN_GROUP(msiof0_sync),
4215 SH_PFC_PIN_GROUP(msiof0_ss1),
4216 SH_PFC_PIN_GROUP(msiof0_ss2),
4217 SH_PFC_PIN_GROUP(msiof0_txd),
4218 SH_PFC_PIN_GROUP(msiof0_rxd),
4219 SH_PFC_PIN_GROUP(msiof1_clk_a),
4220 SH_PFC_PIN_GROUP(msiof1_sync_a),
4221 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4222 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4223 SH_PFC_PIN_GROUP(msiof1_txd_a),
4224 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4225 SH_PFC_PIN_GROUP(msiof1_clk_b),
4226 SH_PFC_PIN_GROUP(msiof1_sync_b),
4227 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4228 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4229 SH_PFC_PIN_GROUP(msiof1_txd_b),
4230 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4231 SH_PFC_PIN_GROUP(msiof1_clk_c),
4232 SH_PFC_PIN_GROUP(msiof1_sync_c),
4233 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4234 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4235 SH_PFC_PIN_GROUP(msiof1_txd_c),
4236 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4237 SH_PFC_PIN_GROUP(msiof1_clk_d),
4238 SH_PFC_PIN_GROUP(msiof1_sync_d),
4239 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4240 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4241 SH_PFC_PIN_GROUP(msiof1_txd_d),
4242 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4243 SH_PFC_PIN_GROUP(msiof1_clk_e),
4244 SH_PFC_PIN_GROUP(msiof1_sync_e),
4245 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4246 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4247 SH_PFC_PIN_GROUP(msiof1_txd_e),
4248 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4249 SH_PFC_PIN_GROUP(msiof1_clk_f),
4250 SH_PFC_PIN_GROUP(msiof1_sync_f),
4251 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4252 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4253 SH_PFC_PIN_GROUP(msiof1_txd_f),
4254 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4255 SH_PFC_PIN_GROUP(msiof1_clk_g),
4256 SH_PFC_PIN_GROUP(msiof1_sync_g),
4257 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4258 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4259 SH_PFC_PIN_GROUP(msiof1_txd_g),
4260 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4261 SH_PFC_PIN_GROUP(msiof2_clk_a),
4262 SH_PFC_PIN_GROUP(msiof2_sync_a),
4263 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4264 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4265 SH_PFC_PIN_GROUP(msiof2_txd_a),
4266 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4267 SH_PFC_PIN_GROUP(msiof2_clk_b),
4268 SH_PFC_PIN_GROUP(msiof2_sync_b),
4269 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4270 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4271 SH_PFC_PIN_GROUP(msiof2_txd_b),
4272 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4273 SH_PFC_PIN_GROUP(msiof2_clk_c),
4274 SH_PFC_PIN_GROUP(msiof2_sync_c),
4275 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4276 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4277 SH_PFC_PIN_GROUP(msiof2_txd_c),
4278 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4279 SH_PFC_PIN_GROUP(msiof2_clk_d),
4280 SH_PFC_PIN_GROUP(msiof2_sync_d),
4281 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4282 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4283 SH_PFC_PIN_GROUP(msiof2_txd_d),
4284 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4285 SH_PFC_PIN_GROUP(msiof3_clk_a),
4286 SH_PFC_PIN_GROUP(msiof3_sync_a),
4287 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4288 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4289 SH_PFC_PIN_GROUP(msiof3_txd_a),
4290 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4291 SH_PFC_PIN_GROUP(msiof3_clk_b),
4292 SH_PFC_PIN_GROUP(msiof3_sync_b),
4293 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4294 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4295 SH_PFC_PIN_GROUP(msiof3_txd_b),
4296 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4297 SH_PFC_PIN_GROUP(msiof3_clk_c),
4298 SH_PFC_PIN_GROUP(msiof3_sync_c),
4299 SH_PFC_PIN_GROUP(msiof3_txd_c),
4300 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4301 SH_PFC_PIN_GROUP(msiof3_clk_d),
4302 SH_PFC_PIN_GROUP(msiof3_sync_d),
4303 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4304 SH_PFC_PIN_GROUP(msiof3_txd_d),
4305 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4306 SH_PFC_PIN_GROUP(msiof3_clk_e),
4307 SH_PFC_PIN_GROUP(msiof3_sync_e),
4308 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4309 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4310 SH_PFC_PIN_GROUP(msiof3_txd_e),
4311 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4312 SH_PFC_PIN_GROUP(pwm0),
4313 SH_PFC_PIN_GROUP(pwm1_a),
4314 SH_PFC_PIN_GROUP(pwm1_b),
4315 SH_PFC_PIN_GROUP(pwm2_a),
4316 SH_PFC_PIN_GROUP(pwm2_b),
4317 SH_PFC_PIN_GROUP(pwm3_a),
4318 SH_PFC_PIN_GROUP(pwm3_b),
4319 SH_PFC_PIN_GROUP(pwm4_a),
4320 SH_PFC_PIN_GROUP(pwm4_b),
4321 SH_PFC_PIN_GROUP(pwm5_a),
4322 SH_PFC_PIN_GROUP(pwm5_b),
4323 SH_PFC_PIN_GROUP(pwm6_a),
4324 SH_PFC_PIN_GROUP(pwm6_b),
4325 SH_PFC_PIN_GROUP(scif0_data),
4326 SH_PFC_PIN_GROUP(scif0_clk),
4327 SH_PFC_PIN_GROUP(scif0_ctrl),
4328 SH_PFC_PIN_GROUP(scif1_data_a),
4329 SH_PFC_PIN_GROUP(scif1_clk),
4330 SH_PFC_PIN_GROUP(scif1_ctrl),
4331 SH_PFC_PIN_GROUP(scif1_data_b),
4332 SH_PFC_PIN_GROUP(scif2_data_a),
4333 SH_PFC_PIN_GROUP(scif2_clk),
4334 SH_PFC_PIN_GROUP(scif2_data_b),
4335 SH_PFC_PIN_GROUP(scif3_data_a),
4336 SH_PFC_PIN_GROUP(scif3_clk),
4337 SH_PFC_PIN_GROUP(scif3_ctrl),
4338 SH_PFC_PIN_GROUP(scif3_data_b),
4339 SH_PFC_PIN_GROUP(scif4_data_a),
4340 SH_PFC_PIN_GROUP(scif4_clk_a),
4341 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4342 SH_PFC_PIN_GROUP(scif4_data_b),
4343 SH_PFC_PIN_GROUP(scif4_clk_b),
4344 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4345 SH_PFC_PIN_GROUP(scif4_data_c),
4346 SH_PFC_PIN_GROUP(scif4_clk_c),
4347 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4348 SH_PFC_PIN_GROUP(scif5_data_a),
4349 SH_PFC_PIN_GROUP(scif5_clk_a),
4350 SH_PFC_PIN_GROUP(scif5_data_b),
4351 SH_PFC_PIN_GROUP(scif5_clk_b),
4352 SH_PFC_PIN_GROUP(scif_clk_a),
4353 SH_PFC_PIN_GROUP(scif_clk_b),
4354 SH_PFC_PIN_GROUP(sdhi0_data1),
4355 SH_PFC_PIN_GROUP(sdhi0_data4),
4356 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4357 SH_PFC_PIN_GROUP(sdhi0_cd),
4358 SH_PFC_PIN_GROUP(sdhi0_wp),
4359 SH_PFC_PIN_GROUP(sdhi1_data1),
4360 SH_PFC_PIN_GROUP(sdhi1_data4),
4361 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4362 SH_PFC_PIN_GROUP(sdhi1_cd),
4363 SH_PFC_PIN_GROUP(sdhi1_wp),
4364 SH_PFC_PIN_GROUP(sdhi2_data1),
4365 SH_PFC_PIN_GROUP(sdhi2_data4),
4366 SH_PFC_PIN_GROUP(sdhi2_data8),
4367 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4368 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4369 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4370 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4371 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4372 SH_PFC_PIN_GROUP(sdhi2_ds),
4373 SH_PFC_PIN_GROUP(sdhi3_data1),
4374 SH_PFC_PIN_GROUP(sdhi3_data4),
4375 SH_PFC_PIN_GROUP(sdhi3_data8),
4376 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4377 SH_PFC_PIN_GROUP(sdhi3_cd),
4378 SH_PFC_PIN_GROUP(sdhi3_wp),
4379 SH_PFC_PIN_GROUP(sdhi3_ds),
4380 SH_PFC_PIN_GROUP(ssi0_data),
4381 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4382 SH_PFC_PIN_GROUP(ssi1_data_a),
4383 SH_PFC_PIN_GROUP(ssi1_data_b),
4384 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4385 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4386 SH_PFC_PIN_GROUP(ssi2_data_a),
4387 SH_PFC_PIN_GROUP(ssi2_data_b),
4388 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4389 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4390 SH_PFC_PIN_GROUP(ssi3_data),
4391 SH_PFC_PIN_GROUP(ssi349_ctrl),
4392 SH_PFC_PIN_GROUP(ssi4_data),
4393 SH_PFC_PIN_GROUP(ssi4_ctrl),
4394 SH_PFC_PIN_GROUP(ssi5_data),
4395 SH_PFC_PIN_GROUP(ssi5_ctrl),
4396 SH_PFC_PIN_GROUP(ssi6_data),
4397 SH_PFC_PIN_GROUP(ssi6_ctrl),
4398 SH_PFC_PIN_GROUP(ssi7_data),
4399 SH_PFC_PIN_GROUP(ssi78_ctrl),
4400 SH_PFC_PIN_GROUP(ssi8_data),
4401 SH_PFC_PIN_GROUP(ssi9_data_a),
4402 SH_PFC_PIN_GROUP(ssi9_data_b),
4403 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4404 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4405 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4406 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4407 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4408 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4409 SH_PFC_PIN_GROUP(usb0),
4410 SH_PFC_PIN_GROUP(usb1),
4411 SH_PFC_PIN_GROUP(usb30),
4412 VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4413 VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4414 VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4415 VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4416 SH_PFC_PIN_GROUP(vin4_data18_a),
4417 VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4418 VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4419 VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4420 VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4421 VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4422 VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4423 SH_PFC_PIN_GROUP(vin4_data18_b),
4424 VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4425 VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4426 SH_PFC_PIN_GROUP(vin4_sync),
4427 SH_PFC_PIN_GROUP(vin4_field),
4428 SH_PFC_PIN_GROUP(vin4_clkenb),
4429 SH_PFC_PIN_GROUP(vin4_clk),
4430 SH_PFC_PIN_GROUP(vin5_data8),
4431 SH_PFC_PIN_GROUP(vin5_data10),
4432 SH_PFC_PIN_GROUP(vin5_data12),
4433 SH_PFC_PIN_GROUP(vin5_data16),
4434 SH_PFC_PIN_GROUP(vin5_sync),
4435 SH_PFC_PIN_GROUP(vin5_field),
4436 SH_PFC_PIN_GROUP(vin5_clkenb),
4437 SH_PFC_PIN_GROUP(vin5_clk),
4438 },
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]4439 .automotive = {
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]4440 SH_PFC_PIN_GROUP(canfd0_data_a),
4441 SH_PFC_PIN_GROUP(canfd0_data_b),
4442 SH_PFC_PIN_GROUP(canfd1_data),
4443 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4444 SH_PFC_PIN_GROUP(drif0_data0_a),
4445 SH_PFC_PIN_GROUP(drif0_data1_a),
4446 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4447 SH_PFC_PIN_GROUP(drif0_data0_b),
4448 SH_PFC_PIN_GROUP(drif0_data1_b),
4449 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4450 SH_PFC_PIN_GROUP(drif0_data0_c),
4451 SH_PFC_PIN_GROUP(drif0_data1_c),
4452 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4453 SH_PFC_PIN_GROUP(drif1_data0_a),
4454 SH_PFC_PIN_GROUP(drif1_data1_a),
4455 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4456 SH_PFC_PIN_GROUP(drif1_data0_b),
4457 SH_PFC_PIN_GROUP(drif1_data1_b),
4458 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4459 SH_PFC_PIN_GROUP(drif1_data0_c),
4460 SH_PFC_PIN_GROUP(drif1_data1_c),
4461 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4462 SH_PFC_PIN_GROUP(drif2_data0_a),
4463 SH_PFC_PIN_GROUP(drif2_data1_a),
4464 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4465 SH_PFC_PIN_GROUP(drif2_data0_b),
4466 SH_PFC_PIN_GROUP(drif2_data1_b),
4467 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4468 SH_PFC_PIN_GROUP(drif3_data0_a),
4469 SH_PFC_PIN_GROUP(drif3_data1_a),
4470 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4471 SH_PFC_PIN_GROUP(drif3_data0_b),
4472 SH_PFC_PIN_GROUP(drif3_data1_b),
4473 }
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4474};
4475
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]4476static const char * const audio_clk_groups[] = {
4477 "audio_clk_a_a",
4478 "audio_clk_a_b",
4479 "audio_clk_a_c",
4480 "audio_clk_b_a",
4481 "audio_clk_b_b",
4482 "audio_clk_c_a",
4483 "audio_clk_c_b",
4484 "audio_clkout_a",
4485 "audio_clkout_b",
4486 "audio_clkout_c",
4487 "audio_clkout_d",
4488 "audio_clkout1_a",
4489 "audio_clkout1_b",
4490 "audio_clkout2_a",
4491 "audio_clkout2_b",
4492 "audio_clkout3_a",
4493 "audio_clkout3_b",
4494};
4495
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]4496static const char * const avb_groups[] = {
4497 "avb_link",
4498 "avb_magic",
4499 "avb_phy_int",
Geert Uytterhoeven350aba92018-03-12 14:53:13 +0100[diff] [blame]4500 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4501 "avb_mdio",
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]4502 "avb_mii",
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]4503 "avb_avtp_pps",
4504 "avb_avtp_match_a",
4505 "avb_avtp_capture_a",
4506 "avb_avtp_match_b",
4507 "avb_avtp_capture_b",
4508};
4509
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]4510static const char * const can0_groups[] = {
4511 "can0_data_a",
4512 "can0_data_b",
4513};
4514
4515static const char * const can1_groups[] = {
4516 "can1_data",
4517};
4518
4519static const char * const can_clk_groups[] = {
4520 "can_clk",
4521};
4522
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]4523static const char * const canfd0_groups[] = {
4524 "canfd0_data_a",
4525 "canfd0_data_b",
4526};
4527
4528static const char * const canfd1_groups[] = {
4529 "canfd1_data",
4530};
4531
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]4532static const char * const drif0_groups[] = {
4533 "drif0_ctrl_a",
4534 "drif0_data0_a",
4535 "drif0_data1_a",
4536 "drif0_ctrl_b",
4537 "drif0_data0_b",
4538 "drif0_data1_b",
4539 "drif0_ctrl_c",
4540 "drif0_data0_c",
4541 "drif0_data1_c",
4542};
4543
4544static const char * const drif1_groups[] = {
4545 "drif1_ctrl_a",
4546 "drif1_data0_a",
4547 "drif1_data1_a",
4548 "drif1_ctrl_b",
4549 "drif1_data0_b",
4550 "drif1_data1_b",
4551 "drif1_ctrl_c",
4552 "drif1_data0_c",
4553 "drif1_data1_c",
4554};
4555
4556static const char * const drif2_groups[] = {
4557 "drif2_ctrl_a",
4558 "drif2_data0_a",
4559 "drif2_data1_a",
4560 "drif2_ctrl_b",
4561 "drif2_data0_b",
4562 "drif2_data1_b",
4563};
4564
4565static const char * const drif3_groups[] = {
4566 "drif3_ctrl_a",
4567 "drif3_data0_a",
4568 "drif3_data1_a",
4569 "drif3_ctrl_b",
4570 "drif3_data0_b",
4571 "drif3_data1_b",
4572};
4573
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]4574static const char * const du_groups[] = {
4575 "du_rgb666",
4576 "du_rgb888",
4577 "du_clk_out_0",
4578 "du_clk_out_1",
4579 "du_sync",
4580 "du_oddf",
4581 "du_cde",
4582 "du_disp",
4583};
4584
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame]4585static const char * const hdmi0_groups[] = {
4586 "hdmi0_cec",
4587};
4588
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]4589static const char * const hscif0_groups[] = {
4590 "hscif0_data",
4591 "hscif0_clk",
4592 "hscif0_ctrl",
4593};
4594
4595static const char * const hscif1_groups[] = {
4596 "hscif1_data_a",
4597 "hscif1_clk_a",
4598 "hscif1_ctrl_a",
4599 "hscif1_data_b",
4600 "hscif1_clk_b",
4601 "hscif1_ctrl_b",
4602};
4603
4604static const char * const hscif2_groups[] = {
4605 "hscif2_data_a",
4606 "hscif2_clk_a",
4607 "hscif2_ctrl_a",
4608 "hscif2_data_b",
4609 "hscif2_clk_b",
4610 "hscif2_ctrl_b",
4611 "hscif2_data_c",
4612 "hscif2_clk_c",
4613 "hscif2_ctrl_c",
4614};
4615
4616static const char * const hscif3_groups[] = {
4617 "hscif3_data_a",
4618 "hscif3_clk",
4619 "hscif3_ctrl",
4620 "hscif3_data_b",
4621 "hscif3_data_c",
4622 "hscif3_data_d",
4623};
4624
4625static const char * const hscif4_groups[] = {
4626 "hscif4_data_a",
4627 "hscif4_clk",
4628 "hscif4_ctrl",
4629 "hscif4_data_b",
4630};
4631
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]4632static const char * const i2c1_groups[] = {
4633 "i2c1_a",
4634 "i2c1_b",
4635};
4636
4637static const char * const i2c2_groups[] = {
4638 "i2c2_a",
4639 "i2c2_b",
4640};
4641
4642static const char * const i2c6_groups[] = {
4643 "i2c6_a",
4644 "i2c6_b",
4645 "i2c6_c",
4646};
4647
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]4648static const char * const intc_ex_groups[] = {
4649 "intc_ex_irq0",
4650 "intc_ex_irq1",
4651 "intc_ex_irq2",
4652 "intc_ex_irq3",
4653 "intc_ex_irq4",
4654 "intc_ex_irq5",
4655};
4656
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]4657static const char * const msiof0_groups[] = {
4658 "msiof0_clk",
4659 "msiof0_sync",
4660 "msiof0_ss1",
4661 "msiof0_ss2",
4662 "msiof0_txd",
4663 "msiof0_rxd",
4664};
4665
4666static const char * const msiof1_groups[] = {
4667 "msiof1_clk_a",
4668 "msiof1_sync_a",
4669 "msiof1_ss1_a",
4670 "msiof1_ss2_a",
4671 "msiof1_txd_a",
4672 "msiof1_rxd_a",
4673 "msiof1_clk_b",
4674 "msiof1_sync_b",
4675 "msiof1_ss1_b",
4676 "msiof1_ss2_b",
4677 "msiof1_txd_b",
4678 "msiof1_rxd_b",
4679 "msiof1_clk_c",
4680 "msiof1_sync_c",
4681 "msiof1_ss1_c",
4682 "msiof1_ss2_c",
4683 "msiof1_txd_c",
4684 "msiof1_rxd_c",
4685 "msiof1_clk_d",
4686 "msiof1_sync_d",
4687 "msiof1_ss1_d",
4688 "msiof1_ss2_d",
4689 "msiof1_txd_d",
4690 "msiof1_rxd_d",
4691 "msiof1_clk_e",
4692 "msiof1_sync_e",
4693 "msiof1_ss1_e",
4694 "msiof1_ss2_e",
4695 "msiof1_txd_e",
4696 "msiof1_rxd_e",
4697 "msiof1_clk_f",
4698 "msiof1_sync_f",
4699 "msiof1_ss1_f",
4700 "msiof1_ss2_f",
4701 "msiof1_txd_f",
4702 "msiof1_rxd_f",
4703 "msiof1_clk_g",
4704 "msiof1_sync_g",
4705 "msiof1_ss1_g",
4706 "msiof1_ss2_g",
4707 "msiof1_txd_g",
4708 "msiof1_rxd_g",
4709};
4710
4711static const char * const msiof2_groups[] = {
4712 "msiof2_clk_a",
4713 "msiof2_sync_a",
4714 "msiof2_ss1_a",
4715 "msiof2_ss2_a",
4716 "msiof2_txd_a",
4717 "msiof2_rxd_a",
4718 "msiof2_clk_b",
4719 "msiof2_sync_b",
4720 "msiof2_ss1_b",
4721 "msiof2_ss2_b",
4722 "msiof2_txd_b",
4723 "msiof2_rxd_b",
4724 "msiof2_clk_c",
4725 "msiof2_sync_c",
4726 "msiof2_ss1_c",
4727 "msiof2_ss2_c",
4728 "msiof2_txd_c",
4729 "msiof2_rxd_c",
4730 "msiof2_clk_d",
4731 "msiof2_sync_d",
4732 "msiof2_ss1_d",
4733 "msiof2_ss2_d",
4734 "msiof2_txd_d",
4735 "msiof2_rxd_d",
4736};
4737
4738static const char * const msiof3_groups[] = {
4739 "msiof3_clk_a",
4740 "msiof3_sync_a",
4741 "msiof3_ss1_a",
4742 "msiof3_ss2_a",
4743 "msiof3_txd_a",
4744 "msiof3_rxd_a",
4745 "msiof3_clk_b",
4746 "msiof3_sync_b",
4747 "msiof3_ss1_b",
4748 "msiof3_ss2_b",
4749 "msiof3_txd_b",
4750 "msiof3_rxd_b",
4751 "msiof3_clk_c",
4752 "msiof3_sync_c",
4753 "msiof3_txd_c",
4754 "msiof3_rxd_c",
4755 "msiof3_clk_d",
4756 "msiof3_sync_d",
4757 "msiof3_ss1_d",
4758 "msiof3_txd_d",
4759 "msiof3_rxd_d",
4760 "msiof3_clk_e",
4761 "msiof3_sync_e",
4762 "msiof3_ss1_e",
4763 "msiof3_ss2_e",
4764 "msiof3_txd_e",
4765 "msiof3_rxd_e",
4766};
4767
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]4768static const char * const pwm0_groups[] = {
4769 "pwm0",
4770};
4771
4772static const char * const pwm1_groups[] = {
4773 "pwm1_a",
4774 "pwm1_b",
4775};
4776
4777static const char * const pwm2_groups[] = {
4778 "pwm2_a",
4779 "pwm2_b",
4780};
4781
4782static const char * const pwm3_groups[] = {
4783 "pwm3_a",
4784 "pwm3_b",
4785};
4786
4787static const char * const pwm4_groups[] = {
4788 "pwm4_a",
4789 "pwm4_b",
4790};
4791
4792static const char * const pwm5_groups[] = {
4793 "pwm5_a",
4794 "pwm5_b",
4795};
4796
4797static const char * const pwm6_groups[] = {
4798 "pwm6_a",
4799 "pwm6_b",
4800};
4801
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4802static const char * const scif0_groups[] = {
4803 "scif0_data",
4804 "scif0_clk",
4805 "scif0_ctrl",
4806};
4807
4808static const char * const scif1_groups[] = {
4809 "scif1_data_a",
4810 "scif1_clk",
4811 "scif1_ctrl",
4812 "scif1_data_b",
4813};
4814
4815static const char * const scif2_groups[] = {
4816 "scif2_data_a",
4817 "scif2_clk",
4818 "scif2_data_b",
4819};
4820
4821static const char * const scif3_groups[] = {
4822 "scif3_data_a",
4823 "scif3_clk",
4824 "scif3_ctrl",
4825 "scif3_data_b",
4826};
4827
4828static const char * const scif4_groups[] = {
4829 "scif4_data_a",
4830 "scif4_clk_a",
4831 "scif4_ctrl_a",
4832 "scif4_data_b",
4833 "scif4_clk_b",
4834 "scif4_ctrl_b",
4835 "scif4_data_c",
4836 "scif4_clk_c",
4837 "scif4_ctrl_c",
4838};
4839
4840static const char * const scif5_groups[] = {
4841 "scif5_data_a",
4842 "scif5_clk_a",
4843 "scif5_data_b",
4844 "scif5_clk_b",
4845};
4846
4847static const char * const scif_clk_groups[] = {
4848 "scif_clk_a",
4849 "scif_clk_b",
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]4850};
4851
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]4852static const char * const sdhi0_groups[] = {
4853 "sdhi0_data1",
4854 "sdhi0_data4",
4855 "sdhi0_ctrl",
4856 "sdhi0_cd",
4857 "sdhi0_wp",
4858};
4859
4860static const char * const sdhi1_groups[] = {
4861 "sdhi1_data1",
4862 "sdhi1_data4",
4863 "sdhi1_ctrl",
4864 "sdhi1_cd",
4865 "sdhi1_wp",
4866};
4867
4868static const char * const sdhi2_groups[] = {
4869 "sdhi2_data1",
4870 "sdhi2_data4",
4871 "sdhi2_data8",
4872 "sdhi2_ctrl",
4873 "sdhi2_cd_a",
4874 "sdhi2_wp_a",
4875 "sdhi2_cd_b",
4876 "sdhi2_wp_b",
4877 "sdhi2_ds",
4878};
4879
4880static const char * const sdhi3_groups[] = {
4881 "sdhi3_data1",
4882 "sdhi3_data4",
4883 "sdhi3_data8",
4884 "sdhi3_ctrl",
4885 "sdhi3_cd",
4886 "sdhi3_wp",
4887 "sdhi3_ds",
4888};
4889
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]4890static const char * const ssi_groups[] = {
4891 "ssi0_data",
4892 "ssi01239_ctrl",
4893 "ssi1_data_a",
4894 "ssi1_data_b",
4895 "ssi1_ctrl_a",
4896 "ssi1_ctrl_b",
4897 "ssi2_data_a",
4898 "ssi2_data_b",
4899 "ssi2_ctrl_a",
4900 "ssi2_ctrl_b",
4901 "ssi3_data",
4902 "ssi349_ctrl",
4903 "ssi4_data",
4904 "ssi4_ctrl",
4905 "ssi5_data",
4906 "ssi5_ctrl",
4907 "ssi6_data",
4908 "ssi6_ctrl",
4909 "ssi7_data",
4910 "ssi78_ctrl",
4911 "ssi8_data",
4912 "ssi9_data_a",
4913 "ssi9_data_b",
4914 "ssi9_ctrl_a",
4915 "ssi9_ctrl_b",
4916};
4917
Takeshi Kihara74965de2018-02-16 15:26:11 +0100[diff] [blame]4918static const char * const tmu_groups[] = {
4919 "tmu_tclk1_a",
4920 "tmu_tclk1_b",
4921 "tmu_tclk2_a",
4922 "tmu_tclk2_b",
4923};
4924
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]4925static const char * const usb0_groups[] = {
4926 "usb0",
4927};
4928
4929static const char * const usb1_groups[] = {
4930 "usb1",
4931};
4932
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]4933static const char * const usb30_groups[] = {
4934 "usb30",
4935};
4936
Ulrich Hecht8db6cba2018-02-15 13:01:28 +0100[diff] [blame]4937static const char * const vin4_groups[] = {
4938 "vin4_data8_a",
4939 "vin4_data10_a",
4940 "vin4_data12_a",
4941 "vin4_data16_a",
4942 "vin4_data18_a",
4943 "vin4_data20_a",
4944 "vin4_data24_a",
4945 "vin4_data8_b",
4946 "vin4_data10_b",
4947 "vin4_data12_b",
4948 "vin4_data16_b",
4949 "vin4_data18_b",
4950 "vin4_data20_b",
4951 "vin4_data24_b",
4952 "vin4_sync",
4953 "vin4_field",
4954 "vin4_clkenb",
4955 "vin4_clk",
4956};
4957
4958static const char * const vin5_groups[] = {
4959 "vin5_data8",
4960 "vin5_data10",
4961 "vin5_data12",
4962 "vin5_data16",
4963 "vin5_sync",
4964 "vin5_field",
4965 "vin5_clkenb",
4966 "vin5_clk",
4967};
4968
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]4969static const struct {
4970 struct sh_pfc_function common[45];
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]4971 struct sh_pfc_function automotive[6];
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]4972} pinmux_functions = {
4973 .common = {
4974 SH_PFC_FUNCTION(audio_clk),
4975 SH_PFC_FUNCTION(avb),
4976 SH_PFC_FUNCTION(can0),
4977 SH_PFC_FUNCTION(can1),
4978 SH_PFC_FUNCTION(can_clk),
4979 SH_PFC_FUNCTION(du),
4980 SH_PFC_FUNCTION(hdmi0),
4981 SH_PFC_FUNCTION(hscif0),
4982 SH_PFC_FUNCTION(hscif1),
4983 SH_PFC_FUNCTION(hscif2),
4984 SH_PFC_FUNCTION(hscif3),
4985 SH_PFC_FUNCTION(hscif4),
4986 SH_PFC_FUNCTION(i2c1),
4987 SH_PFC_FUNCTION(i2c2),
4988 SH_PFC_FUNCTION(i2c6),
4989 SH_PFC_FUNCTION(intc_ex),
4990 SH_PFC_FUNCTION(msiof0),
4991 SH_PFC_FUNCTION(msiof1),
4992 SH_PFC_FUNCTION(msiof2),
4993 SH_PFC_FUNCTION(msiof3),
4994 SH_PFC_FUNCTION(pwm0),
4995 SH_PFC_FUNCTION(pwm1),
4996 SH_PFC_FUNCTION(pwm2),
4997 SH_PFC_FUNCTION(pwm3),
4998 SH_PFC_FUNCTION(pwm4),
4999 SH_PFC_FUNCTION(pwm5),
5000 SH_PFC_FUNCTION(pwm6),
5001 SH_PFC_FUNCTION(scif0),
5002 SH_PFC_FUNCTION(scif1),
5003 SH_PFC_FUNCTION(scif2),
5004 SH_PFC_FUNCTION(scif3),
5005 SH_PFC_FUNCTION(scif4),
5006 SH_PFC_FUNCTION(scif5),
5007 SH_PFC_FUNCTION(scif_clk),
5008 SH_PFC_FUNCTION(sdhi0),
5009 SH_PFC_FUNCTION(sdhi1),
5010 SH_PFC_FUNCTION(sdhi2),
5011 SH_PFC_FUNCTION(sdhi3),
5012 SH_PFC_FUNCTION(ssi),
5013 SH_PFC_FUNCTION(tmu),
5014 SH_PFC_FUNCTION(usb0),
5015 SH_PFC_FUNCTION(usb1),
5016 SH_PFC_FUNCTION(usb30),
5017 SH_PFC_FUNCTION(vin4),
5018 SH_PFC_FUNCTION(vin5),
5019 },
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]5020 .automotive = {
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]5021 SH_PFC_FUNCTION(canfd0),
5022 SH_PFC_FUNCTION(canfd1),
5023 SH_PFC_FUNCTION(drif0),
5024 SH_PFC_FUNCTION(drif1),
5025 SH_PFC_FUNCTION(drif2),
5026 SH_PFC_FUNCTION(drif3),
5027 }
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5028};
5029
5030static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5031#define F_(x, y) FN_##y
5032#define FM(x) FN_##x
5033 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5034 0, 0,
5035 0, 0,
5036 0, 0,
5037 0, 0,
5038 0, 0,
5039 0, 0,
5040 0, 0,
5041 0, 0,
5042 0, 0,
5043 0, 0,
5044 0, 0,
5045 0, 0,
5046 0, 0,
5047 0, 0,
5048 0, 0,
5049 0, 0,
5050 GP_0_15_FN, GPSR0_15,
5051 GP_0_14_FN, GPSR0_14,
5052 GP_0_13_FN, GPSR0_13,
5053 GP_0_12_FN, GPSR0_12,
5054 GP_0_11_FN, GPSR0_11,
5055 GP_0_10_FN, GPSR0_10,
5056 GP_0_9_FN, GPSR0_9,
5057 GP_0_8_FN, GPSR0_8,
5058 GP_0_7_FN, GPSR0_7,
5059 GP_0_6_FN, GPSR0_6,
5060 GP_0_5_FN, GPSR0_5,
5061 GP_0_4_FN, GPSR0_4,
5062 GP_0_3_FN, GPSR0_3,
5063 GP_0_2_FN, GPSR0_2,
5064 GP_0_1_FN, GPSR0_1,
5065 GP_0_0_FN, GPSR0_0, }
5066 },
5067 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5068 0, 0,
5069 0, 0,
5070 0, 0,
5071 GP_1_28_FN, GPSR1_28,
5072 GP_1_27_FN, GPSR1_27,
5073 GP_1_26_FN, GPSR1_26,
5074 GP_1_25_FN, GPSR1_25,
5075 GP_1_24_FN, GPSR1_24,
5076 GP_1_23_FN, GPSR1_23,
5077 GP_1_22_FN, GPSR1_22,
5078 GP_1_21_FN, GPSR1_21,
5079 GP_1_20_FN, GPSR1_20,
5080 GP_1_19_FN, GPSR1_19,
5081 GP_1_18_FN, GPSR1_18,
5082 GP_1_17_FN, GPSR1_17,
5083 GP_1_16_FN, GPSR1_16,
5084 GP_1_15_FN, GPSR1_15,
5085 GP_1_14_FN, GPSR1_14,
5086 GP_1_13_FN, GPSR1_13,
5087 GP_1_12_FN, GPSR1_12,
5088 GP_1_11_FN, GPSR1_11,
5089 GP_1_10_FN, GPSR1_10,
5090 GP_1_9_FN, GPSR1_9,
5091 GP_1_8_FN, GPSR1_8,
5092 GP_1_7_FN, GPSR1_7,
5093 GP_1_6_FN, GPSR1_6,
5094 GP_1_5_FN, GPSR1_5,
5095 GP_1_4_FN, GPSR1_4,
5096 GP_1_3_FN, GPSR1_3,
5097 GP_1_2_FN, GPSR1_2,
5098 GP_1_1_FN, GPSR1_1,
5099 GP_1_0_FN, GPSR1_0, }
5100 },
5101 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5102 0, 0,
5103 0, 0,
5104 0, 0,
5105 0, 0,
5106 0, 0,
5107 0, 0,
5108 0, 0,
5109 0, 0,
5110 0, 0,
5111 0, 0,
5112 0, 0,
5113 0, 0,
5114 0, 0,
5115 0, 0,
5116 0, 0,
5117 0, 0,
5118 0, 0,
5119 GP_2_14_FN, GPSR2_14,
5120 GP_2_13_FN, GPSR2_13,
5121 GP_2_12_FN, GPSR2_12,
5122 GP_2_11_FN, GPSR2_11,
5123 GP_2_10_FN, GPSR2_10,
5124 GP_2_9_FN, GPSR2_9,
5125 GP_2_8_FN, GPSR2_8,
5126 GP_2_7_FN, GPSR2_7,
5127 GP_2_6_FN, GPSR2_6,
5128 GP_2_5_FN, GPSR2_5,
5129 GP_2_4_FN, GPSR2_4,
5130 GP_2_3_FN, GPSR2_3,
5131 GP_2_2_FN, GPSR2_2,
5132 GP_2_1_FN, GPSR2_1,
5133 GP_2_0_FN, GPSR2_0, }
5134 },
5135 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 0, 0,
5150 0, 0,
5151 0, 0,
5152 GP_3_15_FN, GPSR3_15,
5153 GP_3_14_FN, GPSR3_14,
5154 GP_3_13_FN, GPSR3_13,
5155 GP_3_12_FN, GPSR3_12,
5156 GP_3_11_FN, GPSR3_11,
5157 GP_3_10_FN, GPSR3_10,
5158 GP_3_9_FN, GPSR3_9,
5159 GP_3_8_FN, GPSR3_8,
5160 GP_3_7_FN, GPSR3_7,
5161 GP_3_6_FN, GPSR3_6,
5162 GP_3_5_FN, GPSR3_5,
5163 GP_3_4_FN, GPSR3_4,
5164 GP_3_3_FN, GPSR3_3,
5165 GP_3_2_FN, GPSR3_2,
5166 GP_3_1_FN, GPSR3_1,
5167 GP_3_0_FN, GPSR3_0, }
5168 },
5169 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 0, 0,
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 0, 0,
5183 0, 0,
5184 GP_4_17_FN, GPSR4_17,
5185 GP_4_16_FN, GPSR4_16,
5186 GP_4_15_FN, GPSR4_15,
5187 GP_4_14_FN, GPSR4_14,
5188 GP_4_13_FN, GPSR4_13,
5189 GP_4_12_FN, GPSR4_12,
5190 GP_4_11_FN, GPSR4_11,
5191 GP_4_10_FN, GPSR4_10,
5192 GP_4_9_FN, GPSR4_9,
5193 GP_4_8_FN, GPSR4_8,
5194 GP_4_7_FN, GPSR4_7,
5195 GP_4_6_FN, GPSR4_6,
5196 GP_4_5_FN, GPSR4_5,
5197 GP_4_4_FN, GPSR4_4,
5198 GP_4_3_FN, GPSR4_3,
5199 GP_4_2_FN, GPSR4_2,
5200 GP_4_1_FN, GPSR4_1,
5201 GP_4_0_FN, GPSR4_0, }
5202 },
5203 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 GP_5_25_FN, GPSR5_25,
5211 GP_5_24_FN, GPSR5_24,
5212 GP_5_23_FN, GPSR5_23,
5213 GP_5_22_FN, GPSR5_22,
5214 GP_5_21_FN, GPSR5_21,
5215 GP_5_20_FN, GPSR5_20,
5216 GP_5_19_FN, GPSR5_19,
5217 GP_5_18_FN, GPSR5_18,
5218 GP_5_17_FN, GPSR5_17,
5219 GP_5_16_FN, GPSR5_16,
5220 GP_5_15_FN, GPSR5_15,
5221 GP_5_14_FN, GPSR5_14,
5222 GP_5_13_FN, GPSR5_13,
5223 GP_5_12_FN, GPSR5_12,
5224 GP_5_11_FN, GPSR5_11,
5225 GP_5_10_FN, GPSR5_10,
5226 GP_5_9_FN, GPSR5_9,
5227 GP_5_8_FN, GPSR5_8,
5228 GP_5_7_FN, GPSR5_7,
5229 GP_5_6_FN, GPSR5_6,
5230 GP_5_5_FN, GPSR5_5,
5231 GP_5_4_FN, GPSR5_4,
5232 GP_5_3_FN, GPSR5_3,
5233 GP_5_2_FN, GPSR5_2,
5234 GP_5_1_FN, GPSR5_1,
5235 GP_5_0_FN, GPSR5_0, }
5236 },
5237 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5238 GP_6_31_FN, GPSR6_31,
5239 GP_6_30_FN, GPSR6_30,
5240 GP_6_29_FN, GPSR6_29,
5241 GP_6_28_FN, GPSR6_28,
5242 GP_6_27_FN, GPSR6_27,
5243 GP_6_26_FN, GPSR6_26,
5244 GP_6_25_FN, GPSR6_25,
5245 GP_6_24_FN, GPSR6_24,
5246 GP_6_23_FN, GPSR6_23,
5247 GP_6_22_FN, GPSR6_22,
5248 GP_6_21_FN, GPSR6_21,
5249 GP_6_20_FN, GPSR6_20,
5250 GP_6_19_FN, GPSR6_19,
5251 GP_6_18_FN, GPSR6_18,
5252 GP_6_17_FN, GPSR6_17,
5253 GP_6_16_FN, GPSR6_16,
5254 GP_6_15_FN, GPSR6_15,
5255 GP_6_14_FN, GPSR6_14,
5256 GP_6_13_FN, GPSR6_13,
5257 GP_6_12_FN, GPSR6_12,
5258 GP_6_11_FN, GPSR6_11,
5259 GP_6_10_FN, GPSR6_10,
5260 GP_6_9_FN, GPSR6_9,
5261 GP_6_8_FN, GPSR6_8,
5262 GP_6_7_FN, GPSR6_7,
5263 GP_6_6_FN, GPSR6_6,
5264 GP_6_5_FN, GPSR6_5,
5265 GP_6_4_FN, GPSR6_4,
5266 GP_6_3_FN, GPSR6_3,
5267 GP_6_2_FN, GPSR6_2,
5268 GP_6_1_FN, GPSR6_1,
5269 GP_6_0_FN, GPSR6_0, }
5270 },
5271 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5272 0, 0,
5273 0, 0,
5274 0, 0,
5275 0, 0,
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 0, 0,
5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 0, 0,
5291 0, 0,
5292 0, 0,
5293 0, 0,
5294 0, 0,
5295 0, 0,
5296 0, 0,
5297 0, 0,
5298 0, 0,
5299 0, 0,
5300 GP_7_3_FN, GPSR7_3,
5301 GP_7_2_FN, GPSR7_2,
5302 GP_7_1_FN, GPSR7_1,
5303 GP_7_0_FN, GPSR7_0, }
5304 },
5305#undef F_
5306#undef FM
5307
5308#define F_(x, y) x,
5309#define FM(x) FN_##x,
5310 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5311 IP0_31_28
5312 IP0_27_24
5313 IP0_23_20
5314 IP0_19_16
5315 IP0_15_12
5316 IP0_11_8
5317 IP0_7_4
5318 IP0_3_0 }
5319 },
5320 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5321 IP1_31_28
5322 IP1_27_24
5323 IP1_23_20
5324 IP1_19_16
5325 IP1_15_12
5326 IP1_11_8
5327 IP1_7_4
5328 IP1_3_0 }
5329 },
5330 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5331 IP2_31_28
5332 IP2_27_24
5333 IP2_23_20
5334 IP2_19_16
5335 IP2_15_12
5336 IP2_11_8
5337 IP2_7_4
5338 IP2_3_0 }
5339 },
5340 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5341 IP3_31_28
5342 IP3_27_24
5343 IP3_23_20
5344 IP3_19_16
5345 IP3_15_12
5346 IP3_11_8
5347 IP3_7_4
5348 IP3_3_0 }
5349 },
5350 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5351 IP4_31_28
5352 IP4_27_24
5353 IP4_23_20
5354 IP4_19_16
5355 IP4_15_12
5356 IP4_11_8
5357 IP4_7_4
5358 IP4_3_0 }
5359 },
5360 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5361 IP5_31_28
5362 IP5_27_24
5363 IP5_23_20
5364 IP5_19_16
5365 IP5_15_12
5366 IP5_11_8
5367 IP5_7_4
5368 IP5_3_0 }
5369 },
5370 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5371 IP6_31_28
5372 IP6_27_24
5373 IP6_23_20
5374 IP6_19_16
5375 IP6_15_12
5376 IP6_11_8
5377 IP6_7_4
5378 IP6_3_0 }
5379 },
5380 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5381 IP7_31_28
5382 IP7_27_24
5383 IP7_23_20
5384 IP7_19_16
Takeshi Kihara89217782017-07-13 01:55:43 +0900[diff] [blame]5385 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5386 IP7_11_8
5387 IP7_7_4
5388 IP7_3_0 }
5389 },
5390 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5391 IP8_31_28
5392 IP8_27_24
5393 IP8_23_20
5394 IP8_19_16
5395 IP8_15_12
5396 IP8_11_8
5397 IP8_7_4
5398 IP8_3_0 }
5399 },
5400 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5401 IP9_31_28
5402 IP9_27_24
5403 IP9_23_20
5404 IP9_19_16
5405 IP9_15_12
5406 IP9_11_8
5407 IP9_7_4
5408 IP9_3_0 }
5409 },
5410 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5411 IP10_31_28
5412 IP10_27_24
5413 IP10_23_20
5414 IP10_19_16
5415 IP10_15_12
5416 IP10_11_8
5417 IP10_7_4
5418 IP10_3_0 }
5419 },
5420 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5421 IP11_31_28
5422 IP11_27_24
5423 IP11_23_20
5424 IP11_19_16
5425 IP11_15_12
5426 IP11_11_8
5427 IP11_7_4
5428 IP11_3_0 }
5429 },
5430 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5431 IP12_31_28
5432 IP12_27_24
5433 IP12_23_20
5434 IP12_19_16
5435 IP12_15_12
5436 IP12_11_8
5437 IP12_7_4
5438 IP12_3_0 }
5439 },
5440 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5441 IP13_31_28
5442 IP13_27_24
5443 IP13_23_20
5444 IP13_19_16
5445 IP13_15_12
5446 IP13_11_8
5447 IP13_7_4
5448 IP13_3_0 }
5449 },
5450 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5451 IP14_31_28
5452 IP14_27_24
5453 IP14_23_20
5454 IP14_19_16
5455 IP14_15_12
5456 IP14_11_8
5457 IP14_7_4
5458 IP14_3_0 }
5459 },
5460 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5461 IP15_31_28
5462 IP15_27_24
5463 IP15_23_20
5464 IP15_19_16
5465 IP15_15_12
5466 IP15_11_8
5467 IP15_7_4
5468 IP15_3_0 }
5469 },
5470 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5471 IP16_31_28
5472 IP16_27_24
5473 IP16_23_20
5474 IP16_19_16
5475 IP16_15_12
5476 IP16_11_8
5477 IP16_7_4
5478 IP16_3_0 }
5479 },
5480 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5481 IP17_31_28
5482 IP17_27_24
5483 IP17_23_20
5484 IP17_19_16
5485 IP17_15_12
5486 IP17_11_8
5487 IP17_7_4
5488 IP17_3_0 }
5489 },
5490 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5491 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5492 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5493 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5494 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5495 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5496 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5497 IP18_7_4
5498 IP18_3_0 }
5499 },
5500#undef F_
5501#undef FM
5502
5503#define F_(x, y) x,
5504#define FM(x) FN_##x,
5505 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5506 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5507 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5508 MOD_SEL0_31_30_29
5509 MOD_SEL0_28_27
5510 MOD_SEL0_26_25_24
5511 MOD_SEL0_23
5512 MOD_SEL0_22
5513 MOD_SEL0_21
5514 MOD_SEL0_20
5515 MOD_SEL0_19
5516 MOD_SEL0_18_17
5517 MOD_SEL0_16
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]5518 0, 0, /* RESERVED 15 */
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5519 MOD_SEL0_14_13
5520 MOD_SEL0_12
5521 MOD_SEL0_11
5522 MOD_SEL0_10
5523 MOD_SEL0_9_8
5524 MOD_SEL0_7_6
5525 MOD_SEL0_5
5526 MOD_SEL0_4_3
5527 /* RESERVED 2, 1, 0 */
5528 0, 0, 0, 0, 0, 0, 0, 0 }
5529 },
5530 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5531 2, 3, 1, 2, 3, 1, 1, 2, 1,
5532 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5533 MOD_SEL1_31_30
5534 MOD_SEL1_29_28_27
5535 MOD_SEL1_26
5536 MOD_SEL1_25_24
5537 MOD_SEL1_23_22_21
5538 MOD_SEL1_20
5539 MOD_SEL1_19
5540 MOD_SEL1_18_17
5541 MOD_SEL1_16
5542 MOD_SEL1_15_14
5543 MOD_SEL1_13
5544 MOD_SEL1_12
5545 MOD_SEL1_11
5546 MOD_SEL1_10
5547 MOD_SEL1_9
5548 0, 0, 0, 0, /* RESERVED 8, 7 */
5549 MOD_SEL1_6
5550 MOD_SEL1_5
5551 MOD_SEL1_4
5552 MOD_SEL1_3
5553 MOD_SEL1_2
5554 MOD_SEL1_1
5555 MOD_SEL1_0 }
5556 },
5557 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5558 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5559 4, 4, 4, 3, 1) {
5560 MOD_SEL2_31
5561 MOD_SEL2_30
5562 MOD_SEL2_29
5563 MOD_SEL2_28_27
5564 MOD_SEL2_26
5565 MOD_SEL2_25_24_23
5566 MOD_SEL2_22
5567 MOD_SEL2_21
5568 MOD_SEL2_20
5569 MOD_SEL2_19
5570 MOD_SEL2_18
5571 MOD_SEL2_17
5572 /* RESERVED 16 */
5573 0, 0,
5574 /* RESERVED 15, 14, 13, 12 */
5575 0, 0, 0, 0, 0, 0, 0, 0,
5576 0, 0, 0, 0, 0, 0, 0, 0,
5577 /* RESERVED 11, 10, 9, 8 */
5578 0, 0, 0, 0, 0, 0, 0, 0,
5579 0, 0, 0, 0, 0, 0, 0, 0,
5580 /* RESERVED 7, 6, 5, 4 */
5581 0, 0, 0, 0, 0, 0, 0, 0,
5582 0, 0, 0, 0, 0, 0, 0, 0,
5583 /* RESERVED 3, 2, 1 */
5584 0, 0, 0, 0, 0, 0, 0, 0,
5585 MOD_SEL2_0 }
5586 },
5587 { },
5588};
5589
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5590static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5591 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5592 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5593 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5594 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5595 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5596 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5597 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5598 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5599 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5600 } },
5601 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5602 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5603 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5604 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5605 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5606 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5607 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5608 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5609 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5610 } },
5611 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5612 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5613 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5614 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5615 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5616 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5617 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5618 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5619 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5620 } },
5621 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5622 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5623 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5624 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5625 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5626 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5627 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5628 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5629 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5630 } },
5631 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5632 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5633 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5634 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5635 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5636 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5637 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5638 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5639 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5640 } },
5641 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5642 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5643 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5644 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5645 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5646 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5647 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5648 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5649 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5650 } },
5651 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5652 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5653 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5654 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5655 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5656 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5657 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5658 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5659 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5660 } },
5661 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5662 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5663 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5664 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5665 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5666 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5667 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5668 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5669 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5670 } },
5671 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5672 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5673 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5674 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5675 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5676 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5677 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5678 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5679 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5680 } },
5681 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5682 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5683 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5684 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5685 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5686 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5687 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5688 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5689 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5690 } },
5691 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5692 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5693 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5694 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5695 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5696 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5697 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5698 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5699 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5700 } },
5701 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5702 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5703 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5704 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5705 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5706 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5707 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5708 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5709 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5710 } },
5711 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5712 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5713 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5714 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5715 } },
5716 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5717 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5718 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5719 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5720 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5721 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5722 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5723 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5724 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5725 } },
5726 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5727 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5728 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5729 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5730 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5731 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5732 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5733 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5734 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5735 } },
5736 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5737 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5738 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5739 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5740 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5741 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5742 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5743 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5744 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5745 } },
5746 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5747 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5748 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5749 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5750 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5751 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5752 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5753 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5754 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5755 } },
5756 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5757 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5758 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5759 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5760 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5761 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5762 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5763 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5764 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5765 } },
5766 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5767 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5768 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5769 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5770 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5771 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5772 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5773 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5774 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5777 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5778 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5779 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5780 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5781 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5782 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5783 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5784 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5787 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5788 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5789 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5790 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5791 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5792 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5793 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5794 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5797 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5798 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5799 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5800 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]5801 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5802 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5803 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5804 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5807 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5808 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5809 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5810 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5811 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5812 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5813 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5814 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5817 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5818 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5819 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5820 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5821 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5822 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5823 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5824 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5827 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5828 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5829 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5830 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5831 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5832 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5833 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5834 } },
5835 { },
5836};
5837
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]5838enum ioctrl_regs {
5839 POCCTRL,
5840};
5841
5842static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5843 [POCCTRL] = { 0xe6060380, },
5844 { /* sentinel */ },
5845};
5846
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5847static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5848{
5849 int bit = -EINVAL;
5850
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]5851 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5852
5853 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5854 bit = pin & 0x1f;
5855
5856 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5857 bit = (pin & 0x1f) + 12;
5858
5859 return bit;
5860}
5861
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5862static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5863 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5864 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5865 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5866 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5867 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5868 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5869 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5870 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5871 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5872 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5873 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5874 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5875 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5876 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5877 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5878 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5879 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5880 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5881 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5882 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5883 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5884 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5885 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5886 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5887 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5888 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5889 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5890 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5891 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5892 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5893 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5894 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5895 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5896 } },
5897 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5898 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5899 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5900 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5901 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5902 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5903 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5904 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5905 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5906 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5907 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5908 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5909 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5910 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5911 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5912 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5913 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5914 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5915 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5916 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5917 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5918 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5919 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5920 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5921 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5922 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5923 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5924 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5925 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5926 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5927 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5928 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5929 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5930 } },
5931 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5932 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5933 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5934 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5935 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5936 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5937 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5938 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5939 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5940 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5941 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5942 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5943 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5944 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5945 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5946 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5947 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5948 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5949 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5950 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5951 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5952 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5953 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5954 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5955 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5956 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5957 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5958 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5959 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5960 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5961 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5962 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5963 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5964 } },
5965 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5966 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5967 [ 1] = PIN_NONE,
5968 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5969 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5970 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5971 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5972 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5973 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5974 [ 8] = PIN_NONE,
5975 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5976 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5977 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5978 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5979 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5980 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5981 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5982 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5983 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5984 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5985 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5986 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5987 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5988 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5989 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5990 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5991 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5992 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5993 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5994 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5995 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5996 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5997 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5998 } },
5999 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6000 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6001 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6002 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6003 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6004 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6005 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6006 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6007 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6008 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6009 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6010 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6011 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6012 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6013 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6014 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6015 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]6016 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6017 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6018 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6019 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]6020 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6021 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6022 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6023 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6024 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6025 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6026 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6027 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6028 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6029 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6030 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6031 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6032 } },
6033 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6034 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6035 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6036 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6037 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6038 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6039 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6040 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6041 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6042 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6043 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6044 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6045 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6046 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6047 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6048 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6049 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6050 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6051 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6052 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6053 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6054 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6055 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6056 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6057 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6058 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6059 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6060 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6061 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6062 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6063 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6064 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6065 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6066 } },
6067 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6068 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6069 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6070 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6071 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6072 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6073 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6074 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6075 [ 7] = PIN_NONE,
6076 [ 8] = PIN_NONE,
6077 [ 9] = PIN_NONE,
6078 [10] = PIN_NONE,
6079 [11] = PIN_NONE,
6080 [12] = PIN_NONE,
6081 [13] = PIN_NONE,
6082 [14] = PIN_NONE,
6083 [15] = PIN_NONE,
6084 [16] = PIN_NONE,
6085 [17] = PIN_NONE,
6086 [18] = PIN_NONE,
6087 [19] = PIN_NONE,
6088 [20] = PIN_NONE,
6089 [21] = PIN_NONE,
6090 [22] = PIN_NONE,
6091 [23] = PIN_NONE,
6092 [24] = PIN_NONE,
6093 [25] = PIN_NONE,
6094 [26] = PIN_NONE,
6095 [27] = PIN_NONE,
6096 [28] = PIN_NONE,
6097 [29] = PIN_NONE,
6098 [30] = PIN_NONE,
6099 [31] = PIN_NONE,
6100 } },
6101 { /* sentinel */ },
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6102};
6103
6104static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6105 unsigned int pin)
6106{
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6107 const struct pinmux_bias_reg *reg;
6108 unsigned int bit;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6109
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6110 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6111 if (!reg)
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6112 return PIN_CONFIG_BIAS_DISABLE;
6113
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6114 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6115 return PIN_CONFIG_BIAS_DISABLE;
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6116 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6117 return PIN_CONFIG_BIAS_PULL_UP;
6118 else
6119 return PIN_CONFIG_BIAS_PULL_DOWN;
6120}
6121
6122static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6123 unsigned int bias)
6124{
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6125 const struct pinmux_bias_reg *reg;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6126 u32 enable, updown;
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6127 unsigned int bit;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6128
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6129 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6130 if (!reg)
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6131 return;
6132
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6133 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6134 if (bias != PIN_CONFIG_BIAS_DISABLE)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6135 enable |= BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6136
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6137 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6138 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6139 updown |= BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6140
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6141 sh_pfc_write(pfc, reg->pud, updown);
6142 sh_pfc_write(pfc, reg->puen, enable);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6143}
6144
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]6145static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6146 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]6147 .get_bias = r8a7796_pinmux_get_bias,
6148 .set_bias = r8a7796_pinmux_set_bias,
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]6149};
6150
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]6151#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6152const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6153 .name = "r8a774a1_pfc",
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]6154 .ops = &r8a7796_pinmux_ops,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]6155 .unlock_reg = 0xe6060000, /* PMMR */
6156
6157 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6158
6159 .pins = pinmux_pins,
6160 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]6161 .groups = pinmux_groups.common,
6162 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6163 .functions = pinmux_functions.common,
6164 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]6165
6166 .cfg_regs = pinmux_config_regs,
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]6167 .drive_regs = pinmux_drive_regs,
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]6168 .bias_regs = pinmux_bias_regs,
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]6169 .ioctrl_regs = pinmux_ioctrl_regs,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]6170
6171 .pinmux_data = pinmux_data,
6172 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6173};
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]6174#endif
6175
6176#ifdef CONFIG_PINCTRL_PFC_R8A7796
6177const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6178 .name = "r8a77960_pfc",
6179 .ops = &r8a7796_pinmux_ops,
6180 .unlock_reg = 0xe6060000, /* PMMR */
6181
6182 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6183
6184 .pins = pinmux_pins,
6185 .nr_pins = ARRAY_SIZE(pinmux_pins),
6186 .groups = pinmux_groups.common,
6187 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]6188 ARRAY_SIZE(pinmux_groups.automotive),
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]6189 .functions = pinmux_functions.common,
6190 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
Geert Uytterhoevena97f3402018-09-26 15:29:54 +0200[diff] [blame]6191 ARRAY_SIZE(pinmux_functions.automotive),
Biju Das91d627a2018-08-13 14:52:32 +0100[diff] [blame]6192
6193 .cfg_regs = pinmux_config_regs,
6194 .drive_regs = pinmux_drive_regs,
6195 .bias_regs = pinmux_bias_regs,
6196 .ioctrl_regs = pinmux_ioctrl_regs,
6197
6198 .pinmux_data = pinmux_data,
6199 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6200};
6201#endif