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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 71c236adf037543284990e22f0241abec57cf860 / . / drivers / pinctrl / sh-pfc / pfc-r8a7796.c
blob: 8d1046262ed4b7ee2aabf0031b60cfa5c257415b [file] [log] [blame]
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1/*
2 * R8A7796 processor support - PFC hardware block.
3 *
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]25
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]26#define CPU_ALL_PORT(fn, sfx) \
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]39/*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
43
44/* GPSR0 */
45#define GPSR0_15 F_(D15, IP7_11_8)
46#define GPSR0_14 F_(D14, IP7_7_4)
47#define GPSR0_13 F_(D13, IP7_3_0)
48#define GPSR0_12 F_(D12, IP6_31_28)
49#define GPSR0_11 F_(D11, IP6_27_24)
50#define GPSR0_10 F_(D10, IP6_23_20)
51#define GPSR0_9 F_(D9, IP6_19_16)
52#define GPSR0_8 F_(D8, IP6_15_12)
53#define GPSR0_7 F_(D7, IP6_11_8)
54#define GPSR0_6 F_(D6, IP6_7_4)
55#define GPSR0_5 F_(D5, IP6_3_0)
56#define GPSR0_4 F_(D4, IP5_31_28)
57#define GPSR0_3 F_(D3, IP5_27_24)
58#define GPSR0_2 F_(D2, IP5_23_20)
59#define GPSR0_1 F_(D1, IP5_19_16)
60#define GPSR0_0 F_(D0, IP5_15_12)
61
62/* GPSR1 */
63#define GPSR1_28 FM(CLKOUT)
64#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65#define GPSR1_26 F_(WE1_N, IP5_7_4)
66#define GPSR1_25 F_(WE0_N, IP5_3_0)
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20)
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]70#define GPSR1_21 F_(CS1_N, IP4_19_16)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4)
74#define GPSR1_17 F_(A17, IP4_3_0)
75#define GPSR1_16 F_(A16, IP3_31_28)
76#define GPSR1_15 F_(A15, IP3_27_24)
77#define GPSR1_14 F_(A14, IP3_23_20)
78#define GPSR1_13 F_(A13, IP3_19_16)
79#define GPSR1_12 F_(A12, IP3_15_12)
80#define GPSR1_11 F_(A11, IP3_11_8)
81#define GPSR1_10 F_(A10, IP3_7_4)
82#define GPSR1_9 F_(A9, IP3_3_0)
83#define GPSR1_8 F_(A8, IP2_31_28)
84#define GPSR1_7 F_(A7, IP2_27_24)
85#define GPSR1_6 F_(A6, IP2_23_20)
86#define GPSR1_5 F_(A5, IP2_19_16)
87#define GPSR1_4 F_(A4, IP2_15_12)
88#define GPSR1_3 F_(A3, IP2_11_8)
89#define GPSR1_2 F_(A2, IP2_7_4)
90#define GPSR1_1 F_(A1, IP2_3_0)
91#define GPSR1_0 F_(A0, IP1_31_28)
92
93/* GPSR2 */
94#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100#define GPSR2_8 F_(PWM2_A, IP1_27_24)
101#define GPSR2_7 F_(PWM1_A, IP1_23_20)
102#define GPSR2_6 F_(PWM0, IP1_19_16)
103#define GPSR2_5 F_(IRQ5, IP1_15_12)
104#define GPSR2_4 F_(IRQ4, IP1_11_8)
105#define GPSR2_3 F_(IRQ3, IP1_7_4)
106#define GPSR2_2 F_(IRQ2, IP1_3_0)
107#define GPSR2_1 F_(IRQ1, IP0_31_28)
108#define GPSR2_0 F_(IRQ0, IP0_27_24)
109
110/* GPSR3 */
111#define GPSR3_15 F_(SD1_WP, IP11_23_20)
112#define GPSR3_14 F_(SD1_CD, IP11_19_16)
113#define GPSR3_13 F_(SD0_WP, IP11_15_12)
114#define GPSR3_12 F_(SD0_CD, IP11_11_8)
115#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
127
128/* GPSR4 */
Geert Uytterhoeven0f866a92016-10-21 17:30:59 +0200[diff] [blame]129#define GPSR4_17 F_(SD3_DS, IP11_7_4)
130#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]134#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
Geert Uytterhoeven0f866a92016-10-21 17:30:59 +0200[diff] [blame]140#define GPSR4_6 F_(SD2_DS, IP9_27_24)
141#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]145#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
147
148/* GPSR5 */
149#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152#define GPSR5_22 FM(MSIOF0_RXD)
153#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154#define GPSR5_20 FM(MSIOF0_TXD)
155#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157#define GPSR5_17 FM(MSIOF0_SCK)
158#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160#define GPSR5_14 F_(HTX0, IP13_19_16)
161#define GPSR5_13 F_(HRX0, IP13_15_12)
162#define GPSR5_12 F_(HSCK0, IP13_11_8)
163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]166#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]170#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28)
174#define GPSR5_0 F_(SCK0, IP11_27_24)
175
176/* GPSR6 */
177#define GPSR6_31 F_(GP6_31, IP18_7_4)
178#define GPSR6_30 F_(GP6_30, IP18_3_0)
179#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195#define GPSR6_13 FM(SSI_SDATA5)
196#define GPSR6_12 FM(SSI_WS5)
197#define GPSR6_11 FM(SSI_SCK5)
198#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]202#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]204#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]207#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]209
210/* GPSR7 */
211#define GPSR7_3 FM(GP7_03)
212#define GPSR7_2 FM(HDMI0_CEC)
213#define GPSR7_1 FM(AVS2)
214#define GPSR7_0 FM(AVS1)
215
216
217/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara70070192017-06-01 22:37:24 +0900[diff] [blame]224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharafbd81e32017-11-16 12:17:18 +0900[diff] [blame]227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]256#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]281#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara6fb18702017-07-13 01:55:40 +0900[diff] [blame]293#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0a5e7372017-07-13 01:55:44 +0900[diff] [blame]299#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara6fb18702017-07-13 01:55:40 +0900[diff] [blame]300#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]311#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
313/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]321#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]325#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]329#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]340#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]342
343/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]347#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]349#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]368#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]371
372#define PINMUX_GPSR \
373\
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
406
407#define PINMUX_IPSR \
408\
409FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417\
418FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
Takeshi Kihara89217782017-07-13 01:55:43 +0900[diff] [blame]421FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]422FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426\
427FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435\
436FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444\
445FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453
454/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
455#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]465#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
472#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]473
474/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
475#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]480#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]481#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]488#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]489#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497
Wolfram Sang94888a42017-10-09 10:37:25 +0200[diff] [blame]498/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]505#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]506#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
509#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
510#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
511#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
512
513#define PINMUX_MOD_SELS \
514\
515MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518MOD_SEL0_28_27 MOD_SEL2_28_27 \
519MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521MOD_SEL0_23 MOD_SEL1_23_22_21 \
522MOD_SEL0_22 MOD_SEL2_22 \
523MOD_SEL0_21 MOD_SEL2_21 \
524MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528MOD_SEL0_16 MOD_SEL1_16 \
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]529 MOD_SEL1_15_14 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]530MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532MOD_SEL0_12 MOD_SEL1_12 \
533MOD_SEL0_11 MOD_SEL1_11 \
534MOD_SEL0_10 MOD_SEL1_10 \
535MOD_SEL0_9_8 MOD_SEL1_9 \
536MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538MOD_SEL0_5 MOD_SEL1_5 \
539MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
Takeshi Kiharae56c5132017-07-13 01:55:45 +0900[diff] [blame]541 MOD_SEL1_2 \
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
544
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]545/*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549#define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]561
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]562enum {
563 PINMUX_RESERVED = 0,
564
565 PINMUX_DATA_BEGIN,
566 GP_ALL(DATA),
567 PINMUX_DATA_END,
568
569#define F_(x, y)
570#define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
572 GP_ALL(FN),
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577#undef F_
578#undef FM
579
580#define F_(x, y)
581#define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]586 PINMUX_STATIC
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]587 PINMUX_MARK_END,
588#undef F_
589#undef FM
590};
591
592static const u16 pinmux_data[] = {
593 PINMUX_DATA_GP_ALL(),
594
595 PINMUX_SINGLE(AVS1),
596 PINMUX_SINGLE(AVS2),
597 PINMUX_SINGLE(CLKOUT),
598 PINMUX_SINGLE(GP7_03),
599 PINMUX_SINGLE(HDMI0_CEC),
600 PINMUX_SINGLE(MSIOF0_RXD),
601 PINMUX_SINGLE(MSIOF0_SCK),
602 PINMUX_SINGLE(MSIOF0_TXD),
603 PINMUX_SINGLE(SSI_SCK5),
604 PINMUX_SINGLE(SSI_SDATA5),
605 PINMUX_SINGLE(SSI_WS5),
606
607 /* IPSR0 */
608 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
609 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
610
611 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
612 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
614
615 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
616 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
618
619 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
620 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
622
623 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
626
627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
633 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
634 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
638
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
Takeshi Kihara1554b982017-06-01 22:25:30 +0900[diff] [blame]645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]646
647 /* IPSR1 */
648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
649 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
650 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
651 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]657 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
658 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
661
662 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
663 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
668
669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]671 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
672 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
673 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697 /* IPSR2 */
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758 /* IPSR3 */
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812 /* IPSR4 */
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
Takeshi Kiharabf1a8aa2017-07-13 01:55:47 +0900[diff] [blame]831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858 /* IPSR5 */
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908 /* IPSR6 */
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960 /* IPSR7 */
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002 /* IPSR8 */
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051 /* IPSR9 */
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072
1073 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1074 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1075
1076 /* IPSR10 */
1077 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1078 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1079
1080 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1081 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1082
1083 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1084 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1085
1086 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1087 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1088
1089 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1090 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1091
1092 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1093 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1094 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1095
1096 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1097 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1099
1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1102 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1103
1104 /* IPSR11 */
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1107 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1108
1109 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1110 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1111
1112 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1113 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1114 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1116
1117 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1118 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1119 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1120
1121 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1122 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1123 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1126 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1145
1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1206
1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1266
1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Takeshi Kihara8b446c42018-02-16 15:25:04 +0100[diff] [blame]1270 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
Kuninori Morimoto54040322017-05-12 00:12:41 +0000[diff] [blame]1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1307
1308 /* IPSR15 */
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1310
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1313
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1358
1359 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1360 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1363 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1364
1365 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1366 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1367 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1368 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1370 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1372
1373 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1374 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1375 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1376 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1378 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1380
1381 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1382 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1383 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1384 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
Takeshi Kiharaf21b4fc2017-07-13 01:55:42 +0900[diff] [blame]1388 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1389
1390 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1391 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1392 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1393 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1395 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1397
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1398 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1399 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1400 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1402 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1403 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1404 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
Takeshi Kihara04ee2ab2017-07-13 01:55:36 +0900[diff] [blame]1405 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1406
1407 /* IPSR17 */
1408 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1409 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1410
1411 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
Takeshi Kiharadda7e6c2017-07-13 01:55:38 +0900[diff] [blame]1412 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1413 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1414 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1416
1417 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1418 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1419 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1420 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1422 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1423 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1424
1425 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1426 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1427 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1428 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1429 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1431
1432 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1433 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1434 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1435 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1436 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1437 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1438 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1439 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1440 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1441
1442 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1443 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1444 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1445 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1446 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1447 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1449 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1451
1452 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1453 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1454 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1455 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
Takeshi Kihara7aa36a32017-07-13 01:55:34 +0900[diff] [blame]1456 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1457 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1458 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
Takeshi Kiharaf21b4fc2017-07-13 01:55:42 +0900[diff] [blame]1459 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1460 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1461 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1462 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1463
1464 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1465 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1466 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1467 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1468 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1469 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1470 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]1471 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1472 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1473
1474 /* IPSR18 */
1475 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1476 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1477 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1478 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1479 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1480 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1481 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1482 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1483 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1484
1485 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1486 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Takeshi Kiharab418c462018-02-16 15:25:03 +0100[diff] [blame]1487 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1488 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1489 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1490 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1491 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1492 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1493 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1494
1495 /* I2C */
1496 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1497 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1499
1500/*
1501 * Static pins can not be muxed between different functions but
1502 * still needs a mark entry in the pinmux list. Add each static
1503 * pin to the list without an associated function. The sh-pfc
1504 * core will do the right thing and skip trying to mux then pin
1505 * while still applying configuration to it
1506 */
1507#define FM(x) PINMUX_DATA(x##_MARK, 0),
1508 PINMUX_STATIC
1509#undef FM
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1510};
1511
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1512/*
1513 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1514 * Physical layout rows: A - AW, cols: 1 - 39.
1515 */
1516#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1517#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1518#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]1519#define PIN_NONE U16_MAX
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1520
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1521static const struct sh_pfc_pin pinmux_pins[] = {
1522 PINMUX_GPIO_GP_ALL(),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1523
1524 /*
1525 * Pins not associated with a GPIO port.
1526 *
1527 * The pin positions are different between different r8a7796
1528 * packages, all that is needed for the pfc driver is a unique
1529 * number for each pin. To this end use the pin layout from
1530 * R-Car M3SiP to calculate a unique number for each pin.
1531 */
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]1532 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]1574};
1575
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]1576/* - AUDIO CLOCK ------------------------------------------------------------ */
1577static const unsigned int audio_clk_a_a_pins[] = {
1578 /* CLK A */
1579 RCAR_GP_PIN(6, 22),
1580};
1581static const unsigned int audio_clk_a_a_mux[] = {
1582 AUDIO_CLKA_A_MARK,
1583};
1584static const unsigned int audio_clk_a_b_pins[] = {
1585 /* CLK A */
1586 RCAR_GP_PIN(5, 4),
1587};
1588static const unsigned int audio_clk_a_b_mux[] = {
1589 AUDIO_CLKA_B_MARK,
1590};
1591static const unsigned int audio_clk_a_c_pins[] = {
1592 /* CLK A */
1593 RCAR_GP_PIN(5, 19),
1594};
1595static const unsigned int audio_clk_a_c_mux[] = {
1596 AUDIO_CLKA_C_MARK,
1597};
1598static const unsigned int audio_clk_b_a_pins[] = {
1599 /* CLK B */
1600 RCAR_GP_PIN(5, 12),
1601};
1602static const unsigned int audio_clk_b_a_mux[] = {
1603 AUDIO_CLKB_A_MARK,
1604};
1605static const unsigned int audio_clk_b_b_pins[] = {
1606 /* CLK B */
1607 RCAR_GP_PIN(6, 23),
1608};
1609static const unsigned int audio_clk_b_b_mux[] = {
1610 AUDIO_CLKB_B_MARK,
1611};
1612static const unsigned int audio_clk_c_a_pins[] = {
1613 /* CLK C */
1614 RCAR_GP_PIN(5, 21),
1615};
1616static const unsigned int audio_clk_c_a_mux[] = {
1617 AUDIO_CLKC_A_MARK,
1618};
1619static const unsigned int audio_clk_c_b_pins[] = {
1620 /* CLK C */
1621 RCAR_GP_PIN(5, 0),
1622};
1623static const unsigned int audio_clk_c_b_mux[] = {
1624 AUDIO_CLKC_B_MARK,
1625};
1626static const unsigned int audio_clkout_a_pins[] = {
1627 /* CLKOUT */
1628 RCAR_GP_PIN(5, 18),
1629};
1630static const unsigned int audio_clkout_a_mux[] = {
1631 AUDIO_CLKOUT_A_MARK,
1632};
1633static const unsigned int audio_clkout_b_pins[] = {
1634 /* CLKOUT */
1635 RCAR_GP_PIN(6, 28),
1636};
1637static const unsigned int audio_clkout_b_mux[] = {
1638 AUDIO_CLKOUT_B_MARK,
1639};
1640static const unsigned int audio_clkout_c_pins[] = {
1641 /* CLKOUT */
1642 RCAR_GP_PIN(5, 3),
1643};
1644static const unsigned int audio_clkout_c_mux[] = {
1645 AUDIO_CLKOUT_C_MARK,
1646};
1647static const unsigned int audio_clkout_d_pins[] = {
1648 /* CLKOUT */
1649 RCAR_GP_PIN(5, 21),
1650};
1651static const unsigned int audio_clkout_d_mux[] = {
1652 AUDIO_CLKOUT_D_MARK,
1653};
1654static const unsigned int audio_clkout1_a_pins[] = {
1655 /* CLKOUT1 */
1656 RCAR_GP_PIN(5, 15),
1657};
1658static const unsigned int audio_clkout1_a_mux[] = {
1659 AUDIO_CLKOUT1_A_MARK,
1660};
1661static const unsigned int audio_clkout1_b_pins[] = {
1662 /* CLKOUT1 */
1663 RCAR_GP_PIN(6, 29),
1664};
1665static const unsigned int audio_clkout1_b_mux[] = {
1666 AUDIO_CLKOUT1_B_MARK,
1667};
1668static const unsigned int audio_clkout2_a_pins[] = {
1669 /* CLKOUT2 */
1670 RCAR_GP_PIN(5, 16),
1671};
1672static const unsigned int audio_clkout2_a_mux[] = {
1673 AUDIO_CLKOUT2_A_MARK,
1674};
1675static const unsigned int audio_clkout2_b_pins[] = {
1676 /* CLKOUT2 */
1677 RCAR_GP_PIN(6, 30),
1678};
1679static const unsigned int audio_clkout2_b_mux[] = {
1680 AUDIO_CLKOUT2_B_MARK,
1681};
1682
1683static const unsigned int audio_clkout3_a_pins[] = {
1684 /* CLKOUT3 */
1685 RCAR_GP_PIN(5, 19),
1686};
1687static const unsigned int audio_clkout3_a_mux[] = {
1688 AUDIO_CLKOUT3_A_MARK,
1689};
1690static const unsigned int audio_clkout3_b_pins[] = {
1691 /* CLKOUT3 */
1692 RCAR_GP_PIN(6, 31),
1693};
1694static const unsigned int audio_clkout3_b_mux[] = {
1695 AUDIO_CLKOUT3_B_MARK,
1696};
1697
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1698/* - EtherAVB --------------------------------------------------------------- */
1699static const unsigned int avb_link_pins[] = {
1700 /* AVB_LINK */
1701 RCAR_GP_PIN(2, 12),
1702};
1703static const unsigned int avb_link_mux[] = {
1704 AVB_LINK_MARK,
1705};
1706static const unsigned int avb_magic_pins[] = {
1707 /* AVB_MAGIC_ */
1708 RCAR_GP_PIN(2, 10),
1709};
1710static const unsigned int avb_magic_mux[] = {
1711 AVB_MAGIC_MARK,
1712};
1713static const unsigned int avb_phy_int_pins[] = {
1714 /* AVB_PHY_INT */
1715 RCAR_GP_PIN(2, 11),
1716};
1717static const unsigned int avb_phy_int_mux[] = {
1718 AVB_PHY_INT_MARK,
1719};
1720static const unsigned int avb_mdc_pins[] = {
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]1721 /* AVB_MDC, AVB_MDIO */
1722 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1723};
1724static const unsigned int avb_mdc_mux[] = {
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]1725 AVB_MDC_MARK, AVB_MDIO_MARK,
1726};
1727static const unsigned int avb_mii_pins[] = {
1728 /*
1729 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1730 * AVB_TD1, AVB_TD2, AVB_TD3,
1731 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1732 * AVB_RD1, AVB_RD2, AVB_RD3,
1733 * AVB_TXCREFCLK
1734 */
1735 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1736 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1737 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1738 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1739 PIN_NUMBER('A', 12),
1740
1741};
1742static const unsigned int avb_mii_mux[] = {
1743 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1744 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1745 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1746 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1747 AVB_TXCREFCLK_MARK,
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]1748};
1749static const unsigned int avb_avtp_pps_pins[] = {
1750 /* AVB_AVTP_PPS */
1751 RCAR_GP_PIN(2, 6),
1752};
1753static const unsigned int avb_avtp_pps_mux[] = {
1754 AVB_AVTP_PPS_MARK,
1755};
1756static const unsigned int avb_avtp_match_a_pins[] = {
1757 /* AVB_AVTP_MATCH_A */
1758 RCAR_GP_PIN(2, 13),
1759};
1760static const unsigned int avb_avtp_match_a_mux[] = {
1761 AVB_AVTP_MATCH_A_MARK,
1762};
1763static const unsigned int avb_avtp_capture_a_pins[] = {
1764 /* AVB_AVTP_CAPTURE_A */
1765 RCAR_GP_PIN(2, 14),
1766};
1767static const unsigned int avb_avtp_capture_a_mux[] = {
1768 AVB_AVTP_CAPTURE_A_MARK,
1769};
1770static const unsigned int avb_avtp_match_b_pins[] = {
1771 /* AVB_AVTP_MATCH_B */
1772 RCAR_GP_PIN(1, 8),
1773};
1774static const unsigned int avb_avtp_match_b_mux[] = {
1775 AVB_AVTP_MATCH_B_MARK,
1776};
1777static const unsigned int avb_avtp_capture_b_pins[] = {
1778 /* AVB_AVTP_CAPTURE_B */
1779 RCAR_GP_PIN(1, 11),
1780};
1781static const unsigned int avb_avtp_capture_b_mux[] = {
1782 AVB_AVTP_CAPTURE_B_MARK,
1783};
1784
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]1785/* - CAN ------------------------------------------------------------------ */
1786static const unsigned int can0_data_a_pins[] = {
1787 /* TX, RX */
1788 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1789};
1790static const unsigned int can0_data_a_mux[] = {
1791 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1792};
1793static const unsigned int can0_data_b_pins[] = {
1794 /* TX, RX */
1795 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1796};
1797static const unsigned int can0_data_b_mux[] = {
1798 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1799};
1800static const unsigned int can1_data_pins[] = {
1801 /* TX, RX */
1802 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1803};
1804static const unsigned int can1_data_mux[] = {
1805 CAN1_TX_MARK, CAN1_RX_MARK,
1806};
1807
1808/* - CAN Clock -------------------------------------------------------------- */
1809static const unsigned int can_clk_pins[] = {
1810 /* CLK */
1811 RCAR_GP_PIN(1, 25),
1812};
1813static const unsigned int can_clk_mux[] = {
1814 CAN_CLK_MARK,
1815};
1816
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]1817/* - CAN FD --------------------------------------------------------------- */
1818static const unsigned int canfd0_data_a_pins[] = {
1819 /* TX, RX */
1820 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1821};
1822static const unsigned int canfd0_data_a_mux[] = {
1823 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1824};
1825static const unsigned int canfd0_data_b_pins[] = {
1826 /* TX, RX */
1827 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1828};
1829static const unsigned int canfd0_data_b_mux[] = {
1830 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1831};
1832static const unsigned int canfd1_data_pins[] = {
1833 /* TX, RX */
1834 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1835};
1836static const unsigned int canfd1_data_mux[] = {
1837 CANFD1_TX_MARK, CANFD1_RX_MARK,
1838};
1839
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]1840/* - DRIF0 --------------------------------------------------------------- */
1841static const unsigned int drif0_ctrl_a_pins[] = {
1842 /* CLK, SYNC */
1843 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1844};
1845static const unsigned int drif0_ctrl_a_mux[] = {
1846 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1847};
1848static const unsigned int drif0_data0_a_pins[] = {
1849 /* D0 */
1850 RCAR_GP_PIN(6, 10),
1851};
1852static const unsigned int drif0_data0_a_mux[] = {
1853 RIF0_D0_A_MARK,
1854};
1855static const unsigned int drif0_data1_a_pins[] = {
1856 /* D1 */
1857 RCAR_GP_PIN(6, 7),
1858};
1859static const unsigned int drif0_data1_a_mux[] = {
1860 RIF0_D1_A_MARK,
1861};
1862static const unsigned int drif0_ctrl_b_pins[] = {
1863 /* CLK, SYNC */
1864 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1865};
1866static const unsigned int drif0_ctrl_b_mux[] = {
1867 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1868};
1869static const unsigned int drif0_data0_b_pins[] = {
1870 /* D0 */
1871 RCAR_GP_PIN(5, 1),
1872};
1873static const unsigned int drif0_data0_b_mux[] = {
1874 RIF0_D0_B_MARK,
1875};
1876static const unsigned int drif0_data1_b_pins[] = {
1877 /* D1 */
1878 RCAR_GP_PIN(5, 2),
1879};
1880static const unsigned int drif0_data1_b_mux[] = {
1881 RIF0_D1_B_MARK,
1882};
1883static const unsigned int drif0_ctrl_c_pins[] = {
1884 /* CLK, SYNC */
1885 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1886};
1887static const unsigned int drif0_ctrl_c_mux[] = {
1888 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1889};
1890static const unsigned int drif0_data0_c_pins[] = {
1891 /* D0 */
1892 RCAR_GP_PIN(5, 13),
1893};
1894static const unsigned int drif0_data0_c_mux[] = {
1895 RIF0_D0_C_MARK,
1896};
1897static const unsigned int drif0_data1_c_pins[] = {
1898 /* D1 */
1899 RCAR_GP_PIN(5, 14),
1900};
1901static const unsigned int drif0_data1_c_mux[] = {
1902 RIF0_D1_C_MARK,
1903};
1904/* - DRIF1 --------------------------------------------------------------- */
1905static const unsigned int drif1_ctrl_a_pins[] = {
1906 /* CLK, SYNC */
1907 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1908};
1909static const unsigned int drif1_ctrl_a_mux[] = {
1910 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1911};
1912static const unsigned int drif1_data0_a_pins[] = {
1913 /* D0 */
1914 RCAR_GP_PIN(6, 19),
1915};
1916static const unsigned int drif1_data0_a_mux[] = {
1917 RIF1_D0_A_MARK,
1918};
1919static const unsigned int drif1_data1_a_pins[] = {
1920 /* D1 */
1921 RCAR_GP_PIN(6, 20),
1922};
1923static const unsigned int drif1_data1_a_mux[] = {
1924 RIF1_D1_A_MARK,
1925};
1926static const unsigned int drif1_ctrl_b_pins[] = {
1927 /* CLK, SYNC */
1928 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1929};
1930static const unsigned int drif1_ctrl_b_mux[] = {
1931 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1932};
1933static const unsigned int drif1_data0_b_pins[] = {
1934 /* D0 */
1935 RCAR_GP_PIN(5, 7),
1936};
1937static const unsigned int drif1_data0_b_mux[] = {
1938 RIF1_D0_B_MARK,
1939};
1940static const unsigned int drif1_data1_b_pins[] = {
1941 /* D1 */
1942 RCAR_GP_PIN(5, 8),
1943};
1944static const unsigned int drif1_data1_b_mux[] = {
1945 RIF1_D1_B_MARK,
1946};
1947static const unsigned int drif1_ctrl_c_pins[] = {
1948 /* CLK, SYNC */
1949 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1950};
1951static const unsigned int drif1_ctrl_c_mux[] = {
1952 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1953};
1954static const unsigned int drif1_data0_c_pins[] = {
1955 /* D0 */
1956 RCAR_GP_PIN(5, 6),
1957};
1958static const unsigned int drif1_data0_c_mux[] = {
1959 RIF1_D0_C_MARK,
1960};
1961static const unsigned int drif1_data1_c_pins[] = {
1962 /* D1 */
1963 RCAR_GP_PIN(5, 10),
1964};
1965static const unsigned int drif1_data1_c_mux[] = {
1966 RIF1_D1_C_MARK,
1967};
1968/* - DRIF2 --------------------------------------------------------------- */
1969static const unsigned int drif2_ctrl_a_pins[] = {
1970 /* CLK, SYNC */
1971 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1972};
1973static const unsigned int drif2_ctrl_a_mux[] = {
1974 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1975};
1976static const unsigned int drif2_data0_a_pins[] = {
1977 /* D0 */
1978 RCAR_GP_PIN(6, 7),
1979};
1980static const unsigned int drif2_data0_a_mux[] = {
1981 RIF2_D0_A_MARK,
1982};
1983static const unsigned int drif2_data1_a_pins[] = {
1984 /* D1 */
1985 RCAR_GP_PIN(6, 10),
1986};
1987static const unsigned int drif2_data1_a_mux[] = {
1988 RIF2_D1_A_MARK,
1989};
1990static const unsigned int drif2_ctrl_b_pins[] = {
1991 /* CLK, SYNC */
1992 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1993};
1994static const unsigned int drif2_ctrl_b_mux[] = {
1995 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1996};
1997static const unsigned int drif2_data0_b_pins[] = {
1998 /* D0 */
1999 RCAR_GP_PIN(6, 30),
2000};
2001static const unsigned int drif2_data0_b_mux[] = {
2002 RIF2_D0_B_MARK,
2003};
2004static const unsigned int drif2_data1_b_pins[] = {
2005 /* D1 */
2006 RCAR_GP_PIN(6, 31),
2007};
2008static const unsigned int drif2_data1_b_mux[] = {
2009 RIF2_D1_B_MARK,
2010};
2011/* - DRIF3 --------------------------------------------------------------- */
2012static const unsigned int drif3_ctrl_a_pins[] = {
2013 /* CLK, SYNC */
2014 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2015};
2016static const unsigned int drif3_ctrl_a_mux[] = {
2017 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2018};
2019static const unsigned int drif3_data0_a_pins[] = {
2020 /* D0 */
2021 RCAR_GP_PIN(6, 19),
2022};
2023static const unsigned int drif3_data0_a_mux[] = {
2024 RIF3_D0_A_MARK,
2025};
2026static const unsigned int drif3_data1_a_pins[] = {
2027 /* D1 */
2028 RCAR_GP_PIN(6, 20),
2029};
2030static const unsigned int drif3_data1_a_mux[] = {
2031 RIF3_D1_A_MARK,
2032};
2033static const unsigned int drif3_ctrl_b_pins[] = {
2034 /* CLK, SYNC */
2035 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2036};
2037static const unsigned int drif3_ctrl_b_mux[] = {
2038 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2039};
2040static const unsigned int drif3_data0_b_pins[] = {
2041 /* D0 */
2042 RCAR_GP_PIN(6, 28),
2043};
2044static const unsigned int drif3_data0_b_mux[] = {
2045 RIF3_D0_B_MARK,
2046};
2047static const unsigned int drif3_data1_b_pins[] = {
2048 /* D1 */
2049 RCAR_GP_PIN(6, 29),
2050};
2051static const unsigned int drif3_data1_b_mux[] = {
2052 RIF3_D1_B_MARK,
2053};
2054
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]2055/* - DU --------------------------------------------------------------------- */
2056static const unsigned int du_rgb666_pins[] = {
2057 /* R[7:2], G[7:2], B[7:2] */
2058 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2059 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2060 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2061 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2062 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2063 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2064};
2065static const unsigned int du_rgb666_mux[] = {
2066 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2067 DU_DR3_MARK, DU_DR2_MARK,
2068 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2069 DU_DG3_MARK, DU_DG2_MARK,
2070 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2071 DU_DB3_MARK, DU_DB2_MARK,
2072};
2073static const unsigned int du_rgb888_pins[] = {
2074 /* R[7:0], G[7:0], B[7:0] */
2075 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2076 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2077 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2078 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2079 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2080 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2081 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2082 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2083 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2084};
2085static const unsigned int du_rgb888_mux[] = {
2086 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2087 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2088 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2089 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2090 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2091 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2092};
2093static const unsigned int du_clk_out_0_pins[] = {
2094 /* CLKOUT */
2095 RCAR_GP_PIN(1, 27),
2096};
2097static const unsigned int du_clk_out_0_mux[] = {
2098 DU_DOTCLKOUT0_MARK
2099};
2100static const unsigned int du_clk_out_1_pins[] = {
2101 /* CLKOUT */
2102 RCAR_GP_PIN(2, 3),
2103};
2104static const unsigned int du_clk_out_1_mux[] = {
2105 DU_DOTCLKOUT1_MARK
2106};
2107static const unsigned int du_sync_pins[] = {
2108 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2109 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2110};
2111static const unsigned int du_sync_mux[] = {
2112 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2113};
2114static const unsigned int du_oddf_pins[] = {
2115 /* EXDISP/EXODDF/EXCDE */
2116 RCAR_GP_PIN(2, 2),
2117};
2118static const unsigned int du_oddf_mux[] = {
2119 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2120};
2121static const unsigned int du_cde_pins[] = {
2122 /* CDE */
2123 RCAR_GP_PIN(2, 0),
2124};
2125static const unsigned int du_cde_mux[] = {
2126 DU_CDE_MARK,
2127};
2128static const unsigned int du_disp_pins[] = {
2129 /* DISP */
2130 RCAR_GP_PIN(2, 1),
2131};
2132static const unsigned int du_disp_mux[] = {
2133 DU_DISP_MARK,
2134};
2135
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame^]2136/* - HDMI ------------------------------------------------------------------- */
2137static const unsigned int hdmi0_cec_pins[] = {
2138 /* HDMI0_CEC */
2139 RCAR_GP_PIN(7, 2),
2140};
2141static const unsigned int hdmi0_cec_mux[] = {
2142 HDMI0_CEC_MARK,
2143};
2144
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]2145/* - HSCIF0 ----------------------------------------------------------------- */
2146static const unsigned int hscif0_data_pins[] = {
2147 /* RX, TX */
2148 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2149};
2150static const unsigned int hscif0_data_mux[] = {
2151 HRX0_MARK, HTX0_MARK,
2152};
2153static const unsigned int hscif0_clk_pins[] = {
2154 /* SCK */
2155 RCAR_GP_PIN(5, 12),
2156};
2157static const unsigned int hscif0_clk_mux[] = {
2158 HSCK0_MARK,
2159};
2160static const unsigned int hscif0_ctrl_pins[] = {
2161 /* RTS, CTS */
2162 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2163};
2164static const unsigned int hscif0_ctrl_mux[] = {
2165 HRTS0_N_MARK, HCTS0_N_MARK,
2166};
2167/* - HSCIF1 ----------------------------------------------------------------- */
2168static const unsigned int hscif1_data_a_pins[] = {
2169 /* RX, TX */
2170 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2171};
2172static const unsigned int hscif1_data_a_mux[] = {
2173 HRX1_A_MARK, HTX1_A_MARK,
2174};
2175static const unsigned int hscif1_clk_a_pins[] = {
2176 /* SCK */
2177 RCAR_GP_PIN(6, 21),
2178};
2179static const unsigned int hscif1_clk_a_mux[] = {
2180 HSCK1_A_MARK,
2181};
2182static const unsigned int hscif1_ctrl_a_pins[] = {
2183 /* RTS, CTS */
2184 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2185};
2186static const unsigned int hscif1_ctrl_a_mux[] = {
2187 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2188};
2189
2190static const unsigned int hscif1_data_b_pins[] = {
2191 /* RX, TX */
2192 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2193};
2194static const unsigned int hscif1_data_b_mux[] = {
2195 HRX1_B_MARK, HTX1_B_MARK,
2196};
2197static const unsigned int hscif1_clk_b_pins[] = {
2198 /* SCK */
2199 RCAR_GP_PIN(5, 0),
2200};
2201static const unsigned int hscif1_clk_b_mux[] = {
2202 HSCK1_B_MARK,
2203};
2204static const unsigned int hscif1_ctrl_b_pins[] = {
2205 /* RTS, CTS */
2206 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2207};
2208static const unsigned int hscif1_ctrl_b_mux[] = {
2209 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2210};
2211/* - HSCIF2 ----------------------------------------------------------------- */
2212static const unsigned int hscif2_data_a_pins[] = {
2213 /* RX, TX */
2214 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2215};
2216static const unsigned int hscif2_data_a_mux[] = {
2217 HRX2_A_MARK, HTX2_A_MARK,
2218};
2219static const unsigned int hscif2_clk_a_pins[] = {
2220 /* SCK */
2221 RCAR_GP_PIN(6, 10),
2222};
2223static const unsigned int hscif2_clk_a_mux[] = {
2224 HSCK2_A_MARK,
2225};
2226static const unsigned int hscif2_ctrl_a_pins[] = {
2227 /* RTS, CTS */
2228 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2229};
2230static const unsigned int hscif2_ctrl_a_mux[] = {
2231 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2232};
2233
2234static const unsigned int hscif2_data_b_pins[] = {
2235 /* RX, TX */
2236 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2237};
2238static const unsigned int hscif2_data_b_mux[] = {
2239 HRX2_B_MARK, HTX2_B_MARK,
2240};
2241static const unsigned int hscif2_clk_b_pins[] = {
2242 /* SCK */
2243 RCAR_GP_PIN(6, 21),
2244};
2245static const unsigned int hscif2_clk_b_mux[] = {
2246 HSCK2_B_MARK,
2247};
2248static const unsigned int hscif2_ctrl_b_pins[] = {
2249 /* RTS, CTS */
2250 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2251};
2252static const unsigned int hscif2_ctrl_b_mux[] = {
2253 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2254};
2255
2256static const unsigned int hscif2_data_c_pins[] = {
2257 /* RX, TX */
2258 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2259};
2260static const unsigned int hscif2_data_c_mux[] = {
2261 HRX2_C_MARK, HTX2_C_MARK,
2262};
2263static const unsigned int hscif2_clk_c_pins[] = {
2264 /* SCK */
2265 RCAR_GP_PIN(6, 24),
2266};
2267static const unsigned int hscif2_clk_c_mux[] = {
2268 HSCK2_C_MARK,
2269};
2270static const unsigned int hscif2_ctrl_c_pins[] = {
2271 /* RTS, CTS */
2272 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2273};
2274static const unsigned int hscif2_ctrl_c_mux[] = {
2275 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2276};
2277/* - HSCIF3 ----------------------------------------------------------------- */
2278static const unsigned int hscif3_data_a_pins[] = {
2279 /* RX, TX */
2280 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2281};
2282static const unsigned int hscif3_data_a_mux[] = {
2283 HRX3_A_MARK, HTX3_A_MARK,
2284};
2285static const unsigned int hscif3_clk_pins[] = {
2286 /* SCK */
2287 RCAR_GP_PIN(1, 22),
2288};
2289static const unsigned int hscif3_clk_mux[] = {
2290 HSCK3_MARK,
2291};
2292static const unsigned int hscif3_ctrl_pins[] = {
2293 /* RTS, CTS */
2294 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2295};
2296static const unsigned int hscif3_ctrl_mux[] = {
2297 HRTS3_N_MARK, HCTS3_N_MARK,
2298};
2299
2300static const unsigned int hscif3_data_b_pins[] = {
2301 /* RX, TX */
2302 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2303};
2304static const unsigned int hscif3_data_b_mux[] = {
2305 HRX3_B_MARK, HTX3_B_MARK,
2306};
2307static const unsigned int hscif3_data_c_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2310};
2311static const unsigned int hscif3_data_c_mux[] = {
2312 HRX3_C_MARK, HTX3_C_MARK,
2313};
2314static const unsigned int hscif3_data_d_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2317};
2318static const unsigned int hscif3_data_d_mux[] = {
2319 HRX3_D_MARK, HTX3_D_MARK,
2320};
2321/* - HSCIF4 ----------------------------------------------------------------- */
2322static const unsigned int hscif4_data_a_pins[] = {
2323 /* RX, TX */
2324 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2325};
2326static const unsigned int hscif4_data_a_mux[] = {
2327 HRX4_A_MARK, HTX4_A_MARK,
2328};
2329static const unsigned int hscif4_clk_pins[] = {
2330 /* SCK */
2331 RCAR_GP_PIN(1, 11),
2332};
2333static const unsigned int hscif4_clk_mux[] = {
2334 HSCK4_MARK,
2335};
2336static const unsigned int hscif4_ctrl_pins[] = {
2337 /* RTS, CTS */
2338 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2339};
2340static const unsigned int hscif4_ctrl_mux[] = {
2341 HRTS4_N_MARK, HCTS4_N_MARK,
2342};
2343
2344static const unsigned int hscif4_data_b_pins[] = {
2345 /* RX, TX */
2346 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2347};
2348static const unsigned int hscif4_data_b_mux[] = {
2349 HRX4_B_MARK, HTX4_B_MARK,
2350};
2351
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]2352/* - I2C -------------------------------------------------------------------- */
2353static const unsigned int i2c1_a_pins[] = {
2354 /* SDA, SCL */
2355 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2356};
2357static const unsigned int i2c1_a_mux[] = {
2358 SDA1_A_MARK, SCL1_A_MARK,
2359};
2360static const unsigned int i2c1_b_pins[] = {
2361 /* SDA, SCL */
2362 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2363};
2364static const unsigned int i2c1_b_mux[] = {
2365 SDA1_B_MARK, SCL1_B_MARK,
2366};
2367static const unsigned int i2c2_a_pins[] = {
2368 /* SDA, SCL */
2369 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2370};
2371static const unsigned int i2c2_a_mux[] = {
2372 SDA2_A_MARK, SCL2_A_MARK,
2373};
2374static const unsigned int i2c2_b_pins[] = {
2375 /* SDA, SCL */
2376 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2377};
2378static const unsigned int i2c2_b_mux[] = {
2379 SDA2_B_MARK, SCL2_B_MARK,
2380};
2381static const unsigned int i2c6_a_pins[] = {
2382 /* SDA, SCL */
2383 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2384};
2385static const unsigned int i2c6_a_mux[] = {
2386 SDA6_A_MARK, SCL6_A_MARK,
2387};
2388static const unsigned int i2c6_b_pins[] = {
2389 /* SDA, SCL */
2390 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2391};
2392static const unsigned int i2c6_b_mux[] = {
2393 SDA6_B_MARK, SCL6_B_MARK,
2394};
2395static const unsigned int i2c6_c_pins[] = {
2396 /* SDA, SCL */
2397 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2398};
2399static const unsigned int i2c6_c_mux[] = {
2400 SDA6_C_MARK, SCL6_C_MARK,
2401};
2402
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]2403/* - INTC-EX ---------------------------------------------------------------- */
2404static const unsigned int intc_ex_irq0_pins[] = {
2405 /* IRQ0 */
2406 RCAR_GP_PIN(2, 0),
2407};
2408static const unsigned int intc_ex_irq0_mux[] = {
2409 IRQ0_MARK,
2410};
2411static const unsigned int intc_ex_irq1_pins[] = {
2412 /* IRQ1 */
2413 RCAR_GP_PIN(2, 1),
2414};
2415static const unsigned int intc_ex_irq1_mux[] = {
2416 IRQ1_MARK,
2417};
2418static const unsigned int intc_ex_irq2_pins[] = {
2419 /* IRQ2 */
2420 RCAR_GP_PIN(2, 2),
2421};
2422static const unsigned int intc_ex_irq2_mux[] = {
2423 IRQ2_MARK,
2424};
2425static const unsigned int intc_ex_irq3_pins[] = {
2426 /* IRQ3 */
2427 RCAR_GP_PIN(2, 3),
2428};
2429static const unsigned int intc_ex_irq3_mux[] = {
2430 IRQ3_MARK,
2431};
2432static const unsigned int intc_ex_irq4_pins[] = {
2433 /* IRQ4 */
2434 RCAR_GP_PIN(2, 4),
2435};
2436static const unsigned int intc_ex_irq4_mux[] = {
2437 IRQ4_MARK,
2438};
2439static const unsigned int intc_ex_irq5_pins[] = {
2440 /* IRQ5 */
2441 RCAR_GP_PIN(2, 5),
2442};
2443static const unsigned int intc_ex_irq5_mux[] = {
2444 IRQ5_MARK,
2445};
2446
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]2447/* - MSIOF0 ----------------------------------------------------------------- */
2448static const unsigned int msiof0_clk_pins[] = {
2449 /* SCK */
2450 RCAR_GP_PIN(5, 17),
2451};
2452static const unsigned int msiof0_clk_mux[] = {
2453 MSIOF0_SCK_MARK,
2454};
2455static const unsigned int msiof0_sync_pins[] = {
2456 /* SYNC */
2457 RCAR_GP_PIN(5, 18),
2458};
2459static const unsigned int msiof0_sync_mux[] = {
2460 MSIOF0_SYNC_MARK,
2461};
2462static const unsigned int msiof0_ss1_pins[] = {
2463 /* SS1 */
2464 RCAR_GP_PIN(5, 19),
2465};
2466static const unsigned int msiof0_ss1_mux[] = {
2467 MSIOF0_SS1_MARK,
2468};
2469static const unsigned int msiof0_ss2_pins[] = {
2470 /* SS2 */
2471 RCAR_GP_PIN(5, 21),
2472};
2473static const unsigned int msiof0_ss2_mux[] = {
2474 MSIOF0_SS2_MARK,
2475};
2476static const unsigned int msiof0_txd_pins[] = {
2477 /* TXD */
2478 RCAR_GP_PIN(5, 20),
2479};
2480static const unsigned int msiof0_txd_mux[] = {
2481 MSIOF0_TXD_MARK,
2482};
2483static const unsigned int msiof0_rxd_pins[] = {
2484 /* RXD */
2485 RCAR_GP_PIN(5, 22),
2486};
2487static const unsigned int msiof0_rxd_mux[] = {
2488 MSIOF0_RXD_MARK,
2489};
2490/* - MSIOF1 ----------------------------------------------------------------- */
2491static const unsigned int msiof1_clk_a_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(6, 8),
2494};
2495static const unsigned int msiof1_clk_a_mux[] = {
2496 MSIOF1_SCK_A_MARK,
2497};
2498static const unsigned int msiof1_sync_a_pins[] = {
2499 /* SYNC */
2500 RCAR_GP_PIN(6, 9),
2501};
2502static const unsigned int msiof1_sync_a_mux[] = {
2503 MSIOF1_SYNC_A_MARK,
2504};
2505static const unsigned int msiof1_ss1_a_pins[] = {
2506 /* SS1 */
2507 RCAR_GP_PIN(6, 5),
2508};
2509static const unsigned int msiof1_ss1_a_mux[] = {
2510 MSIOF1_SS1_A_MARK,
2511};
2512static const unsigned int msiof1_ss2_a_pins[] = {
2513 /* SS2 */
2514 RCAR_GP_PIN(6, 6),
2515};
2516static const unsigned int msiof1_ss2_a_mux[] = {
2517 MSIOF1_SS2_A_MARK,
2518};
2519static const unsigned int msiof1_txd_a_pins[] = {
2520 /* TXD */
2521 RCAR_GP_PIN(6, 7),
2522};
2523static const unsigned int msiof1_txd_a_mux[] = {
2524 MSIOF1_TXD_A_MARK,
2525};
2526static const unsigned int msiof1_rxd_a_pins[] = {
2527 /* RXD */
2528 RCAR_GP_PIN(6, 10),
2529};
2530static const unsigned int msiof1_rxd_a_mux[] = {
2531 MSIOF1_RXD_A_MARK,
2532};
2533static const unsigned int msiof1_clk_b_pins[] = {
2534 /* SCK */
2535 RCAR_GP_PIN(5, 9),
2536};
2537static const unsigned int msiof1_clk_b_mux[] = {
2538 MSIOF1_SCK_B_MARK,
2539};
2540static const unsigned int msiof1_sync_b_pins[] = {
2541 /* SYNC */
2542 RCAR_GP_PIN(5, 3),
2543};
2544static const unsigned int msiof1_sync_b_mux[] = {
2545 MSIOF1_SYNC_B_MARK,
2546};
2547static const unsigned int msiof1_ss1_b_pins[] = {
2548 /* SS1 */
2549 RCAR_GP_PIN(5, 4),
2550};
2551static const unsigned int msiof1_ss1_b_mux[] = {
2552 MSIOF1_SS1_B_MARK,
2553};
2554static const unsigned int msiof1_ss2_b_pins[] = {
2555 /* SS2 */
2556 RCAR_GP_PIN(5, 0),
2557};
2558static const unsigned int msiof1_ss2_b_mux[] = {
2559 MSIOF1_SS2_B_MARK,
2560};
2561static const unsigned int msiof1_txd_b_pins[] = {
2562 /* TXD */
2563 RCAR_GP_PIN(5, 8),
2564};
2565static const unsigned int msiof1_txd_b_mux[] = {
2566 MSIOF1_TXD_B_MARK,
2567};
2568static const unsigned int msiof1_rxd_b_pins[] = {
2569 /* RXD */
2570 RCAR_GP_PIN(5, 7),
2571};
2572static const unsigned int msiof1_rxd_b_mux[] = {
2573 MSIOF1_RXD_B_MARK,
2574};
2575static const unsigned int msiof1_clk_c_pins[] = {
2576 /* SCK */
2577 RCAR_GP_PIN(6, 17),
2578};
2579static const unsigned int msiof1_clk_c_mux[] = {
2580 MSIOF1_SCK_C_MARK,
2581};
2582static const unsigned int msiof1_sync_c_pins[] = {
2583 /* SYNC */
2584 RCAR_GP_PIN(6, 18),
2585};
2586static const unsigned int msiof1_sync_c_mux[] = {
2587 MSIOF1_SYNC_C_MARK,
2588};
2589static const unsigned int msiof1_ss1_c_pins[] = {
2590 /* SS1 */
2591 RCAR_GP_PIN(6, 21),
2592};
2593static const unsigned int msiof1_ss1_c_mux[] = {
2594 MSIOF1_SS1_C_MARK,
2595};
2596static const unsigned int msiof1_ss2_c_pins[] = {
2597 /* SS2 */
2598 RCAR_GP_PIN(6, 27),
2599};
2600static const unsigned int msiof1_ss2_c_mux[] = {
2601 MSIOF1_SS2_C_MARK,
2602};
2603static const unsigned int msiof1_txd_c_pins[] = {
2604 /* TXD */
2605 RCAR_GP_PIN(6, 20),
2606};
2607static const unsigned int msiof1_txd_c_mux[] = {
2608 MSIOF1_TXD_C_MARK,
2609};
2610static const unsigned int msiof1_rxd_c_pins[] = {
2611 /* RXD */
2612 RCAR_GP_PIN(6, 19),
2613};
2614static const unsigned int msiof1_rxd_c_mux[] = {
2615 MSIOF1_RXD_C_MARK,
2616};
2617static const unsigned int msiof1_clk_d_pins[] = {
2618 /* SCK */
2619 RCAR_GP_PIN(5, 12),
2620};
2621static const unsigned int msiof1_clk_d_mux[] = {
2622 MSIOF1_SCK_D_MARK,
2623};
2624static const unsigned int msiof1_sync_d_pins[] = {
2625 /* SYNC */
2626 RCAR_GP_PIN(5, 15),
2627};
2628static const unsigned int msiof1_sync_d_mux[] = {
2629 MSIOF1_SYNC_D_MARK,
2630};
2631static const unsigned int msiof1_ss1_d_pins[] = {
2632 /* SS1 */
2633 RCAR_GP_PIN(5, 16),
2634};
2635static const unsigned int msiof1_ss1_d_mux[] = {
2636 MSIOF1_SS1_D_MARK,
2637};
2638static const unsigned int msiof1_ss2_d_pins[] = {
2639 /* SS2 */
2640 RCAR_GP_PIN(5, 21),
2641};
2642static const unsigned int msiof1_ss2_d_mux[] = {
2643 MSIOF1_SS2_D_MARK,
2644};
2645static const unsigned int msiof1_txd_d_pins[] = {
2646 /* TXD */
2647 RCAR_GP_PIN(5, 14),
2648};
2649static const unsigned int msiof1_txd_d_mux[] = {
2650 MSIOF1_TXD_D_MARK,
2651};
2652static const unsigned int msiof1_rxd_d_pins[] = {
2653 /* RXD */
2654 RCAR_GP_PIN(5, 13),
2655};
2656static const unsigned int msiof1_rxd_d_mux[] = {
2657 MSIOF1_RXD_D_MARK,
2658};
2659static const unsigned int msiof1_clk_e_pins[] = {
2660 /* SCK */
2661 RCAR_GP_PIN(3, 0),
2662};
2663static const unsigned int msiof1_clk_e_mux[] = {
2664 MSIOF1_SCK_E_MARK,
2665};
2666static const unsigned int msiof1_sync_e_pins[] = {
2667 /* SYNC */
2668 RCAR_GP_PIN(3, 1),
2669};
2670static const unsigned int msiof1_sync_e_mux[] = {
2671 MSIOF1_SYNC_E_MARK,
2672};
2673static const unsigned int msiof1_ss1_e_pins[] = {
2674 /* SS1 */
2675 RCAR_GP_PIN(3, 4),
2676};
2677static const unsigned int msiof1_ss1_e_mux[] = {
2678 MSIOF1_SS1_E_MARK,
2679};
2680static const unsigned int msiof1_ss2_e_pins[] = {
2681 /* SS2 */
2682 RCAR_GP_PIN(3, 5),
2683};
2684static const unsigned int msiof1_ss2_e_mux[] = {
2685 MSIOF1_SS2_E_MARK,
2686};
2687static const unsigned int msiof1_txd_e_pins[] = {
2688 /* TXD */
2689 RCAR_GP_PIN(3, 3),
2690};
2691static const unsigned int msiof1_txd_e_mux[] = {
2692 MSIOF1_TXD_E_MARK,
2693};
2694static const unsigned int msiof1_rxd_e_pins[] = {
2695 /* RXD */
2696 RCAR_GP_PIN(3, 2),
2697};
2698static const unsigned int msiof1_rxd_e_mux[] = {
2699 MSIOF1_RXD_E_MARK,
2700};
2701static const unsigned int msiof1_clk_f_pins[] = {
2702 /* SCK */
2703 RCAR_GP_PIN(5, 23),
2704};
2705static const unsigned int msiof1_clk_f_mux[] = {
2706 MSIOF1_SCK_F_MARK,
2707};
2708static const unsigned int msiof1_sync_f_pins[] = {
2709 /* SYNC */
2710 RCAR_GP_PIN(5, 24),
2711};
2712static const unsigned int msiof1_sync_f_mux[] = {
2713 MSIOF1_SYNC_F_MARK,
2714};
2715static const unsigned int msiof1_ss1_f_pins[] = {
2716 /* SS1 */
2717 RCAR_GP_PIN(6, 1),
2718};
2719static const unsigned int msiof1_ss1_f_mux[] = {
2720 MSIOF1_SS1_F_MARK,
2721};
2722static const unsigned int msiof1_ss2_f_pins[] = {
2723 /* SS2 */
2724 RCAR_GP_PIN(6, 2),
2725};
2726static const unsigned int msiof1_ss2_f_mux[] = {
2727 MSIOF1_SS2_F_MARK,
2728};
2729static const unsigned int msiof1_txd_f_pins[] = {
2730 /* TXD */
2731 RCAR_GP_PIN(6, 0),
2732};
2733static const unsigned int msiof1_txd_f_mux[] = {
2734 MSIOF1_TXD_F_MARK,
2735};
2736static const unsigned int msiof1_rxd_f_pins[] = {
2737 /* RXD */
2738 RCAR_GP_PIN(5, 25),
2739};
2740static const unsigned int msiof1_rxd_f_mux[] = {
2741 MSIOF1_RXD_F_MARK,
2742};
2743static const unsigned int msiof1_clk_g_pins[] = {
2744 /* SCK */
2745 RCAR_GP_PIN(3, 6),
2746};
2747static const unsigned int msiof1_clk_g_mux[] = {
2748 MSIOF1_SCK_G_MARK,
2749};
2750static const unsigned int msiof1_sync_g_pins[] = {
2751 /* SYNC */
2752 RCAR_GP_PIN(3, 7),
2753};
2754static const unsigned int msiof1_sync_g_mux[] = {
2755 MSIOF1_SYNC_G_MARK,
2756};
2757static const unsigned int msiof1_ss1_g_pins[] = {
2758 /* SS1 */
2759 RCAR_GP_PIN(3, 10),
2760};
2761static const unsigned int msiof1_ss1_g_mux[] = {
2762 MSIOF1_SS1_G_MARK,
2763};
2764static const unsigned int msiof1_ss2_g_pins[] = {
2765 /* SS2 */
2766 RCAR_GP_PIN(3, 11),
2767};
2768static const unsigned int msiof1_ss2_g_mux[] = {
2769 MSIOF1_SS2_G_MARK,
2770};
2771static const unsigned int msiof1_txd_g_pins[] = {
2772 /* TXD */
2773 RCAR_GP_PIN(3, 9),
2774};
2775static const unsigned int msiof1_txd_g_mux[] = {
2776 MSIOF1_TXD_G_MARK,
2777};
2778static const unsigned int msiof1_rxd_g_pins[] = {
2779 /* RXD */
2780 RCAR_GP_PIN(3, 8),
2781};
2782static const unsigned int msiof1_rxd_g_mux[] = {
2783 MSIOF1_RXD_G_MARK,
2784};
2785/* - MSIOF2 ----------------------------------------------------------------- */
2786static const unsigned int msiof2_clk_a_pins[] = {
2787 /* SCK */
2788 RCAR_GP_PIN(1, 9),
2789};
2790static const unsigned int msiof2_clk_a_mux[] = {
2791 MSIOF2_SCK_A_MARK,
2792};
2793static const unsigned int msiof2_sync_a_pins[] = {
2794 /* SYNC */
2795 RCAR_GP_PIN(1, 8),
2796};
2797static const unsigned int msiof2_sync_a_mux[] = {
2798 MSIOF2_SYNC_A_MARK,
2799};
2800static const unsigned int msiof2_ss1_a_pins[] = {
2801 /* SS1 */
2802 RCAR_GP_PIN(1, 6),
2803};
2804static const unsigned int msiof2_ss1_a_mux[] = {
2805 MSIOF2_SS1_A_MARK,
2806};
2807static const unsigned int msiof2_ss2_a_pins[] = {
2808 /* SS2 */
2809 RCAR_GP_PIN(1, 7),
2810};
2811static const unsigned int msiof2_ss2_a_mux[] = {
2812 MSIOF2_SS2_A_MARK,
2813};
2814static const unsigned int msiof2_txd_a_pins[] = {
2815 /* TXD */
2816 RCAR_GP_PIN(1, 11),
2817};
2818static const unsigned int msiof2_txd_a_mux[] = {
2819 MSIOF2_TXD_A_MARK,
2820};
2821static const unsigned int msiof2_rxd_a_pins[] = {
2822 /* RXD */
2823 RCAR_GP_PIN(1, 10),
2824};
2825static const unsigned int msiof2_rxd_a_mux[] = {
2826 MSIOF2_RXD_A_MARK,
2827};
2828static const unsigned int msiof2_clk_b_pins[] = {
2829 /* SCK */
2830 RCAR_GP_PIN(0, 4),
2831};
2832static const unsigned int msiof2_clk_b_mux[] = {
2833 MSIOF2_SCK_B_MARK,
2834};
2835static const unsigned int msiof2_sync_b_pins[] = {
2836 /* SYNC */
2837 RCAR_GP_PIN(0, 5),
2838};
2839static const unsigned int msiof2_sync_b_mux[] = {
2840 MSIOF2_SYNC_B_MARK,
2841};
2842static const unsigned int msiof2_ss1_b_pins[] = {
2843 /* SS1 */
2844 RCAR_GP_PIN(0, 0),
2845};
2846static const unsigned int msiof2_ss1_b_mux[] = {
2847 MSIOF2_SS1_B_MARK,
2848};
2849static const unsigned int msiof2_ss2_b_pins[] = {
2850 /* SS2 */
2851 RCAR_GP_PIN(0, 1),
2852};
2853static const unsigned int msiof2_ss2_b_mux[] = {
2854 MSIOF2_SS2_B_MARK,
2855};
2856static const unsigned int msiof2_txd_b_pins[] = {
2857 /* TXD */
2858 RCAR_GP_PIN(0, 7),
2859};
2860static const unsigned int msiof2_txd_b_mux[] = {
2861 MSIOF2_TXD_B_MARK,
2862};
2863static const unsigned int msiof2_rxd_b_pins[] = {
2864 /* RXD */
2865 RCAR_GP_PIN(0, 6),
2866};
2867static const unsigned int msiof2_rxd_b_mux[] = {
2868 MSIOF2_RXD_B_MARK,
2869};
2870static const unsigned int msiof2_clk_c_pins[] = {
2871 /* SCK */
2872 RCAR_GP_PIN(2, 12),
2873};
2874static const unsigned int msiof2_clk_c_mux[] = {
2875 MSIOF2_SCK_C_MARK,
2876};
2877static const unsigned int msiof2_sync_c_pins[] = {
2878 /* SYNC */
2879 RCAR_GP_PIN(2, 11),
2880};
2881static const unsigned int msiof2_sync_c_mux[] = {
2882 MSIOF2_SYNC_C_MARK,
2883};
2884static const unsigned int msiof2_ss1_c_pins[] = {
2885 /* SS1 */
2886 RCAR_GP_PIN(2, 10),
2887};
2888static const unsigned int msiof2_ss1_c_mux[] = {
2889 MSIOF2_SS1_C_MARK,
2890};
2891static const unsigned int msiof2_ss2_c_pins[] = {
2892 /* SS2 */
2893 RCAR_GP_PIN(2, 9),
2894};
2895static const unsigned int msiof2_ss2_c_mux[] = {
2896 MSIOF2_SS2_C_MARK,
2897};
2898static const unsigned int msiof2_txd_c_pins[] = {
2899 /* TXD */
2900 RCAR_GP_PIN(2, 14),
2901};
2902static const unsigned int msiof2_txd_c_mux[] = {
2903 MSIOF2_TXD_C_MARK,
2904};
2905static const unsigned int msiof2_rxd_c_pins[] = {
2906 /* RXD */
2907 RCAR_GP_PIN(2, 13),
2908};
2909static const unsigned int msiof2_rxd_c_mux[] = {
2910 MSIOF2_RXD_C_MARK,
2911};
2912static const unsigned int msiof2_clk_d_pins[] = {
2913 /* SCK */
2914 RCAR_GP_PIN(0, 8),
2915};
2916static const unsigned int msiof2_clk_d_mux[] = {
2917 MSIOF2_SCK_D_MARK,
2918};
2919static const unsigned int msiof2_sync_d_pins[] = {
2920 /* SYNC */
2921 RCAR_GP_PIN(0, 9),
2922};
2923static const unsigned int msiof2_sync_d_mux[] = {
2924 MSIOF2_SYNC_D_MARK,
2925};
2926static const unsigned int msiof2_ss1_d_pins[] = {
2927 /* SS1 */
2928 RCAR_GP_PIN(0, 12),
2929};
2930static const unsigned int msiof2_ss1_d_mux[] = {
2931 MSIOF2_SS1_D_MARK,
2932};
2933static const unsigned int msiof2_ss2_d_pins[] = {
2934 /* SS2 */
2935 RCAR_GP_PIN(0, 13),
2936};
2937static const unsigned int msiof2_ss2_d_mux[] = {
2938 MSIOF2_SS2_D_MARK,
2939};
2940static const unsigned int msiof2_txd_d_pins[] = {
2941 /* TXD */
2942 RCAR_GP_PIN(0, 11),
2943};
2944static const unsigned int msiof2_txd_d_mux[] = {
2945 MSIOF2_TXD_D_MARK,
2946};
2947static const unsigned int msiof2_rxd_d_pins[] = {
2948 /* RXD */
2949 RCAR_GP_PIN(0, 10),
2950};
2951static const unsigned int msiof2_rxd_d_mux[] = {
2952 MSIOF2_RXD_D_MARK,
2953};
2954/* - MSIOF3 ----------------------------------------------------------------- */
2955static const unsigned int msiof3_clk_a_pins[] = {
2956 /* SCK */
2957 RCAR_GP_PIN(0, 0),
2958};
2959static const unsigned int msiof3_clk_a_mux[] = {
2960 MSIOF3_SCK_A_MARK,
2961};
2962static const unsigned int msiof3_sync_a_pins[] = {
2963 /* SYNC */
2964 RCAR_GP_PIN(0, 1),
2965};
2966static const unsigned int msiof3_sync_a_mux[] = {
2967 MSIOF3_SYNC_A_MARK,
2968};
2969static const unsigned int msiof3_ss1_a_pins[] = {
2970 /* SS1 */
2971 RCAR_GP_PIN(0, 14),
2972};
2973static const unsigned int msiof3_ss1_a_mux[] = {
2974 MSIOF3_SS1_A_MARK,
2975};
2976static const unsigned int msiof3_ss2_a_pins[] = {
2977 /* SS2 */
2978 RCAR_GP_PIN(0, 15),
2979};
2980static const unsigned int msiof3_ss2_a_mux[] = {
2981 MSIOF3_SS2_A_MARK,
2982};
2983static const unsigned int msiof3_txd_a_pins[] = {
2984 /* TXD */
2985 RCAR_GP_PIN(0, 3),
2986};
2987static const unsigned int msiof3_txd_a_mux[] = {
2988 MSIOF3_TXD_A_MARK,
2989};
2990static const unsigned int msiof3_rxd_a_pins[] = {
2991 /* RXD */
2992 RCAR_GP_PIN(0, 2),
2993};
2994static const unsigned int msiof3_rxd_a_mux[] = {
2995 MSIOF3_RXD_A_MARK,
2996};
2997static const unsigned int msiof3_clk_b_pins[] = {
2998 /* SCK */
2999 RCAR_GP_PIN(1, 2),
3000};
3001static const unsigned int msiof3_clk_b_mux[] = {
3002 MSIOF3_SCK_B_MARK,
3003};
3004static const unsigned int msiof3_sync_b_pins[] = {
3005 /* SYNC */
3006 RCAR_GP_PIN(1, 0),
3007};
3008static const unsigned int msiof3_sync_b_mux[] = {
3009 MSIOF3_SYNC_B_MARK,
3010};
3011static const unsigned int msiof3_ss1_b_pins[] = {
3012 /* SS1 */
3013 RCAR_GP_PIN(1, 4),
3014};
3015static const unsigned int msiof3_ss1_b_mux[] = {
3016 MSIOF3_SS1_B_MARK,
3017};
3018static const unsigned int msiof3_ss2_b_pins[] = {
3019 /* SS2 */
3020 RCAR_GP_PIN(1, 5),
3021};
3022static const unsigned int msiof3_ss2_b_mux[] = {
3023 MSIOF3_SS2_B_MARK,
3024};
3025static const unsigned int msiof3_txd_b_pins[] = {
3026 /* TXD */
3027 RCAR_GP_PIN(1, 1),
3028};
3029static const unsigned int msiof3_txd_b_mux[] = {
3030 MSIOF3_TXD_B_MARK,
3031};
3032static const unsigned int msiof3_rxd_b_pins[] = {
3033 /* RXD */
3034 RCAR_GP_PIN(1, 3),
3035};
3036static const unsigned int msiof3_rxd_b_mux[] = {
3037 MSIOF3_RXD_B_MARK,
3038};
3039static const unsigned int msiof3_clk_c_pins[] = {
3040 /* SCK */
3041 RCAR_GP_PIN(1, 12),
3042};
3043static const unsigned int msiof3_clk_c_mux[] = {
3044 MSIOF3_SCK_C_MARK,
3045};
3046static const unsigned int msiof3_sync_c_pins[] = {
3047 /* SYNC */
3048 RCAR_GP_PIN(1, 13),
3049};
3050static const unsigned int msiof3_sync_c_mux[] = {
3051 MSIOF3_SYNC_C_MARK,
3052};
3053static const unsigned int msiof3_txd_c_pins[] = {
3054 /* TXD */
3055 RCAR_GP_PIN(1, 15),
3056};
3057static const unsigned int msiof3_txd_c_mux[] = {
3058 MSIOF3_TXD_C_MARK,
3059};
3060static const unsigned int msiof3_rxd_c_pins[] = {
3061 /* RXD */
3062 RCAR_GP_PIN(1, 14),
3063};
3064static const unsigned int msiof3_rxd_c_mux[] = {
3065 MSIOF3_RXD_C_MARK,
3066};
3067static const unsigned int msiof3_clk_d_pins[] = {
3068 /* SCK */
3069 RCAR_GP_PIN(1, 22),
3070};
3071static const unsigned int msiof3_clk_d_mux[] = {
3072 MSIOF3_SCK_D_MARK,
3073};
3074static const unsigned int msiof3_sync_d_pins[] = {
3075 /* SYNC */
3076 RCAR_GP_PIN(1, 23),
3077};
3078static const unsigned int msiof3_sync_d_mux[] = {
3079 MSIOF3_SYNC_D_MARK,
3080};
3081static const unsigned int msiof3_ss1_d_pins[] = {
3082 /* SS1 */
3083 RCAR_GP_PIN(1, 26),
3084};
3085static const unsigned int msiof3_ss1_d_mux[] = {
3086 MSIOF3_SS1_D_MARK,
3087};
3088static const unsigned int msiof3_txd_d_pins[] = {
3089 /* TXD */
3090 RCAR_GP_PIN(1, 25),
3091};
3092static const unsigned int msiof3_txd_d_mux[] = {
3093 MSIOF3_TXD_D_MARK,
3094};
3095static const unsigned int msiof3_rxd_d_pins[] = {
3096 /* RXD */
3097 RCAR_GP_PIN(1, 24),
3098};
3099static const unsigned int msiof3_rxd_d_mux[] = {
3100 MSIOF3_RXD_D_MARK,
3101};
3102
3103static const unsigned int msiof3_clk_e_pins[] = {
3104 /* SCK */
3105 RCAR_GP_PIN(2, 3),
3106};
3107static const unsigned int msiof3_clk_e_mux[] = {
3108 MSIOF3_SCK_E_MARK,
3109};
3110static const unsigned int msiof3_sync_e_pins[] = {
3111 /* SYNC */
3112 RCAR_GP_PIN(2, 2),
3113};
3114static const unsigned int msiof3_sync_e_mux[] = {
3115 MSIOF3_SYNC_E_MARK,
3116};
3117static const unsigned int msiof3_ss1_e_pins[] = {
3118 /* SS1 */
3119 RCAR_GP_PIN(2, 1),
3120};
3121static const unsigned int msiof3_ss1_e_mux[] = {
3122 MSIOF3_SS1_E_MARK,
3123};
3124static const unsigned int msiof3_ss2_e_pins[] = {
3125 /* SS1 */
3126 RCAR_GP_PIN(2, 0),
3127};
3128static const unsigned int msiof3_ss2_e_mux[] = {
Geert Uytterhoevenb6db6bf2017-07-11 11:56:24 +0200[diff] [blame]3129 MSIOF3_SS2_E_MARK,
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]3130};
3131static const unsigned int msiof3_txd_e_pins[] = {
3132 /* TXD */
3133 RCAR_GP_PIN(2, 5),
3134};
3135static const unsigned int msiof3_txd_e_mux[] = {
3136 MSIOF3_TXD_E_MARK,
3137};
3138static const unsigned int msiof3_rxd_e_pins[] = {
3139 /* RXD */
3140 RCAR_GP_PIN(2, 4),
3141};
3142static const unsigned int msiof3_rxd_e_mux[] = {
3143 MSIOF3_RXD_E_MARK,
3144};
3145
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]3146/* - PWM0 --------------------------------------------------------------------*/
3147static const unsigned int pwm0_pins[] = {
3148 /* PWM */
3149 RCAR_GP_PIN(2, 6),
3150};
3151static const unsigned int pwm0_mux[] = {
3152 PWM0_MARK,
3153};
3154/* - PWM1 --------------------------------------------------------------------*/
3155static const unsigned int pwm1_a_pins[] = {
3156 /* PWM */
3157 RCAR_GP_PIN(2, 7),
3158};
3159static const unsigned int pwm1_a_mux[] = {
3160 PWM1_A_MARK,
3161};
3162static const unsigned int pwm1_b_pins[] = {
3163 /* PWM */
3164 RCAR_GP_PIN(1, 8),
3165};
3166static const unsigned int pwm1_b_mux[] = {
3167 PWM1_B_MARK,
3168};
3169/* - PWM2 --------------------------------------------------------------------*/
3170static const unsigned int pwm2_a_pins[] = {
3171 /* PWM */
3172 RCAR_GP_PIN(2, 8),
3173};
3174static const unsigned int pwm2_a_mux[] = {
3175 PWM2_A_MARK,
3176};
3177static const unsigned int pwm2_b_pins[] = {
3178 /* PWM */
3179 RCAR_GP_PIN(1, 11),
3180};
3181static const unsigned int pwm2_b_mux[] = {
3182 PWM2_B_MARK,
3183};
3184/* - PWM3 --------------------------------------------------------------------*/
3185static const unsigned int pwm3_a_pins[] = {
3186 /* PWM */
3187 RCAR_GP_PIN(1, 0),
3188};
3189static const unsigned int pwm3_a_mux[] = {
3190 PWM3_A_MARK,
3191};
3192static const unsigned int pwm3_b_pins[] = {
3193 /* PWM */
3194 RCAR_GP_PIN(2, 2),
3195};
3196static const unsigned int pwm3_b_mux[] = {
3197 PWM3_B_MARK,
3198};
3199/* - PWM4 --------------------------------------------------------------------*/
3200static const unsigned int pwm4_a_pins[] = {
3201 /* PWM */
3202 RCAR_GP_PIN(1, 1),
3203};
3204static const unsigned int pwm4_a_mux[] = {
3205 PWM4_A_MARK,
3206};
3207static const unsigned int pwm4_b_pins[] = {
3208 /* PWM */
3209 RCAR_GP_PIN(2, 3),
3210};
3211static const unsigned int pwm4_b_mux[] = {
3212 PWM4_B_MARK,
3213};
3214/* - PWM5 --------------------------------------------------------------------*/
3215static const unsigned int pwm5_a_pins[] = {
3216 /* PWM */
3217 RCAR_GP_PIN(1, 2),
3218};
3219static const unsigned int pwm5_a_mux[] = {
3220 PWM5_A_MARK,
3221};
3222static const unsigned int pwm5_b_pins[] = {
3223 /* PWM */
3224 RCAR_GP_PIN(2, 4),
3225};
3226static const unsigned int pwm5_b_mux[] = {
3227 PWM5_B_MARK,
3228};
3229/* - PWM6 --------------------------------------------------------------------*/
3230static const unsigned int pwm6_a_pins[] = {
3231 /* PWM */
3232 RCAR_GP_PIN(1, 3),
3233};
3234static const unsigned int pwm6_a_mux[] = {
3235 PWM6_A_MARK,
3236};
3237static const unsigned int pwm6_b_pins[] = {
3238 /* PWM */
3239 RCAR_GP_PIN(2, 5),
3240};
3241static const unsigned int pwm6_b_mux[] = {
3242 PWM6_B_MARK,
3243};
3244
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3245/* - SCIF0 ------------------------------------------------------------------ */
3246static const unsigned int scif0_data_pins[] = {
3247 /* RX, TX */
3248 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3249};
3250static const unsigned int scif0_data_mux[] = {
3251 RX0_MARK, TX0_MARK,
3252};
3253static const unsigned int scif0_clk_pins[] = {
3254 /* SCK */
3255 RCAR_GP_PIN(5, 0),
3256};
3257static const unsigned int scif0_clk_mux[] = {
3258 SCK0_MARK,
3259};
3260static const unsigned int scif0_ctrl_pins[] = {
3261 /* RTS, CTS */
3262 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3263};
3264static const unsigned int scif0_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3265 RTS0_N_MARK, CTS0_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3266};
3267/* - SCIF1 ------------------------------------------------------------------ */
3268static const unsigned int scif1_data_a_pins[] = {
3269 /* RX, TX */
3270 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3271};
3272static const unsigned int scif1_data_a_mux[] = {
3273 RX1_A_MARK, TX1_A_MARK,
3274};
3275static const unsigned int scif1_clk_pins[] = {
3276 /* SCK */
3277 RCAR_GP_PIN(6, 21),
3278};
3279static const unsigned int scif1_clk_mux[] = {
3280 SCK1_MARK,
3281};
3282static const unsigned int scif1_ctrl_pins[] = {
3283 /* RTS, CTS */
3284 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3285};
3286static const unsigned int scif1_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3287 RTS1_N_MARK, CTS1_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3288};
3289
3290static const unsigned int scif1_data_b_pins[] = {
3291 /* RX, TX */
3292 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3293};
3294static const unsigned int scif1_data_b_mux[] = {
3295 RX1_B_MARK, TX1_B_MARK,
3296};
3297/* - SCIF2 ------------------------------------------------------------------ */
3298static const unsigned int scif2_data_a_pins[] = {
3299 /* RX, TX */
3300 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3301};
3302static const unsigned int scif2_data_a_mux[] = {
3303 RX2_A_MARK, TX2_A_MARK,
3304};
3305static const unsigned int scif2_clk_pins[] = {
3306 /* SCK */
3307 RCAR_GP_PIN(5, 9),
3308};
3309static const unsigned int scif2_clk_mux[] = {
3310 SCK2_MARK,
3311};
3312static const unsigned int scif2_data_b_pins[] = {
3313 /* RX, TX */
3314 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3315};
3316static const unsigned int scif2_data_b_mux[] = {
3317 RX2_B_MARK, TX2_B_MARK,
3318};
3319/* - SCIF3 ------------------------------------------------------------------ */
3320static const unsigned int scif3_data_a_pins[] = {
3321 /* RX, TX */
3322 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3323};
3324static const unsigned int scif3_data_a_mux[] = {
3325 RX3_A_MARK, TX3_A_MARK,
3326};
3327static const unsigned int scif3_clk_pins[] = {
3328 /* SCK */
3329 RCAR_GP_PIN(1, 22),
3330};
3331static const unsigned int scif3_clk_mux[] = {
3332 SCK3_MARK,
3333};
3334static const unsigned int scif3_ctrl_pins[] = {
3335 /* RTS, CTS */
3336 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3337};
3338static const unsigned int scif3_ctrl_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3339 RTS3_N_MARK, CTS3_N_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3340};
3341static const unsigned int scif3_data_b_pins[] = {
3342 /* RX, TX */
3343 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3344};
3345static const unsigned int scif3_data_b_mux[] = {
3346 RX3_B_MARK, TX3_B_MARK,
3347};
3348/* - SCIF4 ------------------------------------------------------------------ */
3349static const unsigned int scif4_data_a_pins[] = {
3350 /* RX, TX */
3351 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3352};
3353static const unsigned int scif4_data_a_mux[] = {
3354 RX4_A_MARK, TX4_A_MARK,
3355};
3356static const unsigned int scif4_clk_a_pins[] = {
3357 /* SCK */
3358 RCAR_GP_PIN(2, 10),
3359};
3360static const unsigned int scif4_clk_a_mux[] = {
3361 SCK4_A_MARK,
3362};
3363static const unsigned int scif4_ctrl_a_pins[] = {
3364 /* RTS, CTS */
3365 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3366};
3367static const unsigned int scif4_ctrl_a_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3368 RTS4_N_A_MARK, CTS4_N_A_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3369};
3370static const unsigned int scif4_data_b_pins[] = {
3371 /* RX, TX */
3372 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3373};
3374static const unsigned int scif4_data_b_mux[] = {
3375 RX4_B_MARK, TX4_B_MARK,
3376};
3377static const unsigned int scif4_clk_b_pins[] = {
3378 /* SCK */
3379 RCAR_GP_PIN(1, 5),
3380};
3381static const unsigned int scif4_clk_b_mux[] = {
3382 SCK4_B_MARK,
3383};
3384static const unsigned int scif4_ctrl_b_pins[] = {
3385 /* RTS, CTS */
3386 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3387};
3388static const unsigned int scif4_ctrl_b_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3389 RTS4_N_B_MARK, CTS4_N_B_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3390};
3391static const unsigned int scif4_data_c_pins[] = {
3392 /* RX, TX */
3393 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3394};
3395static const unsigned int scif4_data_c_mux[] = {
3396 RX4_C_MARK, TX4_C_MARK,
3397};
3398static const unsigned int scif4_clk_c_pins[] = {
3399 /* SCK */
3400 RCAR_GP_PIN(0, 8),
3401};
3402static const unsigned int scif4_clk_c_mux[] = {
3403 SCK4_C_MARK,
3404};
3405static const unsigned int scif4_ctrl_c_pins[] = {
3406 /* RTS, CTS */
3407 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3408};
3409static const unsigned int scif4_ctrl_c_mux[] = {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]3410 RTS4_N_C_MARK, CTS4_N_C_MARK,
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]3411};
3412/* - SCIF5 ------------------------------------------------------------------ */
3413static const unsigned int scif5_data_a_pins[] = {
3414 /* RX, TX */
3415 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3416};
3417static const unsigned int scif5_data_a_mux[] = {
3418 RX5_A_MARK, TX5_A_MARK,
3419};
3420static const unsigned int scif5_clk_a_pins[] = {
3421 /* SCK */
3422 RCAR_GP_PIN(6, 21),
3423};
3424static const unsigned int scif5_clk_a_mux[] = {
3425 SCK5_A_MARK,
3426};
3427
3428static const unsigned int scif5_data_b_pins[] = {
3429 /* RX, TX */
3430 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3431};
3432static const unsigned int scif5_data_b_mux[] = {
3433 RX5_B_MARK, TX5_B_MARK,
3434};
3435static const unsigned int scif5_clk_b_pins[] = {
3436 /* SCK */
3437 RCAR_GP_PIN(5, 0),
3438};
3439static const unsigned int scif5_clk_b_mux[] = {
3440 SCK5_B_MARK,
3441};
3442
3443/* - SCIF Clock ------------------------------------------------------------- */
3444static const unsigned int scif_clk_a_pins[] = {
3445 /* SCIF_CLK */
3446 RCAR_GP_PIN(6, 23),
3447};
3448static const unsigned int scif_clk_a_mux[] = {
3449 SCIF_CLK_A_MARK,
3450};
3451static const unsigned int scif_clk_b_pins[] = {
3452 /* SCIF_CLK */
3453 RCAR_GP_PIN(5, 9),
3454};
3455static const unsigned int scif_clk_b_mux[] = {
3456 SCIF_CLK_B_MARK,
3457};
3458
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]3459/* - SDHI0 ------------------------------------------------------------------ */
3460static const unsigned int sdhi0_data1_pins[] = {
3461 /* D0 */
3462 RCAR_GP_PIN(3, 2),
3463};
3464static const unsigned int sdhi0_data1_mux[] = {
3465 SD0_DAT0_MARK,
3466};
3467static const unsigned int sdhi0_data4_pins[] = {
3468 /* D[0:3] */
3469 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3470 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3471};
3472static const unsigned int sdhi0_data4_mux[] = {
3473 SD0_DAT0_MARK, SD0_DAT1_MARK,
3474 SD0_DAT2_MARK, SD0_DAT3_MARK,
3475};
3476static const unsigned int sdhi0_ctrl_pins[] = {
3477 /* CLK, CMD */
3478 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3479};
3480static const unsigned int sdhi0_ctrl_mux[] = {
3481 SD0_CLK_MARK, SD0_CMD_MARK,
3482};
3483static const unsigned int sdhi0_cd_pins[] = {
3484 /* CD */
3485 RCAR_GP_PIN(3, 12),
3486};
3487static const unsigned int sdhi0_cd_mux[] = {
3488 SD0_CD_MARK,
3489};
3490static const unsigned int sdhi0_wp_pins[] = {
3491 /* WP */
3492 RCAR_GP_PIN(3, 13),
3493};
3494static const unsigned int sdhi0_wp_mux[] = {
3495 SD0_WP_MARK,
3496};
3497/* - SDHI1 ------------------------------------------------------------------ */
3498static const unsigned int sdhi1_data1_pins[] = {
3499 /* D0 */
3500 RCAR_GP_PIN(3, 8),
3501};
3502static const unsigned int sdhi1_data1_mux[] = {
3503 SD1_DAT0_MARK,
3504};
3505static const unsigned int sdhi1_data4_pins[] = {
3506 /* D[0:3] */
3507 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3508 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3509};
3510static const unsigned int sdhi1_data4_mux[] = {
3511 SD1_DAT0_MARK, SD1_DAT1_MARK,
3512 SD1_DAT2_MARK, SD1_DAT3_MARK,
3513};
3514static const unsigned int sdhi1_ctrl_pins[] = {
3515 /* CLK, CMD */
3516 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3517};
3518static const unsigned int sdhi1_ctrl_mux[] = {
3519 SD1_CLK_MARK, SD1_CMD_MARK,
3520};
3521static const unsigned int sdhi1_cd_pins[] = {
3522 /* CD */
3523 RCAR_GP_PIN(3, 14),
3524};
3525static const unsigned int sdhi1_cd_mux[] = {
3526 SD1_CD_MARK,
3527};
3528static const unsigned int sdhi1_wp_pins[] = {
3529 /* WP */
3530 RCAR_GP_PIN(3, 15),
3531};
3532static const unsigned int sdhi1_wp_mux[] = {
3533 SD1_WP_MARK,
3534};
3535/* - SDHI2 ------------------------------------------------------------------ */
3536static const unsigned int sdhi2_data1_pins[] = {
3537 /* D0 */
3538 RCAR_GP_PIN(4, 2),
3539};
3540static const unsigned int sdhi2_data1_mux[] = {
3541 SD2_DAT0_MARK,
3542};
3543static const unsigned int sdhi2_data4_pins[] = {
3544 /* D[0:3] */
3545 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3546 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3547};
3548static const unsigned int sdhi2_data4_mux[] = {
3549 SD2_DAT0_MARK, SD2_DAT1_MARK,
3550 SD2_DAT2_MARK, SD2_DAT3_MARK,
3551};
3552static const unsigned int sdhi2_data8_pins[] = {
3553 /* D[0:7] */
3554 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3555 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3556 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3557 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3558};
3559static const unsigned int sdhi2_data8_mux[] = {
3560 SD2_DAT0_MARK, SD2_DAT1_MARK,
3561 SD2_DAT2_MARK, SD2_DAT3_MARK,
3562 SD2_DAT4_MARK, SD2_DAT5_MARK,
3563 SD2_DAT6_MARK, SD2_DAT7_MARK,
3564};
3565static const unsigned int sdhi2_ctrl_pins[] = {
3566 /* CLK, CMD */
3567 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3568};
3569static const unsigned int sdhi2_ctrl_mux[] = {
3570 SD2_CLK_MARK, SD2_CMD_MARK,
3571};
3572static const unsigned int sdhi2_cd_a_pins[] = {
3573 /* CD */
3574 RCAR_GP_PIN(4, 13),
3575};
3576static const unsigned int sdhi2_cd_a_mux[] = {
3577 SD2_CD_A_MARK,
3578};
3579static const unsigned int sdhi2_cd_b_pins[] = {
3580 /* CD */
3581 RCAR_GP_PIN(5, 10),
3582};
3583static const unsigned int sdhi2_cd_b_mux[] = {
3584 SD2_CD_B_MARK,
3585};
3586static const unsigned int sdhi2_wp_a_pins[] = {
3587 /* WP */
3588 RCAR_GP_PIN(4, 14),
3589};
3590static const unsigned int sdhi2_wp_a_mux[] = {
3591 SD2_WP_A_MARK,
3592};
3593static const unsigned int sdhi2_wp_b_pins[] = {
3594 /* WP */
3595 RCAR_GP_PIN(5, 11),
3596};
3597static const unsigned int sdhi2_wp_b_mux[] = {
3598 SD2_WP_B_MARK,
3599};
3600static const unsigned int sdhi2_ds_pins[] = {
3601 /* DS */
3602 RCAR_GP_PIN(4, 6),
3603};
3604static const unsigned int sdhi2_ds_mux[] = {
3605 SD2_DS_MARK,
3606};
3607/* - SDHI3 ------------------------------------------------------------------ */
3608static const unsigned int sdhi3_data1_pins[] = {
3609 /* D0 */
3610 RCAR_GP_PIN(4, 9),
3611};
3612static const unsigned int sdhi3_data1_mux[] = {
3613 SD3_DAT0_MARK,
3614};
3615static const unsigned int sdhi3_data4_pins[] = {
3616 /* D[0:3] */
3617 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3618 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3619};
3620static const unsigned int sdhi3_data4_mux[] = {
3621 SD3_DAT0_MARK, SD3_DAT1_MARK,
3622 SD3_DAT2_MARK, SD3_DAT3_MARK,
3623};
3624static const unsigned int sdhi3_data8_pins[] = {
3625 /* D[0:7] */
3626 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3627 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3628 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3629 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3630};
3631static const unsigned int sdhi3_data8_mux[] = {
3632 SD3_DAT0_MARK, SD3_DAT1_MARK,
3633 SD3_DAT2_MARK, SD3_DAT3_MARK,
3634 SD3_DAT4_MARK, SD3_DAT5_MARK,
3635 SD3_DAT6_MARK, SD3_DAT7_MARK,
3636};
3637static const unsigned int sdhi3_ctrl_pins[] = {
3638 /* CLK, CMD */
3639 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3640};
3641static const unsigned int sdhi3_ctrl_mux[] = {
3642 SD3_CLK_MARK, SD3_CMD_MARK,
3643};
3644static const unsigned int sdhi3_cd_pins[] = {
3645 /* CD */
3646 RCAR_GP_PIN(4, 15),
3647};
3648static const unsigned int sdhi3_cd_mux[] = {
3649 SD3_CD_MARK,
3650};
3651static const unsigned int sdhi3_wp_pins[] = {
3652 /* WP */
3653 RCAR_GP_PIN(4, 16),
3654};
3655static const unsigned int sdhi3_wp_mux[] = {
3656 SD3_WP_MARK,
3657};
3658static const unsigned int sdhi3_ds_pins[] = {
3659 /* DS */
3660 RCAR_GP_PIN(4, 17),
3661};
3662static const unsigned int sdhi3_ds_mux[] = {
3663 SD3_DS_MARK,
3664};
3665
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]3666/* - SSI -------------------------------------------------------------------- */
3667static const unsigned int ssi0_data_pins[] = {
3668 /* SDATA */
3669 RCAR_GP_PIN(6, 2),
3670};
3671static const unsigned int ssi0_data_mux[] = {
3672 SSI_SDATA0_MARK,
3673};
3674static const unsigned int ssi01239_ctrl_pins[] = {
3675 /* SCK, WS */
3676 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3677};
3678static const unsigned int ssi01239_ctrl_mux[] = {
3679 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3680};
3681static const unsigned int ssi1_data_a_pins[] = {
3682 /* SDATA */
3683 RCAR_GP_PIN(6, 3),
3684};
3685static const unsigned int ssi1_data_a_mux[] = {
3686 SSI_SDATA1_A_MARK,
3687};
3688static const unsigned int ssi1_data_b_pins[] = {
3689 /* SDATA */
3690 RCAR_GP_PIN(5, 12),
3691};
3692static const unsigned int ssi1_data_b_mux[] = {
3693 SSI_SDATA1_B_MARK,
3694};
3695static const unsigned int ssi1_ctrl_a_pins[] = {
3696 /* SCK, WS */
3697 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3698};
3699static const unsigned int ssi1_ctrl_a_mux[] = {
3700 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3701};
3702static const unsigned int ssi1_ctrl_b_pins[] = {
3703 /* SCK, WS */
3704 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3705};
3706static const unsigned int ssi1_ctrl_b_mux[] = {
3707 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3708};
3709static const unsigned int ssi2_data_a_pins[] = {
3710 /* SDATA */
3711 RCAR_GP_PIN(6, 4),
3712};
3713static const unsigned int ssi2_data_a_mux[] = {
3714 SSI_SDATA2_A_MARK,
3715};
3716static const unsigned int ssi2_data_b_pins[] = {
3717 /* SDATA */
3718 RCAR_GP_PIN(5, 13),
3719};
3720static const unsigned int ssi2_data_b_mux[] = {
3721 SSI_SDATA2_B_MARK,
3722};
3723static const unsigned int ssi2_ctrl_a_pins[] = {
3724 /* SCK, WS */
3725 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3726};
3727static const unsigned int ssi2_ctrl_a_mux[] = {
3728 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3729};
3730static const unsigned int ssi2_ctrl_b_pins[] = {
3731 /* SCK, WS */
3732 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3733};
3734static const unsigned int ssi2_ctrl_b_mux[] = {
3735 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3736};
3737static const unsigned int ssi3_data_pins[] = {
3738 /* SDATA */
3739 RCAR_GP_PIN(6, 7),
3740};
3741static const unsigned int ssi3_data_mux[] = {
3742 SSI_SDATA3_MARK,
3743};
3744static const unsigned int ssi349_ctrl_pins[] = {
3745 /* SCK, WS */
3746 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3747};
3748static const unsigned int ssi349_ctrl_mux[] = {
3749 SSI_SCK349_MARK, SSI_WS349_MARK,
3750};
3751static const unsigned int ssi4_data_pins[] = {
3752 /* SDATA */
3753 RCAR_GP_PIN(6, 10),
3754};
3755static const unsigned int ssi4_data_mux[] = {
3756 SSI_SDATA4_MARK,
3757};
3758static const unsigned int ssi4_ctrl_pins[] = {
3759 /* SCK, WS */
3760 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3761};
3762static const unsigned int ssi4_ctrl_mux[] = {
3763 SSI_SCK4_MARK, SSI_WS4_MARK,
3764};
3765static const unsigned int ssi5_data_pins[] = {
3766 /* SDATA */
3767 RCAR_GP_PIN(6, 13),
3768};
3769static const unsigned int ssi5_data_mux[] = {
3770 SSI_SDATA5_MARK,
3771};
3772static const unsigned int ssi5_ctrl_pins[] = {
3773 /* SCK, WS */
3774 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3775};
3776static const unsigned int ssi5_ctrl_mux[] = {
3777 SSI_SCK5_MARK, SSI_WS5_MARK,
3778};
3779static const unsigned int ssi6_data_pins[] = {
3780 /* SDATA */
3781 RCAR_GP_PIN(6, 16),
3782};
3783static const unsigned int ssi6_data_mux[] = {
3784 SSI_SDATA6_MARK,
3785};
3786static const unsigned int ssi6_ctrl_pins[] = {
3787 /* SCK, WS */
3788 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3789};
3790static const unsigned int ssi6_ctrl_mux[] = {
3791 SSI_SCK6_MARK, SSI_WS6_MARK,
3792};
3793static const unsigned int ssi7_data_pins[] = {
3794 /* SDATA */
3795 RCAR_GP_PIN(6, 19),
3796};
3797static const unsigned int ssi7_data_mux[] = {
3798 SSI_SDATA7_MARK,
3799};
3800static const unsigned int ssi78_ctrl_pins[] = {
3801 /* SCK, WS */
3802 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3803};
3804static const unsigned int ssi78_ctrl_mux[] = {
3805 SSI_SCK78_MARK, SSI_WS78_MARK,
3806};
3807static const unsigned int ssi8_data_pins[] = {
3808 /* SDATA */
3809 RCAR_GP_PIN(6, 20),
3810};
3811static const unsigned int ssi8_data_mux[] = {
3812 SSI_SDATA8_MARK,
3813};
3814static const unsigned int ssi9_data_a_pins[] = {
3815 /* SDATA */
3816 RCAR_GP_PIN(6, 21),
3817};
3818static const unsigned int ssi9_data_a_mux[] = {
3819 SSI_SDATA9_A_MARK,
3820};
3821static const unsigned int ssi9_data_b_pins[] = {
3822 /* SDATA */
3823 RCAR_GP_PIN(5, 14),
3824};
3825static const unsigned int ssi9_data_b_mux[] = {
3826 SSI_SDATA9_B_MARK,
3827};
3828static const unsigned int ssi9_ctrl_a_pins[] = {
3829 /* SCK, WS */
3830 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3831};
3832static const unsigned int ssi9_ctrl_a_mux[] = {
3833 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3834};
3835static const unsigned int ssi9_ctrl_b_pins[] = {
3836 /* SCK, WS */
3837 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3838};
3839static const unsigned int ssi9_ctrl_b_mux[] = {
3840 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3841};
3842
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]3843/* - USB0 ------------------------------------------------------------------- */
3844static const unsigned int usb0_pins[] = {
3845 /* PWEN, OVC */
3846 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3847};
3848static const unsigned int usb0_mux[] = {
3849 USB0_PWEN_MARK, USB0_OVC_MARK,
3850};
3851/* - USB1 ------------------------------------------------------------------- */
3852static const unsigned int usb1_pins[] = {
3853 /* PWEN, OVC */
3854 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3855};
3856static const unsigned int usb1_mux[] = {
3857 USB1_PWEN_MARK, USB1_OVC_MARK,
3858};
3859
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]3860/* - USB30 ------------------------------------------------------------------ */
3861static const unsigned int usb30_pins[] = {
3862 /* PWEN, OVC */
3863 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3864};
3865static const unsigned int usb30_mux[] = {
3866 USB30_PWEN_MARK, USB30_OVC_MARK,
3867};
3868
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]3869static const struct sh_pfc_pin_group pinmux_groups[] = {
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]3870 SH_PFC_PIN_GROUP(audio_clk_a_a),
3871 SH_PFC_PIN_GROUP(audio_clk_a_b),
3872 SH_PFC_PIN_GROUP(audio_clk_a_c),
3873 SH_PFC_PIN_GROUP(audio_clk_b_a),
3874 SH_PFC_PIN_GROUP(audio_clk_b_b),
3875 SH_PFC_PIN_GROUP(audio_clk_c_a),
3876 SH_PFC_PIN_GROUP(audio_clk_c_b),
3877 SH_PFC_PIN_GROUP(audio_clkout_a),
3878 SH_PFC_PIN_GROUP(audio_clkout_b),
3879 SH_PFC_PIN_GROUP(audio_clkout_c),
3880 SH_PFC_PIN_GROUP(audio_clkout_d),
3881 SH_PFC_PIN_GROUP(audio_clkout1_a),
3882 SH_PFC_PIN_GROUP(audio_clkout1_b),
3883 SH_PFC_PIN_GROUP(audio_clkout2_a),
3884 SH_PFC_PIN_GROUP(audio_clkout2_b),
3885 SH_PFC_PIN_GROUP(audio_clkout3_a),
3886 SH_PFC_PIN_GROUP(audio_clkout3_b),
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]3887 SH_PFC_PIN_GROUP(avb_link),
3888 SH_PFC_PIN_GROUP(avb_magic),
3889 SH_PFC_PIN_GROUP(avb_phy_int),
3890 SH_PFC_PIN_GROUP(avb_mdc),
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]3891 SH_PFC_PIN_GROUP(avb_mii),
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]3892 SH_PFC_PIN_GROUP(avb_avtp_pps),
3893 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3894 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3895 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3896 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]3897 SH_PFC_PIN_GROUP(can0_data_a),
3898 SH_PFC_PIN_GROUP(can0_data_b),
3899 SH_PFC_PIN_GROUP(can1_data),
3900 SH_PFC_PIN_GROUP(can_clk),
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]3901 SH_PFC_PIN_GROUP(canfd0_data_a),
3902 SH_PFC_PIN_GROUP(canfd0_data_b),
3903 SH_PFC_PIN_GROUP(canfd1_data),
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]3904 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3905 SH_PFC_PIN_GROUP(drif0_data0_a),
3906 SH_PFC_PIN_GROUP(drif0_data1_a),
3907 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3908 SH_PFC_PIN_GROUP(drif0_data0_b),
3909 SH_PFC_PIN_GROUP(drif0_data1_b),
3910 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3911 SH_PFC_PIN_GROUP(drif0_data0_c),
3912 SH_PFC_PIN_GROUP(drif0_data1_c),
3913 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3914 SH_PFC_PIN_GROUP(drif1_data0_a),
3915 SH_PFC_PIN_GROUP(drif1_data1_a),
3916 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3917 SH_PFC_PIN_GROUP(drif1_data0_b),
3918 SH_PFC_PIN_GROUP(drif1_data1_b),
3919 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3920 SH_PFC_PIN_GROUP(drif1_data0_c),
3921 SH_PFC_PIN_GROUP(drif1_data1_c),
3922 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3923 SH_PFC_PIN_GROUP(drif2_data0_a),
3924 SH_PFC_PIN_GROUP(drif2_data1_a),
3925 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3926 SH_PFC_PIN_GROUP(drif2_data0_b),
3927 SH_PFC_PIN_GROUP(drif2_data1_b),
3928 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3929 SH_PFC_PIN_GROUP(drif3_data0_a),
3930 SH_PFC_PIN_GROUP(drif3_data1_a),
3931 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3932 SH_PFC_PIN_GROUP(drif3_data0_b),
3933 SH_PFC_PIN_GROUP(drif3_data1_b),
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]3934 SH_PFC_PIN_GROUP(du_rgb666),
3935 SH_PFC_PIN_GROUP(du_rgb888),
3936 SH_PFC_PIN_GROUP(du_clk_out_0),
3937 SH_PFC_PIN_GROUP(du_clk_out_1),
3938 SH_PFC_PIN_GROUP(du_sync),
3939 SH_PFC_PIN_GROUP(du_oddf),
3940 SH_PFC_PIN_GROUP(du_cde),
3941 SH_PFC_PIN_GROUP(du_disp),
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame^]3942 SH_PFC_PIN_GROUP(hdmi0_cec),
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]3943 SH_PFC_PIN_GROUP(hscif0_data),
3944 SH_PFC_PIN_GROUP(hscif0_clk),
3945 SH_PFC_PIN_GROUP(hscif0_ctrl),
3946 SH_PFC_PIN_GROUP(hscif1_data_a),
3947 SH_PFC_PIN_GROUP(hscif1_clk_a),
3948 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3949 SH_PFC_PIN_GROUP(hscif1_data_b),
3950 SH_PFC_PIN_GROUP(hscif1_clk_b),
3951 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3952 SH_PFC_PIN_GROUP(hscif2_data_a),
3953 SH_PFC_PIN_GROUP(hscif2_clk_a),
3954 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3955 SH_PFC_PIN_GROUP(hscif2_data_b),
3956 SH_PFC_PIN_GROUP(hscif2_clk_b),
3957 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3958 SH_PFC_PIN_GROUP(hscif2_data_c),
3959 SH_PFC_PIN_GROUP(hscif2_clk_c),
3960 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3961 SH_PFC_PIN_GROUP(hscif3_data_a),
3962 SH_PFC_PIN_GROUP(hscif3_clk),
3963 SH_PFC_PIN_GROUP(hscif3_ctrl),
3964 SH_PFC_PIN_GROUP(hscif3_data_b),
3965 SH_PFC_PIN_GROUP(hscif3_data_c),
3966 SH_PFC_PIN_GROUP(hscif3_data_d),
3967 SH_PFC_PIN_GROUP(hscif4_data_a),
3968 SH_PFC_PIN_GROUP(hscif4_clk),
3969 SH_PFC_PIN_GROUP(hscif4_ctrl),
3970 SH_PFC_PIN_GROUP(hscif4_data_b),
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]3971 SH_PFC_PIN_GROUP(i2c1_a),
3972 SH_PFC_PIN_GROUP(i2c1_b),
3973 SH_PFC_PIN_GROUP(i2c2_a),
3974 SH_PFC_PIN_GROUP(i2c2_b),
3975 SH_PFC_PIN_GROUP(i2c6_a),
3976 SH_PFC_PIN_GROUP(i2c6_b),
3977 SH_PFC_PIN_GROUP(i2c6_c),
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]3978 SH_PFC_PIN_GROUP(intc_ex_irq0),
3979 SH_PFC_PIN_GROUP(intc_ex_irq1),
3980 SH_PFC_PIN_GROUP(intc_ex_irq2),
3981 SH_PFC_PIN_GROUP(intc_ex_irq3),
3982 SH_PFC_PIN_GROUP(intc_ex_irq4),
3983 SH_PFC_PIN_GROUP(intc_ex_irq5),
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]3984 SH_PFC_PIN_GROUP(msiof0_clk),
3985 SH_PFC_PIN_GROUP(msiof0_sync),
3986 SH_PFC_PIN_GROUP(msiof0_ss1),
3987 SH_PFC_PIN_GROUP(msiof0_ss2),
3988 SH_PFC_PIN_GROUP(msiof0_txd),
3989 SH_PFC_PIN_GROUP(msiof0_rxd),
3990 SH_PFC_PIN_GROUP(msiof1_clk_a),
3991 SH_PFC_PIN_GROUP(msiof1_sync_a),
3992 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3993 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3994 SH_PFC_PIN_GROUP(msiof1_txd_a),
3995 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3996 SH_PFC_PIN_GROUP(msiof1_clk_b),
3997 SH_PFC_PIN_GROUP(msiof1_sync_b),
3998 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3999 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4000 SH_PFC_PIN_GROUP(msiof1_txd_b),
4001 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4002 SH_PFC_PIN_GROUP(msiof1_clk_c),
4003 SH_PFC_PIN_GROUP(msiof1_sync_c),
4004 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4005 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4006 SH_PFC_PIN_GROUP(msiof1_txd_c),
4007 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4008 SH_PFC_PIN_GROUP(msiof1_clk_d),
4009 SH_PFC_PIN_GROUP(msiof1_sync_d),
4010 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4011 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4012 SH_PFC_PIN_GROUP(msiof1_txd_d),
4013 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4014 SH_PFC_PIN_GROUP(msiof1_clk_e),
4015 SH_PFC_PIN_GROUP(msiof1_sync_e),
4016 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4017 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4018 SH_PFC_PIN_GROUP(msiof1_txd_e),
4019 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4020 SH_PFC_PIN_GROUP(msiof1_clk_f),
4021 SH_PFC_PIN_GROUP(msiof1_sync_f),
4022 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4023 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4024 SH_PFC_PIN_GROUP(msiof1_txd_f),
4025 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4026 SH_PFC_PIN_GROUP(msiof1_clk_g),
4027 SH_PFC_PIN_GROUP(msiof1_sync_g),
4028 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4029 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4030 SH_PFC_PIN_GROUP(msiof1_txd_g),
4031 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4032 SH_PFC_PIN_GROUP(msiof2_clk_a),
4033 SH_PFC_PIN_GROUP(msiof2_sync_a),
4034 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4035 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4036 SH_PFC_PIN_GROUP(msiof2_txd_a),
4037 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4038 SH_PFC_PIN_GROUP(msiof2_clk_b),
4039 SH_PFC_PIN_GROUP(msiof2_sync_b),
4040 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4041 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4042 SH_PFC_PIN_GROUP(msiof2_txd_b),
4043 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4044 SH_PFC_PIN_GROUP(msiof2_clk_c),
4045 SH_PFC_PIN_GROUP(msiof2_sync_c),
4046 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4047 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4048 SH_PFC_PIN_GROUP(msiof2_txd_c),
4049 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4050 SH_PFC_PIN_GROUP(msiof2_clk_d),
4051 SH_PFC_PIN_GROUP(msiof2_sync_d),
4052 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4053 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4054 SH_PFC_PIN_GROUP(msiof2_txd_d),
4055 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4056 SH_PFC_PIN_GROUP(msiof3_clk_a),
4057 SH_PFC_PIN_GROUP(msiof3_sync_a),
4058 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4059 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4060 SH_PFC_PIN_GROUP(msiof3_txd_a),
4061 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4062 SH_PFC_PIN_GROUP(msiof3_clk_b),
4063 SH_PFC_PIN_GROUP(msiof3_sync_b),
4064 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4065 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4066 SH_PFC_PIN_GROUP(msiof3_txd_b),
4067 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4068 SH_PFC_PIN_GROUP(msiof3_clk_c),
4069 SH_PFC_PIN_GROUP(msiof3_sync_c),
4070 SH_PFC_PIN_GROUP(msiof3_txd_c),
4071 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4072 SH_PFC_PIN_GROUP(msiof3_clk_d),
4073 SH_PFC_PIN_GROUP(msiof3_sync_d),
4074 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4075 SH_PFC_PIN_GROUP(msiof3_txd_d),
4076 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4077 SH_PFC_PIN_GROUP(msiof3_clk_e),
4078 SH_PFC_PIN_GROUP(msiof3_sync_e),
4079 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4080 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4081 SH_PFC_PIN_GROUP(msiof3_txd_e),
4082 SH_PFC_PIN_GROUP(msiof3_rxd_e),
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]4083 SH_PFC_PIN_GROUP(pwm0),
4084 SH_PFC_PIN_GROUP(pwm1_a),
4085 SH_PFC_PIN_GROUP(pwm1_b),
4086 SH_PFC_PIN_GROUP(pwm2_a),
4087 SH_PFC_PIN_GROUP(pwm2_b),
4088 SH_PFC_PIN_GROUP(pwm3_a),
4089 SH_PFC_PIN_GROUP(pwm3_b),
4090 SH_PFC_PIN_GROUP(pwm4_a),
4091 SH_PFC_PIN_GROUP(pwm4_b),
4092 SH_PFC_PIN_GROUP(pwm5_a),
4093 SH_PFC_PIN_GROUP(pwm5_b),
4094 SH_PFC_PIN_GROUP(pwm6_a),
4095 SH_PFC_PIN_GROUP(pwm6_b),
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4096 SH_PFC_PIN_GROUP(scif0_data),
4097 SH_PFC_PIN_GROUP(scif0_clk),
4098 SH_PFC_PIN_GROUP(scif0_ctrl),
4099 SH_PFC_PIN_GROUP(scif1_data_a),
4100 SH_PFC_PIN_GROUP(scif1_clk),
4101 SH_PFC_PIN_GROUP(scif1_ctrl),
4102 SH_PFC_PIN_GROUP(scif1_data_b),
4103 SH_PFC_PIN_GROUP(scif2_data_a),
4104 SH_PFC_PIN_GROUP(scif2_clk),
4105 SH_PFC_PIN_GROUP(scif2_data_b),
4106 SH_PFC_PIN_GROUP(scif3_data_a),
4107 SH_PFC_PIN_GROUP(scif3_clk),
4108 SH_PFC_PIN_GROUP(scif3_ctrl),
4109 SH_PFC_PIN_GROUP(scif3_data_b),
4110 SH_PFC_PIN_GROUP(scif4_data_a),
4111 SH_PFC_PIN_GROUP(scif4_clk_a),
4112 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4113 SH_PFC_PIN_GROUP(scif4_data_b),
4114 SH_PFC_PIN_GROUP(scif4_clk_b),
4115 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4116 SH_PFC_PIN_GROUP(scif4_data_c),
4117 SH_PFC_PIN_GROUP(scif4_clk_c),
4118 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4119 SH_PFC_PIN_GROUP(scif5_data_a),
4120 SH_PFC_PIN_GROUP(scif5_clk_a),
4121 SH_PFC_PIN_GROUP(scif5_data_b),
4122 SH_PFC_PIN_GROUP(scif5_clk_b),
4123 SH_PFC_PIN_GROUP(scif_clk_a),
4124 SH_PFC_PIN_GROUP(scif_clk_b),
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]4125 SH_PFC_PIN_GROUP(sdhi0_data1),
4126 SH_PFC_PIN_GROUP(sdhi0_data4),
4127 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4128 SH_PFC_PIN_GROUP(sdhi0_cd),
4129 SH_PFC_PIN_GROUP(sdhi0_wp),
4130 SH_PFC_PIN_GROUP(sdhi1_data1),
4131 SH_PFC_PIN_GROUP(sdhi1_data4),
4132 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4133 SH_PFC_PIN_GROUP(sdhi1_cd),
4134 SH_PFC_PIN_GROUP(sdhi1_wp),
4135 SH_PFC_PIN_GROUP(sdhi2_data1),
4136 SH_PFC_PIN_GROUP(sdhi2_data4),
4137 SH_PFC_PIN_GROUP(sdhi2_data8),
4138 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4139 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4140 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4141 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4142 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4143 SH_PFC_PIN_GROUP(sdhi2_ds),
4144 SH_PFC_PIN_GROUP(sdhi3_data1),
4145 SH_PFC_PIN_GROUP(sdhi3_data4),
4146 SH_PFC_PIN_GROUP(sdhi3_data8),
4147 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4148 SH_PFC_PIN_GROUP(sdhi3_cd),
4149 SH_PFC_PIN_GROUP(sdhi3_wp),
4150 SH_PFC_PIN_GROUP(sdhi3_ds),
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]4151 SH_PFC_PIN_GROUP(ssi0_data),
4152 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4153 SH_PFC_PIN_GROUP(ssi1_data_a),
4154 SH_PFC_PIN_GROUP(ssi1_data_b),
4155 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4156 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4157 SH_PFC_PIN_GROUP(ssi2_data_a),
4158 SH_PFC_PIN_GROUP(ssi2_data_b),
4159 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4160 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4161 SH_PFC_PIN_GROUP(ssi3_data),
4162 SH_PFC_PIN_GROUP(ssi349_ctrl),
4163 SH_PFC_PIN_GROUP(ssi4_data),
4164 SH_PFC_PIN_GROUP(ssi4_ctrl),
4165 SH_PFC_PIN_GROUP(ssi5_data),
4166 SH_PFC_PIN_GROUP(ssi5_ctrl),
4167 SH_PFC_PIN_GROUP(ssi6_data),
4168 SH_PFC_PIN_GROUP(ssi6_ctrl),
4169 SH_PFC_PIN_GROUP(ssi7_data),
4170 SH_PFC_PIN_GROUP(ssi78_ctrl),
4171 SH_PFC_PIN_GROUP(ssi8_data),
4172 SH_PFC_PIN_GROUP(ssi9_data_a),
4173 SH_PFC_PIN_GROUP(ssi9_data_b),
4174 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4175 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]4176 SH_PFC_PIN_GROUP(usb0),
4177 SH_PFC_PIN_GROUP(usb1),
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]4178 SH_PFC_PIN_GROUP(usb30),
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4179};
4180
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]4181static const char * const audio_clk_groups[] = {
4182 "audio_clk_a_a",
4183 "audio_clk_a_b",
4184 "audio_clk_a_c",
4185 "audio_clk_b_a",
4186 "audio_clk_b_b",
4187 "audio_clk_c_a",
4188 "audio_clk_c_b",
4189 "audio_clkout_a",
4190 "audio_clkout_b",
4191 "audio_clkout_c",
4192 "audio_clkout_d",
4193 "audio_clkout1_a",
4194 "audio_clkout1_b",
4195 "audio_clkout2_a",
4196 "audio_clkout2_b",
4197 "audio_clkout3_a",
4198 "audio_clkout3_b",
4199};
4200
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]4201static const char * const avb_groups[] = {
4202 "avb_link",
4203 "avb_magic",
4204 "avb_phy_int",
4205 "avb_mdc",
Geert Uytterhoeven41397032017-04-19 14:41:21 +0200[diff] [blame]4206 "avb_mii",
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]4207 "avb_avtp_pps",
4208 "avb_avtp_match_a",
4209 "avb_avtp_capture_a",
4210 "avb_avtp_match_b",
4211 "avb_avtp_capture_b",
4212};
4213
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]4214static const char * const can0_groups[] = {
4215 "can0_data_a",
4216 "can0_data_b",
4217};
4218
4219static const char * const can1_groups[] = {
4220 "can1_data",
4221};
4222
4223static const char * const can_clk_groups[] = {
4224 "can_clk",
4225};
4226
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]4227static const char * const canfd0_groups[] = {
4228 "canfd0_data_a",
4229 "canfd0_data_b",
4230};
4231
4232static const char * const canfd1_groups[] = {
4233 "canfd1_data",
4234};
4235
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]4236static const char * const drif0_groups[] = {
4237 "drif0_ctrl_a",
4238 "drif0_data0_a",
4239 "drif0_data1_a",
4240 "drif0_ctrl_b",
4241 "drif0_data0_b",
4242 "drif0_data1_b",
4243 "drif0_ctrl_c",
4244 "drif0_data0_c",
4245 "drif0_data1_c",
4246};
4247
4248static const char * const drif1_groups[] = {
4249 "drif1_ctrl_a",
4250 "drif1_data0_a",
4251 "drif1_data1_a",
4252 "drif1_ctrl_b",
4253 "drif1_data0_b",
4254 "drif1_data1_b",
4255 "drif1_ctrl_c",
4256 "drif1_data0_c",
4257 "drif1_data1_c",
4258};
4259
4260static const char * const drif2_groups[] = {
4261 "drif2_ctrl_a",
4262 "drif2_data0_a",
4263 "drif2_data1_a",
4264 "drif2_ctrl_b",
4265 "drif2_data0_b",
4266 "drif2_data1_b",
4267};
4268
4269static const char * const drif3_groups[] = {
4270 "drif3_ctrl_a",
4271 "drif3_data0_a",
4272 "drif3_data1_a",
4273 "drif3_ctrl_b",
4274 "drif3_data0_b",
4275 "drif3_data1_b",
4276};
4277
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]4278static const char * const du_groups[] = {
4279 "du_rgb666",
4280 "du_rgb888",
4281 "du_clk_out_0",
4282 "du_clk_out_1",
4283 "du_sync",
4284 "du_oddf",
4285 "du_cde",
4286 "du_disp",
4287};
4288
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame^]4289static const char * const hdmi0_groups[] = {
4290 "hdmi0_cec",
4291};
4292
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]4293static const char * const hscif0_groups[] = {
4294 "hscif0_data",
4295 "hscif0_clk",
4296 "hscif0_ctrl",
4297};
4298
4299static const char * const hscif1_groups[] = {
4300 "hscif1_data_a",
4301 "hscif1_clk_a",
4302 "hscif1_ctrl_a",
4303 "hscif1_data_b",
4304 "hscif1_clk_b",
4305 "hscif1_ctrl_b",
4306};
4307
4308static const char * const hscif2_groups[] = {
4309 "hscif2_data_a",
4310 "hscif2_clk_a",
4311 "hscif2_ctrl_a",
4312 "hscif2_data_b",
4313 "hscif2_clk_b",
4314 "hscif2_ctrl_b",
4315 "hscif2_data_c",
4316 "hscif2_clk_c",
4317 "hscif2_ctrl_c",
4318};
4319
4320static const char * const hscif3_groups[] = {
4321 "hscif3_data_a",
4322 "hscif3_clk",
4323 "hscif3_ctrl",
4324 "hscif3_data_b",
4325 "hscif3_data_c",
4326 "hscif3_data_d",
4327};
4328
4329static const char * const hscif4_groups[] = {
4330 "hscif4_data_a",
4331 "hscif4_clk",
4332 "hscif4_ctrl",
4333 "hscif4_data_b",
4334};
4335
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]4336static const char * const i2c1_groups[] = {
4337 "i2c1_a",
4338 "i2c1_b",
4339};
4340
4341static const char * const i2c2_groups[] = {
4342 "i2c2_a",
4343 "i2c2_b",
4344};
4345
4346static const char * const i2c6_groups[] = {
4347 "i2c6_a",
4348 "i2c6_b",
4349 "i2c6_c",
4350};
4351
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]4352static const char * const intc_ex_groups[] = {
4353 "intc_ex_irq0",
4354 "intc_ex_irq1",
4355 "intc_ex_irq2",
4356 "intc_ex_irq3",
4357 "intc_ex_irq4",
4358 "intc_ex_irq5",
4359};
4360
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]4361static const char * const msiof0_groups[] = {
4362 "msiof0_clk",
4363 "msiof0_sync",
4364 "msiof0_ss1",
4365 "msiof0_ss2",
4366 "msiof0_txd",
4367 "msiof0_rxd",
4368};
4369
4370static const char * const msiof1_groups[] = {
4371 "msiof1_clk_a",
4372 "msiof1_sync_a",
4373 "msiof1_ss1_a",
4374 "msiof1_ss2_a",
4375 "msiof1_txd_a",
4376 "msiof1_rxd_a",
4377 "msiof1_clk_b",
4378 "msiof1_sync_b",
4379 "msiof1_ss1_b",
4380 "msiof1_ss2_b",
4381 "msiof1_txd_b",
4382 "msiof1_rxd_b",
4383 "msiof1_clk_c",
4384 "msiof1_sync_c",
4385 "msiof1_ss1_c",
4386 "msiof1_ss2_c",
4387 "msiof1_txd_c",
4388 "msiof1_rxd_c",
4389 "msiof1_clk_d",
4390 "msiof1_sync_d",
4391 "msiof1_ss1_d",
4392 "msiof1_ss2_d",
4393 "msiof1_txd_d",
4394 "msiof1_rxd_d",
4395 "msiof1_clk_e",
4396 "msiof1_sync_e",
4397 "msiof1_ss1_e",
4398 "msiof1_ss2_e",
4399 "msiof1_txd_e",
4400 "msiof1_rxd_e",
4401 "msiof1_clk_f",
4402 "msiof1_sync_f",
4403 "msiof1_ss1_f",
4404 "msiof1_ss2_f",
4405 "msiof1_txd_f",
4406 "msiof1_rxd_f",
4407 "msiof1_clk_g",
4408 "msiof1_sync_g",
4409 "msiof1_ss1_g",
4410 "msiof1_ss2_g",
4411 "msiof1_txd_g",
4412 "msiof1_rxd_g",
4413};
4414
4415static const char * const msiof2_groups[] = {
4416 "msiof2_clk_a",
4417 "msiof2_sync_a",
4418 "msiof2_ss1_a",
4419 "msiof2_ss2_a",
4420 "msiof2_txd_a",
4421 "msiof2_rxd_a",
4422 "msiof2_clk_b",
4423 "msiof2_sync_b",
4424 "msiof2_ss1_b",
4425 "msiof2_ss2_b",
4426 "msiof2_txd_b",
4427 "msiof2_rxd_b",
4428 "msiof2_clk_c",
4429 "msiof2_sync_c",
4430 "msiof2_ss1_c",
4431 "msiof2_ss2_c",
4432 "msiof2_txd_c",
4433 "msiof2_rxd_c",
4434 "msiof2_clk_d",
4435 "msiof2_sync_d",
4436 "msiof2_ss1_d",
4437 "msiof2_ss2_d",
4438 "msiof2_txd_d",
4439 "msiof2_rxd_d",
4440};
4441
4442static const char * const msiof3_groups[] = {
4443 "msiof3_clk_a",
4444 "msiof3_sync_a",
4445 "msiof3_ss1_a",
4446 "msiof3_ss2_a",
4447 "msiof3_txd_a",
4448 "msiof3_rxd_a",
4449 "msiof3_clk_b",
4450 "msiof3_sync_b",
4451 "msiof3_ss1_b",
4452 "msiof3_ss2_b",
4453 "msiof3_txd_b",
4454 "msiof3_rxd_b",
4455 "msiof3_clk_c",
4456 "msiof3_sync_c",
4457 "msiof3_txd_c",
4458 "msiof3_rxd_c",
4459 "msiof3_clk_d",
4460 "msiof3_sync_d",
4461 "msiof3_ss1_d",
4462 "msiof3_txd_d",
4463 "msiof3_rxd_d",
4464 "msiof3_clk_e",
4465 "msiof3_sync_e",
4466 "msiof3_ss1_e",
4467 "msiof3_ss2_e",
4468 "msiof3_txd_e",
4469 "msiof3_rxd_e",
4470};
4471
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]4472static const char * const pwm0_groups[] = {
4473 "pwm0",
4474};
4475
4476static const char * const pwm1_groups[] = {
4477 "pwm1_a",
4478 "pwm1_b",
4479};
4480
4481static const char * const pwm2_groups[] = {
4482 "pwm2_a",
4483 "pwm2_b",
4484};
4485
4486static const char * const pwm3_groups[] = {
4487 "pwm3_a",
4488 "pwm3_b",
4489};
4490
4491static const char * const pwm4_groups[] = {
4492 "pwm4_a",
4493 "pwm4_b",
4494};
4495
4496static const char * const pwm5_groups[] = {
4497 "pwm5_a",
4498 "pwm5_b",
4499};
4500
4501static const char * const pwm6_groups[] = {
4502 "pwm6_a",
4503 "pwm6_b",
4504};
4505
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4506static const char * const scif0_groups[] = {
4507 "scif0_data",
4508 "scif0_clk",
4509 "scif0_ctrl",
4510};
4511
4512static const char * const scif1_groups[] = {
4513 "scif1_data_a",
4514 "scif1_clk",
4515 "scif1_ctrl",
4516 "scif1_data_b",
4517};
4518
4519static const char * const scif2_groups[] = {
4520 "scif2_data_a",
4521 "scif2_clk",
4522 "scif2_data_b",
4523};
4524
4525static const char * const scif3_groups[] = {
4526 "scif3_data_a",
4527 "scif3_clk",
4528 "scif3_ctrl",
4529 "scif3_data_b",
4530};
4531
4532static const char * const scif4_groups[] = {
4533 "scif4_data_a",
4534 "scif4_clk_a",
4535 "scif4_ctrl_a",
4536 "scif4_data_b",
4537 "scif4_clk_b",
4538 "scif4_ctrl_b",
4539 "scif4_data_c",
4540 "scif4_clk_c",
4541 "scif4_ctrl_c",
4542};
4543
4544static const char * const scif5_groups[] = {
4545 "scif5_data_a",
4546 "scif5_clk_a",
4547 "scif5_data_b",
4548 "scif5_clk_b",
4549};
4550
4551static const char * const scif_clk_groups[] = {
4552 "scif_clk_a",
4553 "scif_clk_b",
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]4554};
4555
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]4556static const char * const sdhi0_groups[] = {
4557 "sdhi0_data1",
4558 "sdhi0_data4",
4559 "sdhi0_ctrl",
4560 "sdhi0_cd",
4561 "sdhi0_wp",
4562};
4563
4564static const char * const sdhi1_groups[] = {
4565 "sdhi1_data1",
4566 "sdhi1_data4",
4567 "sdhi1_ctrl",
4568 "sdhi1_cd",
4569 "sdhi1_wp",
4570};
4571
4572static const char * const sdhi2_groups[] = {
4573 "sdhi2_data1",
4574 "sdhi2_data4",
4575 "sdhi2_data8",
4576 "sdhi2_ctrl",
4577 "sdhi2_cd_a",
4578 "sdhi2_wp_a",
4579 "sdhi2_cd_b",
4580 "sdhi2_wp_b",
4581 "sdhi2_ds",
4582};
4583
4584static const char * const sdhi3_groups[] = {
4585 "sdhi3_data1",
4586 "sdhi3_data4",
4587 "sdhi3_data8",
4588 "sdhi3_ctrl",
4589 "sdhi3_cd",
4590 "sdhi3_wp",
4591 "sdhi3_ds",
4592};
4593
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]4594static const char * const ssi_groups[] = {
4595 "ssi0_data",
4596 "ssi01239_ctrl",
4597 "ssi1_data_a",
4598 "ssi1_data_b",
4599 "ssi1_ctrl_a",
4600 "ssi1_ctrl_b",
4601 "ssi2_data_a",
4602 "ssi2_data_b",
4603 "ssi2_ctrl_a",
4604 "ssi2_ctrl_b",
4605 "ssi3_data",
4606 "ssi349_ctrl",
4607 "ssi4_data",
4608 "ssi4_ctrl",
4609 "ssi5_data",
4610 "ssi5_ctrl",
4611 "ssi6_data",
4612 "ssi6_ctrl",
4613 "ssi7_data",
4614 "ssi78_ctrl",
4615 "ssi8_data",
4616 "ssi9_data_a",
4617 "ssi9_data_b",
4618 "ssi9_ctrl_a",
4619 "ssi9_ctrl_b",
4620};
4621
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]4622static const char * const usb0_groups[] = {
4623 "usb0",
4624};
4625
4626static const char * const usb1_groups[] = {
4627 "usb1",
4628};
4629
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]4630static const char * const usb30_groups[] = {
4631 "usb30",
4632};
4633
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]4634static const struct sh_pfc_function pinmux_functions[] = {
Kuninori Morimoto60ffe392017-05-12 00:13:30 +0000[diff] [blame]4635 SH_PFC_FUNCTION(audio_clk),
Takeshi Kihara9c99a632016-03-16 11:44:19 +0900[diff] [blame]4636 SH_PFC_FUNCTION(avb),
Chris Patersoncf753412016-11-22 13:49:02 +0000[diff] [blame]4637 SH_PFC_FUNCTION(can0),
4638 SH_PFC_FUNCTION(can1),
4639 SH_PFC_FUNCTION(can_clk),
Chris Paterson3dc93dc2016-11-22 13:49:03 +0000[diff] [blame]4640 SH_PFC_FUNCTION(canfd0),
4641 SH_PFC_FUNCTION(canfd1),
Ramesh Shanmugasundaramfb082832016-10-13 10:29:14 +0100[diff] [blame]4642 SH_PFC_FUNCTION(drif0),
4643 SH_PFC_FUNCTION(drif1),
4644 SH_PFC_FUNCTION(drif2),
4645 SH_PFC_FUNCTION(drif3),
Niklas Söderlundcccc6182016-11-11 21:40:03 +0100[diff] [blame]4646 SH_PFC_FUNCTION(du),
Takeshi Kihara71c236a2018-02-16 15:25:42 +0100[diff] [blame^]4647 SH_PFC_FUNCTION(hdmi0),
Ulrich Hecht0e4e4992016-12-07 17:44:46 +0100[diff] [blame]4648 SH_PFC_FUNCTION(hscif0),
4649 SH_PFC_FUNCTION(hscif1),
4650 SH_PFC_FUNCTION(hscif2),
4651 SH_PFC_FUNCTION(hscif3),
4652 SH_PFC_FUNCTION(hscif4),
Ulrich Hecht02609a22016-09-14 18:46:08 +0200[diff] [blame]4653 SH_PFC_FUNCTION(i2c1),
4654 SH_PFC_FUNCTION(i2c2),
4655 SH_PFC_FUNCTION(i2c6),
Takeshi Kiharab0149122016-10-24 20:40:09 +0900[diff] [blame]4656 SH_PFC_FUNCTION(intc_ex),
Takeshi Kihara47532312016-03-16 12:22:06 +0900[diff] [blame]4657 SH_PFC_FUNCTION(msiof0),
4658 SH_PFC_FUNCTION(msiof1),
4659 SH_PFC_FUNCTION(msiof2),
4660 SH_PFC_FUNCTION(msiof3),
Takeshi Kihara332cb222017-04-19 15:24:49 +0200[diff] [blame]4661 SH_PFC_FUNCTION(pwm0),
4662 SH_PFC_FUNCTION(pwm1),
4663 SH_PFC_FUNCTION(pwm2),
4664 SH_PFC_FUNCTION(pwm3),
4665 SH_PFC_FUNCTION(pwm4),
4666 SH_PFC_FUNCTION(pwm5),
4667 SH_PFC_FUNCTION(pwm6),
Takeshi Kiharafc43d8b2016-08-18 15:12:33 +0200[diff] [blame]4668 SH_PFC_FUNCTION(scif0),
4669 SH_PFC_FUNCTION(scif1),
4670 SH_PFC_FUNCTION(scif2),
4671 SH_PFC_FUNCTION(scif3),
4672 SH_PFC_FUNCTION(scif4),
4673 SH_PFC_FUNCTION(scif5),
4674 SH_PFC_FUNCTION(scif_clk),
Takeshi Kihara374cf692016-08-17 13:31:52 +0200[diff] [blame]4675 SH_PFC_FUNCTION(sdhi0),
4676 SH_PFC_FUNCTION(sdhi1),
4677 SH_PFC_FUNCTION(sdhi2),
4678 SH_PFC_FUNCTION(sdhi3),
Kuninori Morimoto4fe12382017-05-12 00:13:05 +0000[diff] [blame]4679 SH_PFC_FUNCTION(ssi),
Takeshi Kiharaa8d276e2017-08-02 21:51:09 +0900[diff] [blame]4680 SH_PFC_FUNCTION(usb0),
4681 SH_PFC_FUNCTION(usb1),
Takeshi Kihara656285a2017-08-02 21:51:10 +0900[diff] [blame]4682 SH_PFC_FUNCTION(usb30),
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]4683};
4684
4685static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4686#define F_(x, y) FN_##y
4687#define FM(x) FN_##x
4688 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4689 0, 0,
4690 0, 0,
4691 0, 0,
4692 0, 0,
4693 0, 0,
4694 0, 0,
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 GP_0_15_FN, GPSR0_15,
4706 GP_0_14_FN, GPSR0_14,
4707 GP_0_13_FN, GPSR0_13,
4708 GP_0_12_FN, GPSR0_12,
4709 GP_0_11_FN, GPSR0_11,
4710 GP_0_10_FN, GPSR0_10,
4711 GP_0_9_FN, GPSR0_9,
4712 GP_0_8_FN, GPSR0_8,
4713 GP_0_7_FN, GPSR0_7,
4714 GP_0_6_FN, GPSR0_6,
4715 GP_0_5_FN, GPSR0_5,
4716 GP_0_4_FN, GPSR0_4,
4717 GP_0_3_FN, GPSR0_3,
4718 GP_0_2_FN, GPSR0_2,
4719 GP_0_1_FN, GPSR0_1,
4720 GP_0_0_FN, GPSR0_0, }
4721 },
4722 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4723 0, 0,
4724 0, 0,
4725 0, 0,
4726 GP_1_28_FN, GPSR1_28,
4727 GP_1_27_FN, GPSR1_27,
4728 GP_1_26_FN, GPSR1_26,
4729 GP_1_25_FN, GPSR1_25,
4730 GP_1_24_FN, GPSR1_24,
4731 GP_1_23_FN, GPSR1_23,
4732 GP_1_22_FN, GPSR1_22,
4733 GP_1_21_FN, GPSR1_21,
4734 GP_1_20_FN, GPSR1_20,
4735 GP_1_19_FN, GPSR1_19,
4736 GP_1_18_FN, GPSR1_18,
4737 GP_1_17_FN, GPSR1_17,
4738 GP_1_16_FN, GPSR1_16,
4739 GP_1_15_FN, GPSR1_15,
4740 GP_1_14_FN, GPSR1_14,
4741 GP_1_13_FN, GPSR1_13,
4742 GP_1_12_FN, GPSR1_12,
4743 GP_1_11_FN, GPSR1_11,
4744 GP_1_10_FN, GPSR1_10,
4745 GP_1_9_FN, GPSR1_9,
4746 GP_1_8_FN, GPSR1_8,
4747 GP_1_7_FN, GPSR1_7,
4748 GP_1_6_FN, GPSR1_6,
4749 GP_1_5_FN, GPSR1_5,
4750 GP_1_4_FN, GPSR1_4,
4751 GP_1_3_FN, GPSR1_3,
4752 GP_1_2_FN, GPSR1_2,
4753 GP_1_1_FN, GPSR1_1,
4754 GP_1_0_FN, GPSR1_0, }
4755 },
4756 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4757 0, 0,
4758 0, 0,
4759 0, 0,
4760 0, 0,
4761 0, 0,
4762 0, 0,
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 0, 0,
4769 0, 0,
4770 0, 0,
4771 0, 0,
4772 0, 0,
4773 0, 0,
4774 GP_2_14_FN, GPSR2_14,
4775 GP_2_13_FN, GPSR2_13,
4776 GP_2_12_FN, GPSR2_12,
4777 GP_2_11_FN, GPSR2_11,
4778 GP_2_10_FN, GPSR2_10,
4779 GP_2_9_FN, GPSR2_9,
4780 GP_2_8_FN, GPSR2_8,
4781 GP_2_7_FN, GPSR2_7,
4782 GP_2_6_FN, GPSR2_6,
4783 GP_2_5_FN, GPSR2_5,
4784 GP_2_4_FN, GPSR2_4,
4785 GP_2_3_FN, GPSR2_3,
4786 GP_2_2_FN, GPSR2_2,
4787 GP_2_1_FN, GPSR2_1,
4788 GP_2_0_FN, GPSR2_0, }
4789 },
4790 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4791 0, 0,
4792 0, 0,
4793 0, 0,
4794 0, 0,
4795 0, 0,
4796 0, 0,
4797 0, 0,
4798 0, 0,
4799 0, 0,
4800 0, 0,
4801 0, 0,
4802 0, 0,
4803 0, 0,
4804 0, 0,
4805 0, 0,
4806 0, 0,
4807 GP_3_15_FN, GPSR3_15,
4808 GP_3_14_FN, GPSR3_14,
4809 GP_3_13_FN, GPSR3_13,
4810 GP_3_12_FN, GPSR3_12,
4811 GP_3_11_FN, GPSR3_11,
4812 GP_3_10_FN, GPSR3_10,
4813 GP_3_9_FN, GPSR3_9,
4814 GP_3_8_FN, GPSR3_8,
4815 GP_3_7_FN, GPSR3_7,
4816 GP_3_6_FN, GPSR3_6,
4817 GP_3_5_FN, GPSR3_5,
4818 GP_3_4_FN, GPSR3_4,
4819 GP_3_3_FN, GPSR3_3,
4820 GP_3_2_FN, GPSR3_2,
4821 GP_3_1_FN, GPSR3_1,
4822 GP_3_0_FN, GPSR3_0, }
4823 },
4824 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4825 0, 0,
4826 0, 0,
4827 0, 0,
4828 0, 0,
4829 0, 0,
4830 0, 0,
4831 0, 0,
4832 0, 0,
4833 0, 0,
4834 0, 0,
4835 0, 0,
4836 0, 0,
4837 0, 0,
4838 0, 0,
4839 GP_4_17_FN, GPSR4_17,
4840 GP_4_16_FN, GPSR4_16,
4841 GP_4_15_FN, GPSR4_15,
4842 GP_4_14_FN, GPSR4_14,
4843 GP_4_13_FN, GPSR4_13,
4844 GP_4_12_FN, GPSR4_12,
4845 GP_4_11_FN, GPSR4_11,
4846 GP_4_10_FN, GPSR4_10,
4847 GP_4_9_FN, GPSR4_9,
4848 GP_4_8_FN, GPSR4_8,
4849 GP_4_7_FN, GPSR4_7,
4850 GP_4_6_FN, GPSR4_6,
4851 GP_4_5_FN, GPSR4_5,
4852 GP_4_4_FN, GPSR4_4,
4853 GP_4_3_FN, GPSR4_3,
4854 GP_4_2_FN, GPSR4_2,
4855 GP_4_1_FN, GPSR4_1,
4856 GP_4_0_FN, GPSR4_0, }
4857 },
4858 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4859 0, 0,
4860 0, 0,
4861 0, 0,
4862 0, 0,
4863 0, 0,
4864 0, 0,
4865 GP_5_25_FN, GPSR5_25,
4866 GP_5_24_FN, GPSR5_24,
4867 GP_5_23_FN, GPSR5_23,
4868 GP_5_22_FN, GPSR5_22,
4869 GP_5_21_FN, GPSR5_21,
4870 GP_5_20_FN, GPSR5_20,
4871 GP_5_19_FN, GPSR5_19,
4872 GP_5_18_FN, GPSR5_18,
4873 GP_5_17_FN, GPSR5_17,
4874 GP_5_16_FN, GPSR5_16,
4875 GP_5_15_FN, GPSR5_15,
4876 GP_5_14_FN, GPSR5_14,
4877 GP_5_13_FN, GPSR5_13,
4878 GP_5_12_FN, GPSR5_12,
4879 GP_5_11_FN, GPSR5_11,
4880 GP_5_10_FN, GPSR5_10,
4881 GP_5_9_FN, GPSR5_9,
4882 GP_5_8_FN, GPSR5_8,
4883 GP_5_7_FN, GPSR5_7,
4884 GP_5_6_FN, GPSR5_6,
4885 GP_5_5_FN, GPSR5_5,
4886 GP_5_4_FN, GPSR5_4,
4887 GP_5_3_FN, GPSR5_3,
4888 GP_5_2_FN, GPSR5_2,
4889 GP_5_1_FN, GPSR5_1,
4890 GP_5_0_FN, GPSR5_0, }
4891 },
4892 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4893 GP_6_31_FN, GPSR6_31,
4894 GP_6_30_FN, GPSR6_30,
4895 GP_6_29_FN, GPSR6_29,
4896 GP_6_28_FN, GPSR6_28,
4897 GP_6_27_FN, GPSR6_27,
4898 GP_6_26_FN, GPSR6_26,
4899 GP_6_25_FN, GPSR6_25,
4900 GP_6_24_FN, GPSR6_24,
4901 GP_6_23_FN, GPSR6_23,
4902 GP_6_22_FN, GPSR6_22,
4903 GP_6_21_FN, GPSR6_21,
4904 GP_6_20_FN, GPSR6_20,
4905 GP_6_19_FN, GPSR6_19,
4906 GP_6_18_FN, GPSR6_18,
4907 GP_6_17_FN, GPSR6_17,
4908 GP_6_16_FN, GPSR6_16,
4909 GP_6_15_FN, GPSR6_15,
4910 GP_6_14_FN, GPSR6_14,
4911 GP_6_13_FN, GPSR6_13,
4912 GP_6_12_FN, GPSR6_12,
4913 GP_6_11_FN, GPSR6_11,
4914 GP_6_10_FN, GPSR6_10,
4915 GP_6_9_FN, GPSR6_9,
4916 GP_6_8_FN, GPSR6_8,
4917 GP_6_7_FN, GPSR6_7,
4918 GP_6_6_FN, GPSR6_6,
4919 GP_6_5_FN, GPSR6_5,
4920 GP_6_4_FN, GPSR6_4,
4921 GP_6_3_FN, GPSR6_3,
4922 GP_6_2_FN, GPSR6_2,
4923 GP_6_1_FN, GPSR6_1,
4924 GP_6_0_FN, GPSR6_0, }
4925 },
4926 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4927 0, 0,
4928 0, 0,
4929 0, 0,
4930 0, 0,
4931 0, 0,
4932 0, 0,
4933 0, 0,
4934 0, 0,
4935 0, 0,
4936 0, 0,
4937 0, 0,
4938 0, 0,
4939 0, 0,
4940 0, 0,
4941 0, 0,
4942 0, 0,
4943 0, 0,
4944 0, 0,
4945 0, 0,
4946 0, 0,
4947 0, 0,
4948 0, 0,
4949 0, 0,
4950 0, 0,
4951 0, 0,
4952 0, 0,
4953 0, 0,
4954 0, 0,
4955 GP_7_3_FN, GPSR7_3,
4956 GP_7_2_FN, GPSR7_2,
4957 GP_7_1_FN, GPSR7_1,
4958 GP_7_0_FN, GPSR7_0, }
4959 },
4960#undef F_
4961#undef FM
4962
4963#define F_(x, y) x,
4964#define FM(x) FN_##x,
4965 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4966 IP0_31_28
4967 IP0_27_24
4968 IP0_23_20
4969 IP0_19_16
4970 IP0_15_12
4971 IP0_11_8
4972 IP0_7_4
4973 IP0_3_0 }
4974 },
4975 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4976 IP1_31_28
4977 IP1_27_24
4978 IP1_23_20
4979 IP1_19_16
4980 IP1_15_12
4981 IP1_11_8
4982 IP1_7_4
4983 IP1_3_0 }
4984 },
4985 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4986 IP2_31_28
4987 IP2_27_24
4988 IP2_23_20
4989 IP2_19_16
4990 IP2_15_12
4991 IP2_11_8
4992 IP2_7_4
4993 IP2_3_0 }
4994 },
4995 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4996 IP3_31_28
4997 IP3_27_24
4998 IP3_23_20
4999 IP3_19_16
5000 IP3_15_12
5001 IP3_11_8
5002 IP3_7_4
5003 IP3_3_0 }
5004 },
5005 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5006 IP4_31_28
5007 IP4_27_24
5008 IP4_23_20
5009 IP4_19_16
5010 IP4_15_12
5011 IP4_11_8
5012 IP4_7_4
5013 IP4_3_0 }
5014 },
5015 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5016 IP5_31_28
5017 IP5_27_24
5018 IP5_23_20
5019 IP5_19_16
5020 IP5_15_12
5021 IP5_11_8
5022 IP5_7_4
5023 IP5_3_0 }
5024 },
5025 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5026 IP6_31_28
5027 IP6_27_24
5028 IP6_23_20
5029 IP6_19_16
5030 IP6_15_12
5031 IP6_11_8
5032 IP6_7_4
5033 IP6_3_0 }
5034 },
5035 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5036 IP7_31_28
5037 IP7_27_24
5038 IP7_23_20
5039 IP7_19_16
Takeshi Kihara89217782017-07-13 01:55:43 +0900[diff] [blame]5040 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5041 IP7_11_8
5042 IP7_7_4
5043 IP7_3_0 }
5044 },
5045 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5046 IP8_31_28
5047 IP8_27_24
5048 IP8_23_20
5049 IP8_19_16
5050 IP8_15_12
5051 IP8_11_8
5052 IP8_7_4
5053 IP8_3_0 }
5054 },
5055 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5056 IP9_31_28
5057 IP9_27_24
5058 IP9_23_20
5059 IP9_19_16
5060 IP9_15_12
5061 IP9_11_8
5062 IP9_7_4
5063 IP9_3_0 }
5064 },
5065 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5066 IP10_31_28
5067 IP10_27_24
5068 IP10_23_20
5069 IP10_19_16
5070 IP10_15_12
5071 IP10_11_8
5072 IP10_7_4
5073 IP10_3_0 }
5074 },
5075 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5076 IP11_31_28
5077 IP11_27_24
5078 IP11_23_20
5079 IP11_19_16
5080 IP11_15_12
5081 IP11_11_8
5082 IP11_7_4
5083 IP11_3_0 }
5084 },
5085 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5086 IP12_31_28
5087 IP12_27_24
5088 IP12_23_20
5089 IP12_19_16
5090 IP12_15_12
5091 IP12_11_8
5092 IP12_7_4
5093 IP12_3_0 }
5094 },
5095 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5096 IP13_31_28
5097 IP13_27_24
5098 IP13_23_20
5099 IP13_19_16
5100 IP13_15_12
5101 IP13_11_8
5102 IP13_7_4
5103 IP13_3_0 }
5104 },
5105 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5106 IP14_31_28
5107 IP14_27_24
5108 IP14_23_20
5109 IP14_19_16
5110 IP14_15_12
5111 IP14_11_8
5112 IP14_7_4
5113 IP14_3_0 }
5114 },
5115 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5116 IP15_31_28
5117 IP15_27_24
5118 IP15_23_20
5119 IP15_19_16
5120 IP15_15_12
5121 IP15_11_8
5122 IP15_7_4
5123 IP15_3_0 }
5124 },
5125 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5126 IP16_31_28
5127 IP16_27_24
5128 IP16_23_20
5129 IP16_19_16
5130 IP16_15_12
5131 IP16_11_8
5132 IP16_7_4
5133 IP16_3_0 }
5134 },
5135 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5136 IP17_31_28
5137 IP17_27_24
5138 IP17_23_20
5139 IP17_19_16
5140 IP17_15_12
5141 IP17_11_8
5142 IP17_7_4
5143 IP17_3_0 }
5144 },
5145 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5146 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5147 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5148 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5149 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5150 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5151 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5152 IP18_7_4
5153 IP18_3_0 }
5154 },
5155#undef F_
5156#undef FM
5157
5158#define F_(x, y) x,
5159#define FM(x) FN_##x,
5160 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5161 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5162 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5163 MOD_SEL0_31_30_29
5164 MOD_SEL0_28_27
5165 MOD_SEL0_26_25_24
5166 MOD_SEL0_23
5167 MOD_SEL0_22
5168 MOD_SEL0_21
5169 MOD_SEL0_20
5170 MOD_SEL0_19
5171 MOD_SEL0_18_17
5172 MOD_SEL0_16
Takeshi Kihara78864ed2017-07-13 01:55:46 +0900[diff] [blame]5173 0, 0, /* RESERVED 15 */
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5174 MOD_SEL0_14_13
5175 MOD_SEL0_12
5176 MOD_SEL0_11
5177 MOD_SEL0_10
5178 MOD_SEL0_9_8
5179 MOD_SEL0_7_6
5180 MOD_SEL0_5
5181 MOD_SEL0_4_3
5182 /* RESERVED 2, 1, 0 */
5183 0, 0, 0, 0, 0, 0, 0, 0 }
5184 },
5185 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5186 2, 3, 1, 2, 3, 1, 1, 2, 1,
5187 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5188 MOD_SEL1_31_30
5189 MOD_SEL1_29_28_27
5190 MOD_SEL1_26
5191 MOD_SEL1_25_24
5192 MOD_SEL1_23_22_21
5193 MOD_SEL1_20
5194 MOD_SEL1_19
5195 MOD_SEL1_18_17
5196 MOD_SEL1_16
5197 MOD_SEL1_15_14
5198 MOD_SEL1_13
5199 MOD_SEL1_12
5200 MOD_SEL1_11
5201 MOD_SEL1_10
5202 MOD_SEL1_9
5203 0, 0, 0, 0, /* RESERVED 8, 7 */
5204 MOD_SEL1_6
5205 MOD_SEL1_5
5206 MOD_SEL1_4
5207 MOD_SEL1_3
5208 MOD_SEL1_2
5209 MOD_SEL1_1
5210 MOD_SEL1_0 }
5211 },
5212 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5213 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5214 4, 4, 4, 3, 1) {
5215 MOD_SEL2_31
5216 MOD_SEL2_30
5217 MOD_SEL2_29
5218 MOD_SEL2_28_27
5219 MOD_SEL2_26
5220 MOD_SEL2_25_24_23
5221 MOD_SEL2_22
5222 MOD_SEL2_21
5223 MOD_SEL2_20
5224 MOD_SEL2_19
5225 MOD_SEL2_18
5226 MOD_SEL2_17
5227 /* RESERVED 16 */
5228 0, 0,
5229 /* RESERVED 15, 14, 13, 12 */
5230 0, 0, 0, 0, 0, 0, 0, 0,
5231 0, 0, 0, 0, 0, 0, 0, 0,
5232 /* RESERVED 11, 10, 9, 8 */
5233 0, 0, 0, 0, 0, 0, 0, 0,
5234 0, 0, 0, 0, 0, 0, 0, 0,
5235 /* RESERVED 7, 6, 5, 4 */
5236 0, 0, 0, 0, 0, 0, 0, 0,
5237 0, 0, 0, 0, 0, 0, 0, 0,
5238 /* RESERVED 3, 2, 1 */
5239 0, 0, 0, 0, 0, 0, 0, 0,
5240 MOD_SEL2_0 }
5241 },
5242 { },
5243};
5244
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5245static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5246 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5247 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5248 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5249 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5250 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5251 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5252 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5253 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5254 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5255 } },
5256 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5257 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5258 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5259 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5260 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5261 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5262 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5263 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5264 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5265 } },
5266 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5267 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5268 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5269 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5270 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5271 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5272 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5273 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5274 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5275 } },
5276 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5277 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5278 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5279 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5280 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5281 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5282 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5283 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5284 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5285 } },
5286 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5287 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5288 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5289 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5290 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5291 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5292 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5293 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5294 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5295 } },
5296 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5297 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5298 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5299 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5300 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5301 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5302 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5303 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5304 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5305 } },
5306 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5307 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5308 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5309 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5310 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5311 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5312 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5313 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5314 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5315 } },
5316 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5317 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5318 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5319 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5320 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5321 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5322 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5323 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5324 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5325 } },
5326 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5327 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5328 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5329 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5330 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5331 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5332 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5333 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5334 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5335 } },
5336 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5337 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5338 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5339 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5340 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5341 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5342 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5343 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5344 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5345 } },
5346 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5347 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5348 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5349 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5350 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5351 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5352 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5353 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5354 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5355 } },
5356 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5357 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5358 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5359 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5360 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5361 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5362 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5363 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5364 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5365 } },
5366 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5367 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5368 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5369 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5370 } },
5371 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5372 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5373 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5374 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5375 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5376 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5377 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5378 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5379 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5380 } },
5381 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5382 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5383 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5384 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5385 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5386 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5387 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5388 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5389 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5390 } },
5391 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5392 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5393 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5394 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5395 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5396 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5397 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5398 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5399 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5400 } },
5401 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5402 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5403 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5404 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5405 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5406 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5407 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5408 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5409 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5410 } },
5411 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5412 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5413 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5414 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5415 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5416 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5417 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5418 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5419 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5420 } },
5421 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5422 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5423 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5424 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5425 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5426 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5427 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5428 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5429 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5430 } },
5431 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5432 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5433 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5434 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5435 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5436 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5437 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5438 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5439 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5440 } },
5441 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5442 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5443 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5444 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5445 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5446 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5447 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5448 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5449 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5450 } },
5451 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5452 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5453 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5454 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5455 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
Kuninori Morimoto07073b82017-05-16 08:42:36 +0000[diff] [blame]5456 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5457 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5458 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5459 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5460 } },
5461 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5462 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5463 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5464 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5465 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5466 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5467 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5468 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5469 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5470 } },
5471 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5472 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5473 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5474 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5475 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5476 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5477 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5478 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5479 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5480 } },
5481 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5482 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5483 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5484 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5485 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5486 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5487 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5488 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5489 } },
5490 { },
5491};
5492
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]5493enum ioctrl_regs {
5494 POCCTRL,
5495};
5496
5497static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5498 [POCCTRL] = { 0xe6060380, },
5499 { /* sentinel */ },
5500};
5501
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5502static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5503{
5504 int bit = -EINVAL;
5505
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]5506 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5507
5508 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5509 bit = pin & 0x1f;
5510
5511 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5512 bit = (pin & 0x1f) + 12;
5513
5514 return bit;
5515}
5516
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5517static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5518 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5519 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5520 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5521 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5522 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5523 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5524 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5525 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5526 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5527 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5528 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5529 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5530 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5531 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5532 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5533 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5534 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5535 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5536 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5537 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5538 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5539 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5540 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5541 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5542 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5543 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5544 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5545 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5546 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5547 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5548 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5549 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5550 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5551 } },
5552 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5553 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5554 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5555 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5556 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5557 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5558 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5559 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5560 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5561 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5562 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5563 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5564 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5565 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5566 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5567 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5568 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5569 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5570 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5571 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5572 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5573 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5574 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5575 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5576 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5577 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5578 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5579 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5580 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5581 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5582 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5583 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5584 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5585 } },
5586 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5587 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5588 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5589 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5590 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5591 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5592 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5593 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5594 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5595 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5596 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5597 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5598 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5599 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5600 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5601 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5602 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5603 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5604 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5605 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5606 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5607 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5608 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5609 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5610 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5611 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5612 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5613 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5614 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5615 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5616 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5617 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5618 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5619 } },
5620 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5621 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5622 [ 1] = PIN_NONE,
5623 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5624 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5625 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5626 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5627 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5628 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5629 [ 8] = PIN_NONE,
5630 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5631 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5632 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5633 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5634 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5635 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5636 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5637 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5638 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5639 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5640 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5641 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5642 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5643 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5644 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5645 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5646 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5647 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5648 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5649 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5650 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5651 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5652 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5653 } },
5654 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5655 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5656 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5657 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5658 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5659 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5660 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5661 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5662 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5663 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5664 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5665 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5666 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5667 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5668 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5669 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5670 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5671 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5672 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5673 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5674 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
Takeshi Kihara0f4713d2017-11-16 23:59:21 +0900[diff] [blame]5675 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5676 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5677 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5678 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5679 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5680 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5681 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5682 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5683 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5684 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5685 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5686 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5687 } },
5688 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5689 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5690 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5691 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5692 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5693 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5694 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5695 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5696 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5697 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5698 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5699 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5700 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5701 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5702 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5703 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5704 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5705 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5706 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5707 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5708 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5709 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5710 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5711 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5712 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5713 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5714 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5715 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5716 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5717 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5718 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5719 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5720 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5721 } },
5722 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5723 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5724 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5725 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5726 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5727 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5728 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
5729 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
5730 [ 7] = PIN_NONE,
5731 [ 8] = PIN_NONE,
5732 [ 9] = PIN_NONE,
5733 [10] = PIN_NONE,
5734 [11] = PIN_NONE,
5735 [12] = PIN_NONE,
5736 [13] = PIN_NONE,
5737 [14] = PIN_NONE,
5738 [15] = PIN_NONE,
5739 [16] = PIN_NONE,
5740 [17] = PIN_NONE,
5741 [18] = PIN_NONE,
5742 [19] = PIN_NONE,
5743 [20] = PIN_NONE,
5744 [21] = PIN_NONE,
5745 [22] = PIN_NONE,
5746 [23] = PIN_NONE,
5747 [24] = PIN_NONE,
5748 [25] = PIN_NONE,
5749 [26] = PIN_NONE,
5750 [27] = PIN_NONE,
5751 [28] = PIN_NONE,
5752 [29] = PIN_NONE,
5753 [30] = PIN_NONE,
5754 [31] = PIN_NONE,
5755 } },
5756 { /* sentinel */ },
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5757};
5758
5759static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5760 unsigned int pin)
5761{
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5762 const struct pinmux_bias_reg *reg;
5763 unsigned int bit;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5764
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5765 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5766 if (!reg)
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5767 return PIN_CONFIG_BIAS_DISABLE;
5768
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5769 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5770 return PIN_CONFIG_BIAS_DISABLE;
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5771 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5772 return PIN_CONFIG_BIAS_PULL_UP;
5773 else
5774 return PIN_CONFIG_BIAS_PULL_DOWN;
5775}
5776
5777static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5778 unsigned int bias)
5779{
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5780 const struct pinmux_bias_reg *reg;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5781 u32 enable, updown;
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5782 unsigned int bit;
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5783
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5784 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5785 if (!reg)
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5786 return;
5787
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5788 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5789 if (bias != PIN_CONFIG_BIAS_DISABLE)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5790 enable |= BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5791
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5792 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5793 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5794 updown |= BIT(bit);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5795
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5796 sh_pfc_write(pfc, reg->pud, updown);
5797 sh_pfc_write(pfc, reg->puen, enable);
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5798}
5799
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5800static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5801 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
Niklas Söderlund2d40bd22016-11-17 16:09:20 +0100[diff] [blame]5802 .get_bias = r8a7796_pinmux_get_bias,
5803 .set_bias = r8a7796_pinmux_set_bias,
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5804};
5805
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5806const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5807 .name = "r8a77960_pfc",
Simon Hormanc5901bd2016-09-08 13:57:33 +0200[diff] [blame]5808 .ops = &r8a7796_pinmux_ops,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5809 .unlock_reg = 0xe6060000, /* PMMR */
5810
5811 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5812
5813 .pins = pinmux_pins,
5814 .nr_pins = ARRAY_SIZE(pinmux_pins),
5815 .groups = pinmux_groups,
5816 .nr_groups = ARRAY_SIZE(pinmux_groups),
5817 .functions = pinmux_functions,
5818 .nr_functions = ARRAY_SIZE(pinmux_functions),
5819
5820 .cfg_regs = pinmux_config_regs,
Niklas Söderlund9e35d6f2016-11-17 16:09:19 +0100[diff] [blame]5821 .drive_regs = pinmux_drive_regs,
Geert Uytterhoeven58668a62017-09-29 14:14:29 +0200[diff] [blame]5822 .bias_regs = pinmux_bias_regs,
Geert Uytterhoeven3870a6f2017-09-29 14:15:17 +0200[diff] [blame]5823 .ioctrl_regs = pinmux_ioctrl_regs,
Takeshi Kiharaf9aece72016-08-18 15:12:32 +0200[diff] [blame]5824
5825 .pinmux_data = pinmux_data,
5826 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5827};