blob: 8cdb610561ba81f34f1f34aeb4f314b573cb34d8 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Peter Ujfalusia18301b2018-03-21 12:20:26 +020041 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010042 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Peter Ujfalusia18301b2018-03-21 12:20:26 +020045 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010046}
47
Thierry Reding31b02ca2017-10-12 17:40:46 +020048static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010049 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053050#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010051 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010052#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020054 .atomic_commit = drm_atomic_helper_commit,
55};
56
Thierry Redingc4755fb2017-11-13 11:08:13 +010057static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
58{
59 struct drm_device *drm = old_state->dev;
60 struct tegra_drm *tegra = drm->dev_private;
61
62 if (tegra->hub) {
63 drm_atomic_helper_commit_modeset_disables(drm, old_state);
64 tegra_display_hub_atomic_commit(drm, old_state);
65 drm_atomic_helper_commit_planes(drm, old_state, 0);
66 drm_atomic_helper_commit_modeset_enables(drm, old_state);
67 drm_atomic_helper_commit_hw_done(old_state);
68 drm_atomic_helper_wait_for_vblanks(drm, old_state);
69 drm_atomic_helper_cleanup_planes(drm, old_state);
70 } else {
71 drm_atomic_helper_commit_tail_rpm(old_state);
72 }
73}
74
Thierry Reding31b02ca2017-10-12 17:40:46 +020075static const struct drm_mode_config_helper_funcs
76tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010077 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010078};
79
Thierry Reding776dc382013-10-14 14:43:22 +020080static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000081{
Thierry Reding776dc382013-10-14 14:43:22 +020082 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020083 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000084 int err;
85
Thierry Reding776dc382013-10-14 14:43:22 +020086 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020087 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020088 return -ENOMEM;
89
Thierry Redingdf06b752014-06-26 21:41:53 +020090 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +020091 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +010092 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +020093 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +010094
Thierry Redingdf06b752014-06-26 21:41:53 +020095 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +030096 if (!tegra->domain) {
97 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +020098 goto free;
99 }
100
Thierry Reding24cfdc12018-04-23 08:57:45 +0200101 err = iova_cache_get();
102 if (err < 0)
103 goto domain;
104
Thierry Reding4553f732015-01-19 16:15:04 +0100105 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200106 gem_start = geometry->aperture_start;
107 gem_end = geometry->aperture_end - CARVEOUT_SZ;
108 carveout_start = gem_end + 1;
109 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100110
Mikko Perttunenad926012016-12-14 13:16:11 +0200111 order = __ffs(tegra->domain->pgsize_bitmap);
112 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100113 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200114
115 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
116 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
117
118 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100119 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200120
121 DRM_DEBUG("IOMMU apertures:\n");
122 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
123 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
124 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200125 }
126
Thierry Reding386a2a72013-09-24 13:22:17 +0200127 mutex_init(&tegra->clients_lock);
128 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100129
Thierry Reding386a2a72013-09-24 13:22:17 +0200130 drm->dev_private = tegra;
131 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000132
133 drm_mode_config_init(drm);
134
Thierry Redingf9914212014-11-26 13:03:57 +0100135 drm->mode_config.min_width = 0;
136 drm->mode_config.min_height = 0;
137
138 drm->mode_config.max_width = 4096;
139 drm->mode_config.max_height = 4096;
140
Alexandre Courbot5e911442016-11-08 16:50:42 +0900141 drm->mode_config.allow_fb_modifiers = true;
142
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200143 drm->mode_config.normalize_zpos = true;
144
Thierry Reding31b02ca2017-10-12 17:40:46 +0200145 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
146 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100147
Thierry Redinge2215321f2014-06-27 17:19:25 +0200148 err = tegra_drm_fb_prepare(drm);
149 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100150 goto config;
Thierry Redinge2215321f2014-06-27 17:19:25 +0200151
152 drm_kms_helper_poll_init(drm);
153
Thierry Reding776dc382013-10-14 14:43:22 +0200154 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000155 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100156 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000157
Thierry Redingc4755fb2017-11-13 11:08:13 +0100158 if (tegra->hub) {
159 err = tegra_display_hub_prepare(tegra->hub);
160 if (err < 0)
161 goto device;
162 }
163
Thierry Reding603f0cc2013-04-22 21:22:14 +0200164 /*
165 * We don't use the drm_irq_install() helpers provided by the DRM
166 * core, so we need to set this manually in order to allow the
167 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
168 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300169 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200170
Thierry Reding42e9ce02015-01-28 14:43:05 +0100171 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100172 drm->max_vblank_count = 0xffffffff;
173
Thierry Reding6e5ff992012-11-28 11:45:47 +0100174 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
175 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100176 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100177
Thierry Reding31930d42015-07-02 17:04:06 +0200178 drm_mode_config_reset(drm);
179
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000180 err = tegra_drm_fb_init(drm);
181 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100182 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000183
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000184 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100185
Thierry Redingc4755fb2017-11-13 11:08:13 +0100186hub:
187 if (tegra->hub)
188 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100189device:
190 host1x_device_exit(device);
191fbdev:
192 drm_kms_helper_poll_fini(drm);
193 tegra_drm_fb_free(drm);
194config:
195 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200196
197 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100198 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200199 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200200 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200201 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200202 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200203domain:
204 if (tegra->domain)
205 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200206free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100207 kfree(tegra);
208 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000209}
210
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200211static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000212{
Thierry Reding776dc382013-10-14 14:43:22 +0200213 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200214 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200215 int err;
216
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217 drm_kms_helper_poll_fini(drm);
218 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100219 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200220 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221
Thierry Reding776dc382013-10-14 14:43:22 +0200222 err = host1x_device_exit(device);
223 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200224 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200225
Thierry Redingdf06b752014-06-26 21:41:53 +0200226 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100227 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200228 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200229 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200230 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200231 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200232 }
233
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100234 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000235}
236
237static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
238{
Thierry Reding08943e62013-09-26 16:08:18 +0200239 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200240
241 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
242 if (!fpriv)
243 return -ENOMEM;
244
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100245 idr_init(&fpriv->contexts);
246 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200247 filp->driver_priv = fpriv;
248
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000249 return 0;
250}
251
Thierry Redingc88c3632013-09-26 16:08:22 +0200252static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200253{
254 context->client->ops->close_channel(context);
255 kfree(context);
256}
257
Thierry Redingc40f0f12013-10-10 11:00:33 +0200258static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100259host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200260{
261 struct drm_gem_object *gem;
262 struct tegra_bo *bo;
263
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100264 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200265 if (!gem)
266 return NULL;
267
Thierry Redingc40f0f12013-10-10 11:00:33 +0200268 bo = to_tegra_bo(gem);
269 return &bo->base;
270}
271
Thierry Reding961e3be2014-06-10 10:25:00 +0200272static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
273 struct drm_tegra_reloc __user *src,
274 struct drm_device *drm,
275 struct drm_file *file)
276{
277 u32 cmdbuf, target;
278 int err;
279
280 err = get_user(cmdbuf, &src->cmdbuf.handle);
281 if (err < 0)
282 return err;
283
284 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
285 if (err < 0)
286 return err;
287
288 err = get_user(target, &src->target.handle);
289 if (err < 0)
290 return err;
291
David Ung31f40f82015-01-20 18:37:35 -0800292 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200293 if (err < 0)
294 return err;
295
296 err = get_user(dest->shift, &src->shift);
297 if (err < 0)
298 return err;
299
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100300 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200301 if (!dest->cmdbuf.bo)
302 return -ENOENT;
303
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100304 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200305 if (!dest->target.bo)
306 return -ENOENT;
307
308 return 0;
309}
310
Thierry Redingc40f0f12013-10-10 11:00:33 +0200311int tegra_drm_submit(struct tegra_drm_context *context,
312 struct drm_tegra_submit *args, struct drm_device *drm,
313 struct drm_file *file)
314{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200315 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200316 unsigned int num_cmdbufs = args->num_cmdbufs;
317 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300318 struct drm_tegra_cmdbuf __user *user_cmdbufs;
319 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300320 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200321 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300322 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200323 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300324 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200325 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200326 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200327 int err;
328
Mikko Perttunena176c672017-09-28 15:50:44 +0300329 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
330 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300331 user_syncpt = u64_to_user_ptr(args->syncpts);
332
Thierry Redingc40f0f12013-10-10 11:00:33 +0200333 /* We don't yet support other than one syncpt_incr struct per submit */
334 if (args->num_syncpts != 1)
335 return -EINVAL;
336
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300337 /* We don't yet support waitchks */
338 if (args->num_waitchks != 0)
339 return -EINVAL;
340
Thierry Redingc40f0f12013-10-10 11:00:33 +0200341 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200342 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200343 if (!job)
344 return -ENOMEM;
345
346 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200347 job->client = client;
348 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200349 job->serialize = true;
350
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200351 /*
352 * Track referenced BOs so that they can be unreferenced after the
353 * submission is complete.
354 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200355 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200356
357 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
358 if (!refs) {
359 err = -ENOMEM;
360 goto put;
361 }
362
363 /* reuse as an iterator later */
364 num_refs = 0;
365
Thierry Redingc40f0f12013-10-10 11:00:33 +0200366 while (num_cmdbufs) {
367 struct drm_tegra_cmdbuf cmdbuf;
368 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300369 struct tegra_bo *obj;
370 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200371
Mikko Perttunena176c672017-09-28 15:50:44 +0300372 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300373 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200374 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300375 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200376
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300377 /*
378 * The maximum number of CDMA gather fetches is 16383, a higher
379 * value means the words count is malformed.
380 */
381 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
382 err = -EINVAL;
383 goto fail;
384 }
385
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100386 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200387 if (!bo) {
388 err = -ENOENT;
389 goto fail;
390 }
391
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300392 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
393 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200394 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300395
396 /*
397 * Gather buffer base address must be 4-bytes aligned,
398 * unaligned offset is malformed and cause commands stream
399 * corruption on the buffer address relocation.
400 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300401 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300402 err = -EINVAL;
403 goto fail;
404 }
405
Thierry Redingc40f0f12013-10-10 11:00:33 +0200406 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
407 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300408 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200409 }
410
Thierry Reding961e3be2014-06-10 10:25:00 +0200411 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200412 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300413 struct host1x_reloc *reloc;
414 struct tegra_bo *obj;
415
Thierry Reding06490bb2018-05-16 16:58:44 +0200416 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300417 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200418 file);
419 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200420 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300421
Thierry Reding06490bb2018-05-16 16:58:44 +0200422 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300423 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200424 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300425
426 /*
427 * The unaligned cmdbuf offset will cause an unaligned write
428 * during of the relocations patching, corrupting the commands
429 * stream.
430 */
431 if (reloc->cmdbuf.offset & 3 ||
432 reloc->cmdbuf.offset >= obj->gem.size) {
433 err = -EINVAL;
434 goto fail;
435 }
436
437 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200438 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300439
440 if (reloc->target.offset >= obj->gem.size) {
441 err = -EINVAL;
442 goto fail;
443 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200444 }
445
Mikko Perttunena176c672017-09-28 15:50:44 +0300446 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300447 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200448 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300449 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200450
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300451 /* check whether syncpoint ID is valid */
452 sp = host1x_syncpt_get(host1x, syncpt.id);
453 if (!sp) {
454 err = -ENOENT;
455 goto fail;
456 }
457
Thierry Redingc40f0f12013-10-10 11:00:33 +0200458 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300459 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200460 job->syncpt_incrs = syncpt.incrs;
461 job->syncpt_id = syncpt.id;
462 job->timeout = 10000;
463
464 if (args->timeout && args->timeout < 10000)
465 job->timeout = args->timeout;
466
467 err = host1x_job_pin(job, context->client->base.dev);
468 if (err)
469 goto fail;
470
471 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200472 if (err) {
473 host1x_job_unpin(job);
474 goto fail;
475 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200476
477 args->fence = job->syncpt_end;
478
Thierry Redingc40f0f12013-10-10 11:00:33 +0200479fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200480 while (num_refs--)
481 drm_gem_object_put_unlocked(refs[num_refs]);
482
483 kfree(refs);
484
485put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200486 host1x_job_put(job);
487 return err;
488}
489
490
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200491#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200492static int tegra_gem_create(struct drm_device *drm, void *data,
493 struct drm_file *file)
494{
495 struct drm_tegra_gem_create *args = data;
496 struct tegra_bo *bo;
497
Thierry Reding773af772013-10-04 22:34:01 +0200498 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200499 &args->handle);
500 if (IS_ERR(bo))
501 return PTR_ERR(bo);
502
503 return 0;
504}
505
506static int tegra_gem_mmap(struct drm_device *drm, void *data,
507 struct drm_file *file)
508{
509 struct drm_tegra_gem_mmap *args = data;
510 struct drm_gem_object *gem;
511 struct tegra_bo *bo;
512
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100513 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200514 if (!gem)
515 return -EINVAL;
516
517 bo = to_tegra_bo(gem);
518
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200519 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200520
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300521 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200522
523 return 0;
524}
525
526static int tegra_syncpt_read(struct drm_device *drm, void *data,
527 struct drm_file *file)
528{
Thierry Reding776dc382013-10-14 14:43:22 +0200529 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200530 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200531 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200532
Thierry Reding776dc382013-10-14 14:43:22 +0200533 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200534 if (!sp)
535 return -EINVAL;
536
537 args->value = host1x_syncpt_read_min(sp);
538 return 0;
539}
540
541static int tegra_syncpt_incr(struct drm_device *drm, void *data,
542 struct drm_file *file)
543{
Thierry Reding776dc382013-10-14 14:43:22 +0200544 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200545 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200546 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200547
Thierry Reding776dc382013-10-14 14:43:22 +0200548 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200549 if (!sp)
550 return -EINVAL;
551
Arto Merilainenebae30b2013-05-29 13:26:08 +0300552 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553}
554
555static int tegra_syncpt_wait(struct drm_device *drm, void *data,
556 struct drm_file *file)
557{
Thierry Reding776dc382013-10-14 14:43:22 +0200558 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200559 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200560 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561
Thierry Reding776dc382013-10-14 14:43:22 +0200562 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563 if (!sp)
564 return -EINVAL;
565
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300566 return host1x_syncpt_wait(sp, args->thresh,
567 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200568 &args->value);
569}
570
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100571static int tegra_client_open(struct tegra_drm_file *fpriv,
572 struct tegra_drm_client *client,
573 struct tegra_drm_context *context)
574{
575 int err;
576
577 err = client->ops->open_channel(client, context);
578 if (err < 0)
579 return err;
580
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300581 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100582 if (err < 0) {
583 client->ops->close_channel(context);
584 return err;
585 }
586
587 context->client = client;
588 context->id = err;
589
590 return 0;
591}
592
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200593static int tegra_open_channel(struct drm_device *drm, void *data,
594 struct drm_file *file)
595{
Thierry Reding08943e62013-09-26 16:08:18 +0200596 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200597 struct tegra_drm *tegra = drm->dev_private;
598 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200599 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200600 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200601 int err = -ENODEV;
602
603 context = kzalloc(sizeof(*context), GFP_KERNEL);
604 if (!context)
605 return -ENOMEM;
606
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100607 mutex_lock(&fpriv->lock);
608
Thierry Reding776dc382013-10-14 14:43:22 +0200609 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200610 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100611 err = tegra_client_open(fpriv, client, context);
612 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200613 break;
614
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100615 args->context = context->id;
616 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617 }
618
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100619 if (err < 0)
620 kfree(context);
621
622 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623 return err;
624}
625
626static int tegra_close_channel(struct drm_device *drm, void *data,
627 struct drm_file *file)
628{
Thierry Reding08943e62013-09-26 16:08:18 +0200629 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200630 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200631 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100632 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200633
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100634 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200635
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300636 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100637 if (!context) {
638 err = -EINVAL;
639 goto unlock;
640 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200641
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100642 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200643 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200644
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100645unlock:
646 mutex_unlock(&fpriv->lock);
647 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200648}
649
650static int tegra_get_syncpt(struct drm_device *drm, void *data,
651 struct drm_file *file)
652{
Thierry Reding08943e62013-09-26 16:08:18 +0200653 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200654 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200655 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200656 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100657 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200658
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100659 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200660
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300661 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100662 if (!context) {
663 err = -ENODEV;
664 goto unlock;
665 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200666
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100667 if (args->index >= context->client->base.num_syncpts) {
668 err = -EINVAL;
669 goto unlock;
670 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200671
Thierry Reding53fa7f72013-09-24 15:35:40 +0200672 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200673 args->id = host1x_syncpt_id(syncpt);
674
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100675unlock:
676 mutex_unlock(&fpriv->lock);
677 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200678}
679
680static int tegra_submit(struct drm_device *drm, void *data,
681 struct drm_file *file)
682{
Thierry Reding08943e62013-09-26 16:08:18 +0200683 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200684 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200685 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100686 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200687
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100688 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200689
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300690 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100691 if (!context) {
692 err = -ENODEV;
693 goto unlock;
694 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200695
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100696 err = context->client->ops->submit(context, args, drm, file);
697
698unlock:
699 mutex_unlock(&fpriv->lock);
700 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200701}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300702
703static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
704 struct drm_file *file)
705{
706 struct tegra_drm_file *fpriv = file->driver_priv;
707 struct drm_tegra_get_syncpt_base *args = data;
708 struct tegra_drm_context *context;
709 struct host1x_syncpt_base *base;
710 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300712
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100713 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300714
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300715 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100716 if (!context) {
717 err = -ENODEV;
718 goto unlock;
719 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300720
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100721 if (args->syncpt >= context->client->base.num_syncpts) {
722 err = -EINVAL;
723 goto unlock;
724 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300725
726 syncpt = context->client->base.syncpts[args->syncpt];
727
728 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100729 if (!base) {
730 err = -ENXIO;
731 goto unlock;
732 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300733
734 args->id = host1x_syncpt_base_id(base);
735
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100736unlock:
737 mutex_unlock(&fpriv->lock);
738 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300739}
Thierry Reding7678d712014-06-03 14:56:57 +0200740
741static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
742 struct drm_file *file)
743{
744 struct drm_tegra_gem_set_tiling *args = data;
745 enum tegra_bo_tiling_mode mode;
746 struct drm_gem_object *gem;
747 unsigned long value = 0;
748 struct tegra_bo *bo;
749
750 switch (args->mode) {
751 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
752 mode = TEGRA_BO_TILING_MODE_PITCH;
753
754 if (args->value != 0)
755 return -EINVAL;
756
757 break;
758
759 case DRM_TEGRA_GEM_TILING_MODE_TILED:
760 mode = TEGRA_BO_TILING_MODE_TILED;
761
762 if (args->value != 0)
763 return -EINVAL;
764
765 break;
766
767 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
768 mode = TEGRA_BO_TILING_MODE_BLOCK;
769
770 if (args->value > 5)
771 return -EINVAL;
772
773 value = args->value;
774 break;
775
776 default:
777 return -EINVAL;
778 }
779
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100780 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200781 if (!gem)
782 return -ENOENT;
783
784 bo = to_tegra_bo(gem);
785
786 bo->tiling.mode = mode;
787 bo->tiling.value = value;
788
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300789 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200790
791 return 0;
792}
793
794static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
795 struct drm_file *file)
796{
797 struct drm_tegra_gem_get_tiling *args = data;
798 struct drm_gem_object *gem;
799 struct tegra_bo *bo;
800 int err = 0;
801
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100802 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200803 if (!gem)
804 return -ENOENT;
805
806 bo = to_tegra_bo(gem);
807
808 switch (bo->tiling.mode) {
809 case TEGRA_BO_TILING_MODE_PITCH:
810 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
811 args->value = 0;
812 break;
813
814 case TEGRA_BO_TILING_MODE_TILED:
815 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
816 args->value = 0;
817 break;
818
819 case TEGRA_BO_TILING_MODE_BLOCK:
820 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
821 args->value = bo->tiling.value;
822 break;
823
824 default:
825 err = -EINVAL;
826 break;
827 }
828
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300829 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200830
831 return err;
832}
Thierry Reding7b129082014-06-10 12:04:03 +0200833
834static int tegra_gem_set_flags(struct drm_device *drm, void *data,
835 struct drm_file *file)
836{
837 struct drm_tegra_gem_set_flags *args = data;
838 struct drm_gem_object *gem;
839 struct tegra_bo *bo;
840
841 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
842 return -EINVAL;
843
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100844 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200845 if (!gem)
846 return -ENOENT;
847
848 bo = to_tegra_bo(gem);
849 bo->flags = 0;
850
851 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
852 bo->flags |= TEGRA_BO_BOTTOM_UP;
853
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300854 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200855
856 return 0;
857}
858
859static int tegra_gem_get_flags(struct drm_device *drm, void *data,
860 struct drm_file *file)
861{
862 struct drm_tegra_gem_get_flags *args = data;
863 struct drm_gem_object *gem;
864 struct tegra_bo *bo;
865
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100866 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200867 if (!gem)
868 return -ENOENT;
869
870 bo = to_tegra_bo(gem);
871 args->flags = 0;
872
873 if (bo->flags & TEGRA_BO_BOTTOM_UP)
874 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
875
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300876 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200877
878 return 0;
879}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200880#endif
881
Rob Clarkbaa70942013-08-02 13:27:49 -0400882static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200883#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200884 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
885 DRM_UNLOCKED | DRM_RENDER_ALLOW),
886 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
887 DRM_UNLOCKED | DRM_RENDER_ALLOW),
888 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
889 DRM_UNLOCKED | DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
891 DRM_UNLOCKED | DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
893 DRM_UNLOCKED | DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
895 DRM_UNLOCKED | DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200912#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000913};
914
915static const struct file_operations tegra_drm_fops = {
916 .owner = THIS_MODULE,
917 .open = drm_open,
918 .release = drm_release,
919 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200920 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000921 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000922 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000923 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000924 .llseek = noop_llseek,
925};
926
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100927static int tegra_drm_context_cleanup(int id, void *p, void *data)
928{
929 struct tegra_drm_context *context = p;
930
931 tegra_drm_context_free(context);
932
933 return 0;
934}
935
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200936static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100937{
Thierry Reding08943e62013-09-26 16:08:18 +0200938 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100939
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100940 mutex_lock(&fpriv->lock);
941 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
942 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200943
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100944 idr_destroy(&fpriv->contexts);
945 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200946 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100947}
948
Thierry Redinge450fcc2013-02-13 16:13:16 +0100949#ifdef CONFIG_DEBUG_FS
950static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
951{
952 struct drm_info_node *node = (struct drm_info_node *)s->private;
953 struct drm_device *drm = node->minor->dev;
954 struct drm_framebuffer *fb;
955
956 mutex_lock(&drm->mode_config.fb_lock);
957
958 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
959 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200960 fb->base.id, fb->width, fb->height,
961 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200962 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000963 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100964 }
965
966 mutex_unlock(&drm->mode_config.fb_lock);
967
968 return 0;
969}
970
Thierry Reding28c23372015-01-23 09:16:03 +0100971static int tegra_debugfs_iova(struct seq_file *s, void *data)
972{
973 struct drm_info_node *node = (struct drm_info_node *)s->private;
974 struct drm_device *drm = node->minor->dev;
975 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100976 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100977
Michał Mirosław68d890a2017-08-14 23:53:45 +0200978 if (tegra->domain) {
979 mutex_lock(&tegra->mm_lock);
980 drm_mm_print(&tegra->mm, &p);
981 mutex_unlock(&tegra->mm_lock);
982 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100983
984 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100985}
986
Thierry Redinge450fcc2013-02-13 16:13:16 +0100987static struct drm_info_list tegra_debugfs_list[] = {
988 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100989 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100990};
991
992static int tegra_debugfs_init(struct drm_minor *minor)
993{
994 return drm_debugfs_create_files(tegra_debugfs_list,
995 ARRAY_SIZE(tegra_debugfs_list),
996 minor->debugfs_root, minor);
997}
Thierry Redinge450fcc2013-02-13 16:13:16 +0100998#endif
999
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001000static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001001 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001002 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001003 .load = tegra_drm_load,
1004 .unload = tegra_drm_unload,
1005 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001006 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001007 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001008
Thierry Redinge450fcc2013-02-13 16:13:16 +01001009#if defined(CONFIG_DEBUG_FS)
1010 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001011#endif
1012
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001013 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001014 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001015
1016 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1017 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1018 .gem_prime_export = tegra_gem_prime_export,
1019 .gem_prime_import = tegra_gem_prime_import,
1020
Arto Merilainende2ba662013-03-22 16:34:08 +02001021 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001022
1023 .ioctls = tegra_drm_ioctls,
1024 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1025 .fops = &tegra_drm_fops,
1026
1027 .name = DRIVER_NAME,
1028 .desc = DRIVER_DESC,
1029 .date = DRIVER_DATE,
1030 .major = DRIVER_MAJOR,
1031 .minor = DRIVER_MINOR,
1032 .patchlevel = DRIVER_PATCHLEVEL,
1033};
Thierry Reding776dc382013-10-14 14:43:22 +02001034
1035int tegra_drm_register_client(struct tegra_drm *tegra,
1036 struct tegra_drm_client *client)
1037{
1038 mutex_lock(&tegra->clients_lock);
1039 list_add_tail(&client->list, &tegra->clients);
1040 mutex_unlock(&tegra->clients_lock);
1041
1042 return 0;
1043}
1044
1045int tegra_drm_unregister_client(struct tegra_drm *tegra,
1046 struct tegra_drm_client *client)
1047{
1048 mutex_lock(&tegra->clients_lock);
1049 list_del_init(&client->list);
1050 mutex_unlock(&tegra->clients_lock);
1051
1052 return 0;
1053}
1054
Thierry Reding0c407de2018-05-04 15:02:24 +02001055struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1056 bool shared)
1057{
1058 struct drm_device *drm = dev_get_drvdata(client->parent);
1059 struct tegra_drm *tegra = drm->dev_private;
1060 struct iommu_group *group = NULL;
1061 int err;
1062
1063 if (tegra->domain) {
1064 group = iommu_group_get(client->dev);
1065 if (!group) {
1066 dev_err(client->dev, "failed to get IOMMU group\n");
1067 return ERR_PTR(-ENODEV);
1068 }
1069
1070 if (!shared || (shared && (group != tegra->group))) {
1071 err = iommu_attach_group(tegra->domain, group);
1072 if (err < 0) {
1073 iommu_group_put(group);
1074 return ERR_PTR(err);
1075 }
1076
1077 if (shared && !tegra->group)
1078 tegra->group = group;
1079 }
1080 }
1081
1082 return group;
1083}
1084
1085void host1x_client_iommu_detach(struct host1x_client *client,
1086 struct iommu_group *group)
1087{
1088 struct drm_device *drm = dev_get_drvdata(client->parent);
1089 struct tegra_drm *tegra = drm->dev_private;
1090
1091 if (group) {
1092 if (group == tegra->group) {
1093 iommu_detach_group(tegra->domain, group);
1094 tegra->group = NULL;
1095 }
1096
1097 iommu_group_put(group);
1098 }
1099}
1100
Thierry Reding67485fb2017-11-09 13:17:11 +01001101void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001102{
1103 struct iova *alloc;
1104 void *virt;
1105 gfp_t gfp;
1106 int err;
1107
1108 if (tegra->domain)
1109 size = iova_align(&tegra->carveout.domain, size);
1110 else
1111 size = PAGE_ALIGN(size);
1112
1113 gfp = GFP_KERNEL | __GFP_ZERO;
1114 if (!tegra->domain) {
1115 /*
1116 * Many units only support 32-bit addresses, even on 64-bit
1117 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1118 * virtual address space, force allocations to be in the
1119 * lower 32-bit range.
1120 */
1121 gfp |= GFP_DMA;
1122 }
1123
1124 virt = (void *)__get_free_pages(gfp, get_order(size));
1125 if (!virt)
1126 return ERR_PTR(-ENOMEM);
1127
1128 if (!tegra->domain) {
1129 /*
1130 * If IOMMU is disabled, devices address physical memory
1131 * directly.
1132 */
1133 *dma = virt_to_phys(virt);
1134 return virt;
1135 }
1136
1137 alloc = alloc_iova(&tegra->carveout.domain,
1138 size >> tegra->carveout.shift,
1139 tegra->carveout.limit, true);
1140 if (!alloc) {
1141 err = -EBUSY;
1142 goto free_pages;
1143 }
1144
1145 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1146 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1147 size, IOMMU_READ | IOMMU_WRITE);
1148 if (err < 0)
1149 goto free_iova;
1150
1151 return virt;
1152
1153free_iova:
1154 __free_iova(&tegra->carveout.domain, alloc);
1155free_pages:
1156 free_pages((unsigned long)virt, get_order(size));
1157
1158 return ERR_PTR(err);
1159}
1160
1161void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1162 dma_addr_t dma)
1163{
1164 if (tegra->domain)
1165 size = iova_align(&tegra->carveout.domain, size);
1166 else
1167 size = PAGE_ALIGN(size);
1168
1169 if (tegra->domain) {
1170 iommu_unmap(tegra->domain, dma, size);
1171 free_iova(&tegra->carveout.domain,
1172 iova_pfn(&tegra->carveout.domain, dma));
1173 }
1174
1175 free_pages((unsigned long)virt, get_order(size));
1176}
1177
Thierry Reding9910f5c2014-05-22 09:57:15 +02001178static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001179{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001180 struct drm_driver *driver = &tegra_drm_driver;
1181 struct drm_device *drm;
1182 int err;
1183
1184 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001185 if (IS_ERR(drm))
1186 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001187
Thierry Reding9910f5c2014-05-22 09:57:15 +02001188 dev_set_drvdata(&dev->dev, drm);
1189
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001190 err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
1191 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001192 goto put;
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001193
Thierry Reding9910f5c2014-05-22 09:57:15 +02001194 err = drm_dev_register(drm, 0);
1195 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001196 goto put;
Thierry Reding9910f5c2014-05-22 09:57:15 +02001197
Thierry Reding9910f5c2014-05-22 09:57:15 +02001198 return 0;
1199
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001200put:
1201 drm_dev_put(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001202 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001203}
1204
Thierry Reding9910f5c2014-05-22 09:57:15 +02001205static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001206{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001207 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1208
1209 drm_dev_unregister(drm);
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001210 drm_dev_put(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001211
1212 return 0;
1213}
1214
Thierry Reding359ae682014-12-18 17:15:25 +01001215#ifdef CONFIG_PM_SLEEP
1216static int host1x_drm_suspend(struct device *dev)
1217{
1218 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001219 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001220
1221 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001222 tegra_drm_fb_suspend(drm);
1223
1224 tegra->state = drm_atomic_helper_suspend(drm);
1225 if (IS_ERR(tegra->state)) {
1226 tegra_drm_fb_resume(drm);
1227 drm_kms_helper_poll_enable(drm);
1228 return PTR_ERR(tegra->state);
1229 }
Thierry Reding359ae682014-12-18 17:15:25 +01001230
1231 return 0;
1232}
1233
1234static int host1x_drm_resume(struct device *dev)
1235{
1236 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001237 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001238
Thierry Reding986c58d2015-08-11 13:11:49 +02001239 drm_atomic_helper_resume(drm, tegra->state);
1240 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001241 drm_kms_helper_poll_enable(drm);
1242
1243 return 0;
1244}
1245#endif
1246
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001247static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1248 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001249
Thierry Reding776dc382013-10-14 14:43:22 +02001250static const struct of_device_id host1x_drm_subdevs[] = {
1251 { .compatible = "nvidia,tegra20-dc", },
1252 { .compatible = "nvidia,tegra20-hdmi", },
1253 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001254 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001255 { .compatible = "nvidia,tegra30-dc", },
1256 { .compatible = "nvidia,tegra30-hdmi", },
1257 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001258 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001259 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001260 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001261 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001262 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001263 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001264 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001265 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001266 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001267 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001268 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001269 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001270 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001271 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001272 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001273 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001274 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001275 { .compatible = "nvidia,tegra186-sor", },
1276 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001277 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001278 { /* sentinel */ }
1279};
1280
1281static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001282 .driver = {
1283 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001284 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001285 },
Thierry Reding776dc382013-10-14 14:43:22 +02001286 .probe = host1x_drm_probe,
1287 .remove = host1x_drm_remove,
1288 .subdevs = host1x_drm_subdevs,
1289};
1290
Thierry Reding473112e2015-09-10 16:07:14 +02001291static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001292 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001293 &tegra_dc_driver,
1294 &tegra_hdmi_driver,
1295 &tegra_dsi_driver,
1296 &tegra_dpaux_driver,
1297 &tegra_sor_driver,
1298 &tegra_gr2d_driver,
1299 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001300 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001301};
1302
Thierry Reding776dc382013-10-14 14:43:22 +02001303static int __init host1x_drm_init(void)
1304{
1305 int err;
1306
1307 err = host1x_driver_register(&host1x_drm_driver);
1308 if (err < 0)
1309 return err;
1310
Thierry Reding473112e2015-09-10 16:07:14 +02001311 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001312 if (err < 0)
1313 goto unregister_host1x;
1314
Thierry Reding776dc382013-10-14 14:43:22 +02001315 return 0;
1316
Thierry Reding776dc382013-10-14 14:43:22 +02001317unregister_host1x:
1318 host1x_driver_unregister(&host1x_drm_driver);
1319 return err;
1320}
1321module_init(host1x_drm_init);
1322
1323static void __exit host1x_drm_exit(void)
1324{
Thierry Reding473112e2015-09-10 16:07:14 +02001325 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001326 host1x_driver_unregister(&host1x_drm_driver);
1327}
1328module_exit(host1x_drm_exit);
1329
1330MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1331MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1332MODULE_LICENSE("GPL v2");