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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / c5d9ae265b105d9a67575fb67bd4650a6fc08e25 / . / arch / arm / boot / dts / sama7g5.dtsi
blob: eddcfbf4d22336ad9e9c46c6e35299671c2f7123 [file] [log] [blame]
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
4 *
5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
6 *
7 * Author: Eugen Hristev <eugen.hristev@microchip.com>
8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
9 *
10 */
11
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/at91.h>
15#include <dt-bindings/dma/at91.h>
16#include <dt-bindings/gpio/gpio.h>
17
18/ {
19 model = "Microchip SAMA7G5 family SoC";
20 compatible = "microchip,sama7g5";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 interrupt-parent = <&gic>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a7";
32 reg = <0x0>;
33 };
34 };
35
36 clocks {
37 slow_xtal: slow_xtal {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 };
41
42 main_xtal: main_xtal {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 };
46
47 usb_clk: usb_clk {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <48000000>;
51 };
52 };
53
54 vddout25: fixed-regulator-vddout25 {
55 compatible = "regulator-fixed";
56
57 regulator-name = "VDDOUT25";
58 regulator-min-microvolt = <2500000>;
59 regulator-max-microvolt = <2500000>;
60 regulator-boot-on;
61 status = "disabled";
62 };
63
64 ns_sram: sram@100000 {
65 compatible = "mmio-sram";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 reg = <0x100000 0x20000>;
69 ranges;
70 };
71
72 soc {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
Claudiu Beznea2305d7a2021-08-23 16:19:14 +0300[diff] [blame]78 securam: securam@e0000000 {
79 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
80 reg = <0xe0000000 0x4000>;
81 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges = <0 0xe0000000 0x4000>;
85 no-memory-wc;
86 status = "okay";
87 };
88
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]89 secumod: secumod@e0004000 {
90 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
91 reg = <0xe0004000 0x4000>;
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95
96 sfrbu: sfr@e0008000 {
97 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
98 reg = <0xe0008000 0x20>;
99 };
100
101 pioA: pinctrl@e0014000 {
102 compatible = "microchip,sama7g5-pinctrl";
103 reg = <0xe0014000 0x800>;
104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
114 };
115
116 pmc: pmc@e0018000 {
117 compatible = "microchip,sama7g5-pmc", "syscon";
118 reg = <0xe0018000 0x200>;
119 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
120 #clock-cells = <2>;
121 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
122 clock-names = "td_slck", "md_slck", "main_xtal";
123 };
124
Claudiu Beznea16b161b2021-08-23 16:19:15 +0300[diff] [blame]125 shdwc: shdwc@e001d010 {
126 compatible = "microchip,sama7g5-shdwc", "syscon";
127 reg = <0xe001d010 0x10>;
128 clocks = <&clk32k 0>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 atmel,wakeup-rtc-timer;
132 atmel,wakeup-rtt-timer;
133 status = "disabled";
134 };
135
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]136 rtt: rtt@e001d020 {
137 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
138 reg = <0xe001d020 0x30>;
139 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&clk32k 0>;
141 };
142
143 clk32k: clock-controller@e001d050 {
144 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
145 reg = <0xe001d050 0x4>;
146 clocks = <&slow_xtal>;
147 #clock-cells = <1>;
148 };
149
150 gpbr: gpbr@e001d060 {
151 compatible = "microchip,sama7g5-gpbr", "syscon";
152 reg = <0xe001d060 0x48>;
153 };
154
Eugen Hristeve79c5892021-10-20 12:46:54 +0300[diff] [blame]155 rtc: rtc@e001d0a8 {
156 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
157 reg = <0xe001d0a8 0x30>;
158 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clk32k 1>;
160 };
161
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]162 ps_wdt: watchdog@e001d180 {
163 compatible = "microchip,sama7g5-wdt";
164 reg = <0xe001d180 0x24>;
165 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clk32k 0>;
167 };
168
Claudiu Beznea6f346622021-09-08 12:43:29 +0300[diff] [blame]169 chipid@e0020000 {
170 compatible = "microchip,sama7g5-chipid";
171 reg = <0xe0020000 0x8>;
172 };
173
Claudiu Beznea9430ff32021-10-20 12:46:55 +0300[diff] [blame]174 tcb1: timer@e0800000 {
175 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 reg = <0xe0800000 0x100>;
179 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
181 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
182 };
183
Tudor Ambarus0081a522021-12-09 14:36:42 +0200[diff] [blame]184 qspi0: spi@e080c000 {
185 compatible = "microchip,sama7g5-ospi";
186 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
187 reg-names = "qspi_base", "qspi_mmap";
188 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
189 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
190 <&dma0 AT91_XDMAC_DT_PERID(40)>;
191 dma-names = "tx", "rx";
192 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
193 clock-names = "pclk", "gclk";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 status = "disabled";
197 };
198
199 qspi1: spi@e0810000 {
200 compatible = "microchip,sama7g5-qspi";
201 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
202 reg-names = "qspi_base", "qspi_mmap";
203 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
204 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
205 <&dma0 AT91_XDMAC_DT_PERID(42)>;
206 dma-names = "tx", "rx";
207 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
208 clock-names = "pclk", "gclk";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 status = "disabled";
212 };
213
Eugen Hristevc7472302021-09-01 15:30:12 +0300[diff] [blame]214 adc: adc@e1000000 {
215 compatible = "microchip,sama7g5-adc";
216 reg = <0xe1000000 0x200>;
217 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&pmc PMC_TYPE_GCK 26>;
219 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
220 assigned-clock-rates = <100000000>;
221 clock-names = "adc_clk";
222 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
223 dma-names = "rx";
224 atmel,min-sample-rate-hz = <200000>;
225 atmel,max-sample-rate-hz = <20000000>;
226 atmel,startup-time-ms = <4>;
227 status = "disabled";
228 };
229
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]230 sdmmc0: mmc@e1204000 {
231 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
232 reg = <0xe1204000 0x4000>;
233 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
235 clock-names = "hclock", "multclk";
236 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
237 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
238 assigned-clock-rates = <200000000>;
239 microchip,sdcal-inverted;
240 status = "disabled";
241 };
242
243 sdmmc1: mmc@e1208000 {
244 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
245 reg = <0xe1208000 0x4000>;
246 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
248 clock-names = "hclock", "multclk";
249 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
250 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
251 assigned-clock-rates = <200000000>;
252 microchip,sdcal-inverted;
253 status = "disabled";
254 };
255
256 sdmmc2: mmc@e120c000 {
257 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
258 reg = <0xe120c000 0x4000>;
259 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
261 clock-names = "hclock", "multclk";
262 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
263 assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
264 assigned-clock-rates = <200000000>;
265 microchip,sdcal-inverted;
266 status = "disabled";
267 };
268
269 pwm: pwm@e1604000 {
270 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
271 reg = <0xe1604000 0x4000>;
272 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
273 #pwm-cells = <3>;
274 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
275 status = "disabled";
276 };
277
278 spdifrx: spdifrx@e1614000 {
279 #sound-dai-cells = <0>;
280 compatible = "microchip,sama7g5-spdifrx";
281 reg = <0xe1614000 0x4000>;
282 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
283 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
284 dma-names = "rx";
285 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
286 clock-names = "pclk", "gclk";
287 status = "disabled";
288 };
289
290 spdiftx: spdiftx@e1618000 {
291 #sound-dai-cells = <0>;
292 compatible = "microchip,sama7g5-spdiftx";
293 reg = <0xe1618000 0x4000>;
294 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
295 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
296 dma-names = "tx";
297 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
298 clock-names = "pclk", "gclk";
299 };
300
301 i2s0: i2s@e161c000 {
302 compatible = "microchip,sama7g5-i2smcc";
303 #sound-dai-cells = <0>;
304 reg = <0xe161c000 0x4000>;
305 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
306 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
307 dma-names = "tx", "rx";
308 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
309 clock-names = "pclk", "gclk";
310 status = "disabled";
311 };
312
313 i2s1: i2s@e1620000 {
314 compatible = "microchip,sama7g5-i2smcc";
315 #sound-dai-cells = <0>;
316 reg = <0xe1620000 0x4000>;
317 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
318 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
319 dma-names = "tx", "rx";
320 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
321 clock-names = "pclk", "gclk";
322 status = "disabled";
323 };
324
325 pit64b0: timer@e1800000 {
326 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
327 reg = <0xe1800000 0x4000>;
328 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
330 clock-names = "pclk", "gclk";
331 };
332
333 pit64b1: timer@e1804000 {
334 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
335 reg = <0xe1804000 0x4000>;
336 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
338 clock-names = "pclk", "gclk";
339 };
340
341 flx0: flexcom@e1818000 {
342 compatible = "atmel,sama5d2-flexcom";
343 reg = <0xe1818000 0x200>;
344 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges = <0x0 0xe1818000 0x800>;
348 status = "disabled";
349
350 uart0: serial@200 {
351 compatible = "atmel,at91sam9260-usart";
352 reg = <0x200 0x200>;
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
355 clock-names = "usart";
356 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
357 <&dma1 AT91_XDMAC_DT_PERID(5)>;
358 dma-names = "tx", "rx";
359 atmel,use-dma-rx;
360 atmel,use-dma-tx;
361 status = "disabled";
362 };
363 };
364
365 flx1: flexcom@e181c000 {
366 compatible = "atmel,sama5d2-flexcom";
367 reg = <0xe181c000 0x200>;
368 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
369 #address-cells = <1>;
370 #size-cells = <1>;
371 ranges = <0x0 0xe181c000 0x800>;
372 status = "disabled";
373
374 i2c1: i2c@600 {
375 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
376 reg = <0x600 0x200>;
377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
381 atmel,fifo-size = <32>;
382 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
383 <&dma0 AT91_XDMAC_DT_PERID(8)>;
384 dma-names = "rx", "tx";
385 atmel,use-dma-rx;
386 atmel,use-dma-tx;
387 status = "disabled";
388 };
389 };
390
391 flx3: flexcom@e1824000 {
392 compatible = "atmel,sama5d2-flexcom";
393 reg = <0xe1824000 0x200>;
394 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
395 #address-cells = <1>;
396 #size-cells = <1>;
397 ranges = <0x0 0xe1824000 0x800>;
398 status = "disabled";
399
400 uart3: serial@200 {
401 compatible = "atmel,at91sam9260-usart";
402 reg = <0x200 0x200>;
403 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
405 clock-names = "usart";
406 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
407 <&dma1 AT91_XDMAC_DT_PERID(11)>;
408 dma-names = "tx", "rx";
409 atmel,use-dma-rx;
410 atmel,use-dma-tx;
411 status = "disabled";
412 };
413 };
414
415 trng: rng@e2010000 {
416 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
417 reg = <0xe2010000 0x100>;
418 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
420 status = "disabled";
421 };
422
423 flx4: flexcom@e2018000 {
424 compatible = "atmel,sama5d2-flexcom";
425 reg = <0xe2018000 0x200>;
426 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
427 #address-cells = <1>;
428 #size-cells = <1>;
429 ranges = <0x0 0xe2018000 0x800>;
430 status = "disabled";
431
432 uart4: serial@200 {
433 compatible = "atmel,at91sam9260-usart";
434 reg = <0x200 0x200>;
435 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
437 clock-names = "usart";
438 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
439 <&dma1 AT91_XDMAC_DT_PERID(13)>;
440 dma-names = "tx", "rx";
441 atmel,use-dma-rx;
442 atmel,use-dma-tx;
443 atmel,fifo-size = <16>;
444 status = "disabled";
445 };
446 };
447
448 flx7: flexcom@e2024000 {
449 compatible = "atmel,sama5d2-flexcom";
450 reg = <0xe2024000 0x200>;
451 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
452 #address-cells = <1>;
453 #size-cells = <1>;
454 ranges = <0x0 0xe2024000 0x800>;
455 status = "disabled";
456
457 uart7: serial@200 {
458 compatible = "atmel,at91sam9260-usart";
459 reg = <0x200 0x200>;
460 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
462 clock-names = "usart";
463 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
464 <&dma1 AT91_XDMAC_DT_PERID(19)>;
465 dma-names = "tx", "rx";
466 atmel,use-dma-rx;
467 atmel,use-dma-tx;
468 atmel,fifo-size = <16>;
469 status = "disabled";
470 };
471 };
472
473 gmac0: ethernet@e2800000 {
474 compatible = "microchip,sama7g5-gem";
475 reg = <0xe2800000 0x1000>;
476 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
477 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
478 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
479 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
480 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
481 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
483 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
484 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
485 assigned-clock-rates = <125000000>;
486 status = "disabled";
487 };
488
489 gmac1: ethernet@e2804000 {
490 compatible = "microchip,sama7g5-emac";
491 reg = <0xe2804000 0x1000>;
492 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
493 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
495 clock-names = "pclk", "hclk";
496 status = "disabled";
497 };
498
499 dma0: dma-controller@e2808000 {
500 compatible = "microchip,sama7g5-dma";
501 reg = <0xe2808000 0x1000>;
502 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
503 #dma-cells = <1>;
504 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
505 clock-names = "dma_clk";
506 status = "disabled";
507 };
508
509 dma1: dma-controller@e280c000 {
510 compatible = "microchip,sama7g5-dma";
511 reg = <0xe280c000 0x1000>;
512 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
513 #dma-cells = <1>;
514 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
515 clock-names = "dma_clk";
516 status = "disabled";
517 };
518
519 /* Place dma2 here despite it's address */
520 dma2: dma-controller@e1200000 {
521 compatible = "microchip,sama7g5-dma";
522 reg = <0xe1200000 0x1000>;
523 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
524 #dma-cells = <1>;
525 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
526 clock-names = "dma_clk";
527 dma-requests = <0>;
528 status = "disabled";
529 };
530
Claudiu Beznea9430ff32021-10-20 12:46:55 +0300[diff] [blame]531 tcb0: timer@e2814000 {
532 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <0xe2814000 0x100>;
536 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
538 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
539 };
540
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]541 flx8: flexcom@e2818000 {
542 compatible = "atmel,sama5d2-flexcom";
543 reg = <0xe2818000 0x200>;
544 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
545 #address-cells = <1>;
546 #size-cells = <1>;
547 ranges = <0x0 0xe2818000 0x800>;
548 status = "disabled";
549
550 i2c8: i2c@600 {
551 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
552 reg = <0x600 0x200>;
553 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
557 atmel,fifo-size = <32>;
558 dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
559 <&dma0 AT91_XDMAC_DT_PERID(22)>;
560 dma-names = "rx", "tx";
561 atmel,use-dma-rx;
562 atmel,use-dma-tx;
563 status = "disabled";
564 };
565 };
566
567 flx9: flexcom@e281c000 {
568 compatible = "atmel,sama5d2-flexcom";
569 reg = <0xe281c000 0x200>;
570 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
571 #address-cells = <1>;
572 #size-cells = <1>;
573 ranges = <0x0 0xe281c000 0x800>;
574 status = "disabled";
575
576 i2c9: i2c@600 {
577 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
578 reg = <0x600 0x200>;
579 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
581 #size-cells = <0>;
582 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
583 atmel,fifo-size = <32>;
584 dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
585 <&dma0 AT91_XDMAC_DT_PERID(24)>;
586 dma-names = "rx", "tx";
587 atmel,use-dma-rx;
588 atmel,use-dma-tx;
589 status = "disabled";
590 };
591 };
592
593 flx11: flexcom@e2824000 {
594 compatible = "atmel,sama5d2-flexcom";
595 reg = <0xe2824000 0x200>;
596 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges = <0x0 0xe2824000 0x800>;
600 status = "disabled";
601
602 spi11: spi@400 {
603 compatible = "atmel,at91rm9200-spi";
604 reg = <0x400 0x200>;
605 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
607 clock-names = "spi_clk";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 atmel,fifo-size = <32>;
611 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
612 <&dma0 AT91_XDMAC_DT_PERID(28)>;
613 dma-names = "rx", "tx";
614 status = "disabled";
615 };
616 };
617
Claudiu Beznea63a84d52021-08-23 16:19:13 +0300[diff] [blame]618 uddrc: uddrc@e3800000 {
619 compatible = "microchip,sama7g5-uddrc";
620 reg = <0xe3800000 0x4000>;
621 status = "okay";
622 };
623
624 ddr3phy: ddr3phy@e3804000 {
625 compatible = "microchip,sama7g5-ddr3phy";
626 reg = <0xe3804000 0x1000>;
627 status = "okay";
628 };
629
Eugen Hristev75406292021-06-28 15:04:50 +0300[diff] [blame]630 gic: interrupt-controller@e8c11000 {
631 compatible = "arm,cortex-a7-gic";
632 #interrupt-cells = <3>;
633 #address-cells = <0>;
634 interrupt-controller;
635 interrupt-parent;
636 reg = <0xe8c11000 0x1000>,
637 <0xe8c12000 0x2000>;
638 };
639 };
640};