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Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Catalin Marinas0aea86a2012-03-05 11:49:32 +00002/*
3 * Based on arch/arm/include/asm/uaccess.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
Catalin Marinas0aea86a2012-03-05 11:49:32 +00006 */
7#ifndef __ASM_UACCESS_H
8#define __ASM_UACCESS_H
9
Catalin Marinasbd389672016-07-01 14:58:21 +010010#include <asm/alternative.h>
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010011#include <asm/kernel-pgtable.h>
Catalin Marinasbd389672016-07-01 14:58:21 +010012#include <asm/sysreg.h>
13
Catalin Marinas0aea86a2012-03-05 11:49:32 +000014/*
15 * User space memory access functions
16 */
Andre Przywara87261d12016-10-19 14:40:54 +010017#include <linux/bitops.h>
Yang Shibffe1ba2016-06-08 14:40:56 -070018#include <linux/kasan-checks.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000019#include <linux/string.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000020
James Morse338d4f42015-07-22 19:05:54 +010021#include <asm/cpufeature.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000022#include <asm/ptrace.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000023#include <asm/memory.h>
Al Viro46583932016-12-25 14:00:03 -050024#include <asm/extable.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000025
Catalin Marinas0aea86a2012-03-05 11:49:32 +000026#define get_fs() (current_thread_info()->addr_limit)
27
28static inline void set_fs(mm_segment_t fs)
29{
30 current_thread_info()->addr_limit = fs;
James Morse57f49592016-02-05 14:58:48 +000031
Will Deaconc2f0ad42018-02-05 15:34:21 +000032 /*
33 * Prevent a mispredicted conditional call to set_fs from forwarding
34 * the wrong address limit to access_ok under speculation.
35 */
Will Deaconbd4fb6d2018-06-14 11:21:34 +010036 spec_bar();
Will Deaconc2f0ad42018-02-05 15:34:21 +000037
Thomas Garniercf7de272017-06-14 18:12:03 -070038 /* On user-mode return, check fs is correct */
39 set_thread_flag(TIF_FSCHECK);
40
James Morse57f49592016-02-05 14:58:48 +000041 /*
42 * Enable/disable UAO so that copy_to_user() etc can access
43 * kernel memory with the unprivileged instructions.
44 */
45 if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS)
46 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
47 else
48 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO,
49 CONFIG_ARM64_UAO));
Catalin Marinas0aea86a2012-03-05 11:49:32 +000050}
51
Michael S. Tsirkin967f0e52015-01-06 15:11:13 +020052#define segment_eq(a, b) ((a) == (b))
Catalin Marinas0aea86a2012-03-05 11:49:32 +000053
54/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +000055 * Test whether a block of memory is a valid user space address.
56 * Returns 1 if the range is valid, 0 otherwise.
57 *
58 * This is equivalent to the following test:
Robin Murphy51369e32018-02-05 15:34:18 +000059 * (u65)addr + (u65)size <= (u65)current->addr_limit + 1
Catalin Marinas0aea86a2012-03-05 11:49:32 +000060 */
Robin Murphy9085b342018-02-19 13:38:00 +000061static inline unsigned long __range_ok(const void __user *addr, unsigned long size)
Robin Murphy51369e32018-02-05 15:34:18 +000062{
Robin Murphy9085b342018-02-19 13:38:00 +000063 unsigned long ret, limit = current_thread_info()->addr_limit;
Robin Murphy51369e32018-02-05 15:34:18 +000064
Catalin Marinasdf325e02019-12-05 13:57:36 +000065 /*
66 * Asynchronous I/O running in a kernel thread does not have the
67 * TIF_TAGGED_ADDR flag of the process owning the mm, so always untag
68 * the user address before checking.
69 */
Catalin Marinas63f0c602019-07-23 19:58:39 +020070 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) &&
Catalin Marinasdf325e02019-12-05 13:57:36 +000071 (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR)))
Catalin Marinas63f0c602019-07-23 19:58:39 +020072 addr = untagged_addr(addr);
Andrey Konovalov2b835e22019-07-23 19:58:38 +020073
Robin Murphy51369e32018-02-05 15:34:18 +000074 __chk_user_ptr(addr);
75 asm volatile(
76 // A + B <= C + 1 for all A,B,C, in four easy steps:
77 // 1: X = A + B; X' = X % 2^64
Robin Murphy9085b342018-02-19 13:38:00 +000078 " adds %0, %3, %2\n"
Robin Murphy51369e32018-02-05 15:34:18 +000079 // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4
80 " csel %1, xzr, %1, hi\n"
81 // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X'
82 // to compensate for the carry flag being set in step 4. For
83 // X > 2^64, X' merely has to remain nonzero, which it does.
84 " csinv %0, %0, xzr, cc\n"
85 // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1
86 // comes from the carry in being clear. Otherwise, we are
87 // testing X' - C == 0, subject to the previous adjustments.
88 " sbcs xzr, %0, %1\n"
89 " cset %0, ls\n"
Robin Murphy9085b342018-02-19 13:38:00 +000090 : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc");
Robin Murphy51369e32018-02-05 15:34:18 +000091
Robin Murphy9085b342018-02-19 13:38:00 +000092 return ret;
Robin Murphy51369e32018-02-05 15:34:18 +000093}
Catalin Marinas0aea86a2012-03-05 11:49:32 +000094
Linus Torvalds96d4f262019-01-03 18:57:57 -080095#define access_ok(addr, size) __range_ok(addr, size)
Will Deacon12a0ef72013-11-06 17:20:22 +000096#define user_addr_max get_fs
Catalin Marinas0aea86a2012-03-05 11:49:32 +000097
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010098#define _ASM_EXTABLE(from, to) \
99 " .pushsection __ex_table, \"a\"\n" \
100 " .align 3\n" \
101 " .long (" #from " - .), (" #to " - .)\n" \
102 " .popsection\n"
103
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000104/*
Catalin Marinasbd389672016-07-01 14:58:21 +0100105 * User access enabling/disabling.
106 */
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100107#ifdef CONFIG_ARM64_SW_TTBR0_PAN
108static inline void __uaccess_ttbr0_disable(void)
109{
Catalin Marinas6b88a322018-01-10 13:18:30 +0000110 unsigned long flags, ttbr;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100111
Catalin Marinas6b88a322018-01-10 13:18:30 +0000112 local_irq_save(flags);
Will Deacon27a921e2017-08-10 13:58:16 +0100113 ttbr = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000114 ttbr &= ~TTBR_ASID_MASK;
Steve Capper9dfe4822018-01-11 10:11:57 +0000115 /* reserved_ttbr0 placed before swapper_pg_dir */
116 write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1);
Will Deacon27a921e2017-08-10 13:58:16 +0100117 isb();
118 /* Set reserved ASID */
Will Deacon27a921e2017-08-10 13:58:16 +0100119 write_sysreg(ttbr, ttbr1_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100120 isb();
Catalin Marinas6b88a322018-01-10 13:18:30 +0000121 local_irq_restore(flags);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100122}
123
124static inline void __uaccess_ttbr0_enable(void)
125{
Will Deacon27a921e2017-08-10 13:58:16 +0100126 unsigned long flags, ttbr0, ttbr1;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100127
128 /*
129 * Disable interrupts to avoid preemption between reading the 'ttbr0'
130 * variable and the MSR. A context switch could trigger an ASID
131 * roll-over and an update of 'ttbr0'.
132 */
133 local_irq_save(flags);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000134 ttbr0 = READ_ONCE(current_thread_info()->ttbr0);
Will Deacon27a921e2017-08-10 13:58:16 +0100135
136 /* Restore active ASID */
137 ttbr1 = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000138 ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */
Will Deaconb5195382017-12-01 17:33:48 +0000139 ttbr1 |= ttbr0 & TTBR_ASID_MASK;
Will Deacon27a921e2017-08-10 13:58:16 +0100140 write_sysreg(ttbr1, ttbr1_el1);
141 isb();
142
143 /* Restore user page table */
144 write_sysreg(ttbr0, ttbr0_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100145 isb();
146 local_irq_restore(flags);
147}
148
149static inline bool uaccess_ttbr0_disable(void)
150{
151 if (!system_uses_ttbr0_pan())
152 return false;
153 __uaccess_ttbr0_disable();
154 return true;
155}
156
157static inline bool uaccess_ttbr0_enable(void)
158{
159 if (!system_uses_ttbr0_pan())
160 return false;
161 __uaccess_ttbr0_enable();
162 return true;
163}
164#else
165static inline bool uaccess_ttbr0_disable(void)
166{
167 return false;
168}
169
170static inline bool uaccess_ttbr0_enable(void)
171{
172 return false;
173}
174#endif
175
James Morsee1281f52018-01-08 15:38:11 +0000176static inline void __uaccess_disable_hw_pan(void)
177{
178 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,
179 CONFIG_ARM64_PAN));
180}
181
182static inline void __uaccess_enable_hw_pan(void)
183{
184 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
185 CONFIG_ARM64_PAN));
186}
187
Catalin Marinasbd389672016-07-01 14:58:21 +0100188#define __uaccess_disable(alt) \
189do { \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100190 if (!uaccess_ttbr0_disable()) \
191 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \
192 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100193} while (0)
194
195#define __uaccess_enable(alt) \
196do { \
Marc Zyngier75037122016-12-12 13:50:26 +0000197 if (!uaccess_ttbr0_enable()) \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100198 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \
199 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100200} while (0)
201
202static inline void uaccess_disable(void)
203{
204 __uaccess_disable(ARM64_HAS_PAN);
205}
206
207static inline void uaccess_enable(void)
208{
209 __uaccess_enable(ARM64_HAS_PAN);
210}
211
212/*
213 * These functions are no-ops when UAO is present.
214 */
215static inline void uaccess_disable_not_uao(void)
216{
217 __uaccess_disable(ARM64_ALT_PAN_NOT_UAO);
218}
219
220static inline void uaccess_enable_not_uao(void)
221{
222 __uaccess_enable(ARM64_ALT_PAN_NOT_UAO);
223}
224
225/*
Robin Murphy4d8efc22018-02-05 15:34:19 +0000226 * Sanitise a uaccess pointer such that it becomes NULL if above the
Andrey Konovalov2b835e22019-07-23 19:58:38 +0200227 * current addr_limit. In case the pointer is tagged (has the top byte set),
228 * untag the pointer before checking.
Robin Murphy4d8efc22018-02-05 15:34:19 +0000229 */
230#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
231static inline void __user *__uaccess_mask_ptr(const void __user *ptr)
232{
233 void __user *safe_ptr;
234
235 asm volatile(
Andrey Konovalov2b835e22019-07-23 19:58:38 +0200236 " bics xzr, %3, %2\n"
Robin Murphy4d8efc22018-02-05 15:34:19 +0000237 " csel %0, %1, xzr, eq\n"
238 : "=&r" (safe_ptr)
Andrey Konovalov2b835e22019-07-23 19:58:38 +0200239 : "r" (ptr), "r" (current_thread_info()->addr_limit),
240 "r" (untagged_addr(ptr))
Robin Murphy4d8efc22018-02-05 15:34:19 +0000241 : "cc");
242
243 csdb();
244 return safe_ptr;
245}
246
247/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000248 * The "__xxx" versions of the user access functions do not verify the address
249 * space - it must have been done previously with a separate "access_ok()"
250 * call.
251 *
252 * The "__xxx_error" versions set the third argument to -EFAULT if an error
253 * occurs, and leave it unchanged on success.
254 */
James Morse57f49592016-02-05 14:58:48 +0000255#define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000256 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000257 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
258 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000259 "2:\n" \
260 " .section .fixup, \"ax\"\n" \
261 " .align 2\n" \
262 "3: mov %w0, %3\n" \
263 " mov %1, #0\n" \
264 " b 2b\n" \
265 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100266 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000267 : "+r" (err), "=&r" (x) \
268 : "r" (addr), "i" (-EFAULT))
269
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000270#define __raw_get_user(x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000271do { \
272 unsigned long __gu_val; \
James Morse3b82a6e2018-10-10 16:55:44 +0100273 __chk_user_ptr(ptr); \
274 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000275 switch (sizeof(*(ptr))) { \
276 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000277 __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \
278 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000279 break; \
280 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000281 __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \
282 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000283 break; \
284 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000285 __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \
286 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000287 break; \
288 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100289 __get_user_asm("ldr", "ldtr", "%x", __gu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000290 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000291 break; \
292 default: \
293 BUILD_BUG(); \
294 } \
James Morse3b82a6e2018-10-10 16:55:44 +0100295 uaccess_disable_not_uao(); \
Michael S. Tsirkin58fff512014-12-12 01:56:04 +0200296 (x) = (__force __typeof__(*(ptr)))__gu_val; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000297} while (0)
298
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000299#define __get_user_error(x, ptr, err) \
300do { \
Will Deacon84624082018-02-05 15:34:22 +0000301 __typeof__(*(ptr)) __user *__p = (ptr); \
302 might_fault(); \
Linus Torvalds96d4f262019-01-03 18:57:57 -0800303 if (access_ok(__p, sizeof(*__p))) { \
Will Deacon84624082018-02-05 15:34:22 +0000304 __p = uaccess_mask_ptr(__p); \
Catalin Marinas3cd0ddb2019-03-01 14:19:06 +0000305 __raw_get_user((x), __p, (err)); \
Will Deacon84624082018-02-05 15:34:22 +0000306 } else { \
Al Viro8cfb3472020-05-22 15:23:21 +0100307 (x) = (__force __typeof__(x))0; (err) = -EFAULT; \
Will Deacon84624082018-02-05 15:34:22 +0000308 } \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000309} while (0)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000310
Will Deacon84624082018-02-05 15:34:22 +0000311#define __get_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000312({ \
Will Deacon84624082018-02-05 15:34:22 +0000313 int __gu_err = 0; \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000314 __get_user_error((x), (ptr), __gu_err); \
Will Deacon84624082018-02-05 15:34:22 +0000315 __gu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000316})
317
Will Deacon84624082018-02-05 15:34:22 +0000318#define get_user __get_user
319
James Morse57f49592016-02-05 14:58:48 +0000320#define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000321 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000322 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
323 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000324 "2:\n" \
325 " .section .fixup,\"ax\"\n" \
326 " .align 2\n" \
327 "3: mov %w0, %3\n" \
328 " b 2b\n" \
329 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100330 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000331 : "+r" (err) \
332 : "r" (x), "r" (addr), "i" (-EFAULT))
333
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000334#define __raw_put_user(x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000335do { \
336 __typeof__(*(ptr)) __pu_val = (x); \
James Morse3b82a6e2018-10-10 16:55:44 +0100337 __chk_user_ptr(ptr); \
338 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000339 switch (sizeof(*(ptr))) { \
340 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000341 __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \
342 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000343 break; \
344 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000345 __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \
346 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000347 break; \
348 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000349 __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \
350 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000351 break; \
352 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100353 __put_user_asm("str", "sttr", "%x", __pu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000354 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000355 break; \
356 default: \
357 BUILD_BUG(); \
358 } \
Catalin Marinasbd389672016-07-01 14:58:21 +0100359 uaccess_disable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000360} while (0)
361
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000362#define __put_user_error(x, ptr, err) \
363do { \
Will Deacon84624082018-02-05 15:34:22 +0000364 __typeof__(*(ptr)) __user *__p = (ptr); \
365 might_fault(); \
Linus Torvalds96d4f262019-01-03 18:57:57 -0800366 if (access_ok(__p, sizeof(*__p))) { \
Will Deacon84624082018-02-05 15:34:22 +0000367 __p = uaccess_mask_ptr(__p); \
Catalin Marinas3cd0ddb2019-03-01 14:19:06 +0000368 __raw_put_user((x), __p, (err)); \
Will Deacon84624082018-02-05 15:34:22 +0000369 } else { \
370 (err) = -EFAULT; \
371 } \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000372} while (0)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000373
Will Deacon84624082018-02-05 15:34:22 +0000374#define __put_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000375({ \
Will Deacon84624082018-02-05 15:34:22 +0000376 int __pu_err = 0; \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000377 __put_user_error((x), (ptr), __pu_err); \
Will Deacon84624082018-02-05 15:34:22 +0000378 __pu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000379})
380
Will Deacon84624082018-02-05 15:34:22 +0000381#define put_user __put_user
382
Yang Shibffe1ba2016-06-08 14:40:56 -0700383extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000384#define raw_copy_from_user(to, from, n) \
385({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500386 unsigned long __acfu_ret; \
387 uaccess_enable_not_uao(); \
388 __acfu_ret = __arch_copy_from_user((to), \
389 __uaccess_mask_ptr(from), (n)); \
390 uaccess_disable_not_uao(); \
391 __acfu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000392})
393
Yang Shibffe1ba2016-06-08 14:40:56 -0700394extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000395#define raw_copy_to_user(to, from, n) \
396({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500397 unsigned long __actu_ret; \
398 uaccess_enable_not_uao(); \
399 __actu_ret = __arch_copy_to_user(__uaccess_mask_ptr(to), \
400 (from), (n)); \
401 uaccess_disable_not_uao(); \
402 __actu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000403})
404
405extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n);
406#define raw_copy_in_user(to, from, n) \
407({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500408 unsigned long __aciu_ret; \
409 uaccess_enable_not_uao(); \
410 __aciu_ret = __arch_copy_in_user(__uaccess_mask_ptr(to), \
411 __uaccess_mask_ptr(from), (n)); \
412 uaccess_disable_not_uao(); \
413 __aciu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000414})
415
Al Viro92430da2017-03-21 08:40:57 -0400416#define INLINE_COPY_TO_USER
417#define INLINE_COPY_FROM_USER
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000418
Will Deaconf71c2ff2018-02-05 15:34:23 +0000419extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n);
420static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000421{
Pavel Tatashine50be642019-11-20 12:07:40 -0500422 if (access_ok(to, n)) {
423 uaccess_enable_not_uao();
Will Deaconf71c2ff2018-02-05 15:34:23 +0000424 n = __arch_clear_user(__uaccess_mask_ptr(to), n);
Pavel Tatashine50be642019-11-20 12:07:40 -0500425 uaccess_disable_not_uao();
426 }
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000427 return n;
428}
Will Deaconf71c2ff2018-02-05 15:34:23 +0000429#define clear_user __clear_user
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000430
Will Deacon12a0ef72013-11-06 17:20:22 +0000431extern long strncpy_from_user(char *dest, const char __user *src, long count);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000432
Will Deacon12a0ef72013-11-06 17:20:22 +0000433extern __must_check long strnlen_user(const char __user *str, long n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000434
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100435#ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE
436struct page;
437void memcpy_page_flushcache(char *to, struct page *page, size_t offset, size_t len);
438extern unsigned long __must_check __copy_user_flushcache(void *to, const void __user *from, unsigned long n);
439
440static inline int __copy_from_user_flushcache(void *dst, const void __user *src, unsigned size)
441{
442 kasan_check_write(dst, size);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000443 return __copy_user_flushcache(dst, __uaccess_mask_ptr(src), size);
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100444}
445#endif
446
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000447#endif /* __ASM_UACCESS_H */