Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Based on arch/arm/include/asm/uaccess.h |
| 4 | * |
| 5 | * Copyright (C) 2012 ARM Ltd. |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef __ASM_UACCESS_H |
| 8 | #define __ASM_UACCESS_H |
| 9 | |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 10 | #include <asm/alternative.h> |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 11 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 12 | #include <asm/sysreg.h> |
| 13 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 14 | /* |
| 15 | * User space memory access functions |
| 16 | */ |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 17 | #include <linux/bitops.h> |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 18 | #include <linux/kasan-checks.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 19 | #include <linux/string.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 20 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 21 | #include <asm/cpufeature.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 22 | #include <asm/ptrace.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 23 | #include <asm/memory.h> |
Al Viro | 4658393 | 2016-12-25 14:00:03 -0500 | [diff] [blame] | 24 | #include <asm/extable.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 25 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 26 | #define get_fs() (current_thread_info()->addr_limit) |
| 27 | |
| 28 | static inline void set_fs(mm_segment_t fs) |
| 29 | { |
| 30 | current_thread_info()->addr_limit = fs; |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 31 | |
Will Deacon | c2f0ad4 | 2018-02-05 15:34:21 +0000 | [diff] [blame] | 32 | /* |
| 33 | * Prevent a mispredicted conditional call to set_fs from forwarding |
| 34 | * the wrong address limit to access_ok under speculation. |
| 35 | */ |
Will Deacon | bd4fb6d | 2018-06-14 11:21:34 +0100 | [diff] [blame] | 36 | spec_bar(); |
Will Deacon | c2f0ad4 | 2018-02-05 15:34:21 +0000 | [diff] [blame] | 37 | |
Thomas Garnier | cf7de27 | 2017-06-14 18:12:03 -0700 | [diff] [blame] | 38 | /* On user-mode return, check fs is correct */ |
| 39 | set_thread_flag(TIF_FSCHECK); |
| 40 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 41 | /* |
| 42 | * Enable/disable UAO so that copy_to_user() etc can access |
| 43 | * kernel memory with the unprivileged instructions. |
| 44 | */ |
| 45 | if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS) |
| 46 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); |
| 47 | else |
| 48 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO, |
| 49 | CONFIG_ARM64_UAO)); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 50 | } |
| 51 | |
Michael S. Tsirkin | 967f0e5 | 2015-01-06 15:11:13 +0200 | [diff] [blame] | 52 | #define segment_eq(a, b) ((a) == (b)) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 53 | |
| 54 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 55 | * Test whether a block of memory is a valid user space address. |
| 56 | * Returns 1 if the range is valid, 0 otherwise. |
| 57 | * |
| 58 | * This is equivalent to the following test: |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 59 | * (u65)addr + (u65)size <= (u65)current->addr_limit + 1 |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 60 | */ |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 61 | static inline unsigned long __range_ok(const void __user *addr, unsigned long size) |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 62 | { |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 63 | unsigned long ret, limit = current_thread_info()->addr_limit; |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 64 | |
Catalin Marinas | df325e0 | 2019-12-05 13:57:36 +0000 | [diff] [blame] | 65 | /* |
| 66 | * Asynchronous I/O running in a kernel thread does not have the |
| 67 | * TIF_TAGGED_ADDR flag of the process owning the mm, so always untag |
| 68 | * the user address before checking. |
| 69 | */ |
Catalin Marinas | 63f0c60 | 2019-07-23 19:58:39 +0200 | [diff] [blame] | 70 | if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) && |
Catalin Marinas | df325e0 | 2019-12-05 13:57:36 +0000 | [diff] [blame] | 71 | (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR))) |
Catalin Marinas | 63f0c60 | 2019-07-23 19:58:39 +0200 | [diff] [blame] | 72 | addr = untagged_addr(addr); |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 73 | |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 74 | __chk_user_ptr(addr); |
| 75 | asm volatile( |
| 76 | // A + B <= C + 1 for all A,B,C, in four easy steps: |
| 77 | // 1: X = A + B; X' = X % 2^64 |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 78 | " adds %0, %3, %2\n" |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 79 | // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 |
| 80 | " csel %1, xzr, %1, hi\n" |
| 81 | // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' |
| 82 | // to compensate for the carry flag being set in step 4. For |
| 83 | // X > 2^64, X' merely has to remain nonzero, which it does. |
| 84 | " csinv %0, %0, xzr, cc\n" |
| 85 | // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 |
| 86 | // comes from the carry in being clear. Otherwise, we are |
| 87 | // testing X' - C == 0, subject to the previous adjustments. |
| 88 | " sbcs xzr, %0, %1\n" |
| 89 | " cset %0, ls\n" |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 90 | : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc"); |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 91 | |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 92 | return ret; |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 93 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 94 | |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 95 | #define access_ok(addr, size) __range_ok(addr, size) |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 96 | #define user_addr_max get_fs |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 97 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 98 | #define _ASM_EXTABLE(from, to) \ |
| 99 | " .pushsection __ex_table, \"a\"\n" \ |
| 100 | " .align 3\n" \ |
| 101 | " .long (" #from " - .), (" #to " - .)\n" \ |
| 102 | " .popsection\n" |
| 103 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 104 | /* |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 105 | * User access enabling/disabling. |
| 106 | */ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 107 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 108 | static inline void __uaccess_ttbr0_disable(void) |
| 109 | { |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 110 | unsigned long flags, ttbr; |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 111 | |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 112 | local_irq_save(flags); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 113 | ttbr = read_sysreg(ttbr1_el1); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 114 | ttbr &= ~TTBR_ASID_MASK; |
Steve Capper | 9dfe482 | 2018-01-11 10:11:57 +0000 | [diff] [blame] | 115 | /* reserved_ttbr0 placed before swapper_pg_dir */ |
| 116 | write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 117 | isb(); |
| 118 | /* Set reserved ASID */ |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 119 | write_sysreg(ttbr, ttbr1_el1); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 120 | isb(); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 121 | local_irq_restore(flags); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static inline void __uaccess_ttbr0_enable(void) |
| 125 | { |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 126 | unsigned long flags, ttbr0, ttbr1; |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Disable interrupts to avoid preemption between reading the 'ttbr0' |
| 130 | * variable and the MSR. A context switch could trigger an ASID |
| 131 | * roll-over and an update of 'ttbr0'. |
| 132 | */ |
| 133 | local_irq_save(flags); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 134 | ttbr0 = READ_ONCE(current_thread_info()->ttbr0); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 135 | |
| 136 | /* Restore active ASID */ |
| 137 | ttbr1 = read_sysreg(ttbr1_el1); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 138 | ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */ |
Will Deacon | b519538 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 139 | ttbr1 |= ttbr0 & TTBR_ASID_MASK; |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 140 | write_sysreg(ttbr1, ttbr1_el1); |
| 141 | isb(); |
| 142 | |
| 143 | /* Restore user page table */ |
| 144 | write_sysreg(ttbr0, ttbr0_el1); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 145 | isb(); |
| 146 | local_irq_restore(flags); |
| 147 | } |
| 148 | |
| 149 | static inline bool uaccess_ttbr0_disable(void) |
| 150 | { |
| 151 | if (!system_uses_ttbr0_pan()) |
| 152 | return false; |
| 153 | __uaccess_ttbr0_disable(); |
| 154 | return true; |
| 155 | } |
| 156 | |
| 157 | static inline bool uaccess_ttbr0_enable(void) |
| 158 | { |
| 159 | if (!system_uses_ttbr0_pan()) |
| 160 | return false; |
| 161 | __uaccess_ttbr0_enable(); |
| 162 | return true; |
| 163 | } |
| 164 | #else |
| 165 | static inline bool uaccess_ttbr0_disable(void) |
| 166 | { |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | static inline bool uaccess_ttbr0_enable(void) |
| 171 | { |
| 172 | return false; |
| 173 | } |
| 174 | #endif |
| 175 | |
James Morse | e1281f5 | 2018-01-08 15:38:11 +0000 | [diff] [blame] | 176 | static inline void __uaccess_disable_hw_pan(void) |
| 177 | { |
| 178 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, |
| 179 | CONFIG_ARM64_PAN)); |
| 180 | } |
| 181 | |
| 182 | static inline void __uaccess_enable_hw_pan(void) |
| 183 | { |
| 184 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, |
| 185 | CONFIG_ARM64_PAN)); |
| 186 | } |
| 187 | |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 188 | #define __uaccess_disable(alt) \ |
| 189 | do { \ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 190 | if (!uaccess_ttbr0_disable()) \ |
| 191 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ |
| 192 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 193 | } while (0) |
| 194 | |
| 195 | #define __uaccess_enable(alt) \ |
| 196 | do { \ |
Marc Zyngier | 7503712 | 2016-12-12 13:50:26 +0000 | [diff] [blame] | 197 | if (!uaccess_ttbr0_enable()) \ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 198 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ |
| 199 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 200 | } while (0) |
| 201 | |
| 202 | static inline void uaccess_disable(void) |
| 203 | { |
| 204 | __uaccess_disable(ARM64_HAS_PAN); |
| 205 | } |
| 206 | |
| 207 | static inline void uaccess_enable(void) |
| 208 | { |
| 209 | __uaccess_enable(ARM64_HAS_PAN); |
| 210 | } |
| 211 | |
| 212 | /* |
| 213 | * These functions are no-ops when UAO is present. |
| 214 | */ |
| 215 | static inline void uaccess_disable_not_uao(void) |
| 216 | { |
| 217 | __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); |
| 218 | } |
| 219 | |
| 220 | static inline void uaccess_enable_not_uao(void) |
| 221 | { |
| 222 | __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); |
| 223 | } |
| 224 | |
| 225 | /* |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 226 | * Sanitise a uaccess pointer such that it becomes NULL if above the |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 227 | * current addr_limit. In case the pointer is tagged (has the top byte set), |
| 228 | * untag the pointer before checking. |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 229 | */ |
| 230 | #define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) |
| 231 | static inline void __user *__uaccess_mask_ptr(const void __user *ptr) |
| 232 | { |
| 233 | void __user *safe_ptr; |
| 234 | |
| 235 | asm volatile( |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 236 | " bics xzr, %3, %2\n" |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 237 | " csel %0, %1, xzr, eq\n" |
| 238 | : "=&r" (safe_ptr) |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 239 | : "r" (ptr), "r" (current_thread_info()->addr_limit), |
| 240 | "r" (untagged_addr(ptr)) |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 241 | : "cc"); |
| 242 | |
| 243 | csdb(); |
| 244 | return safe_ptr; |
| 245 | } |
| 246 | |
| 247 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 248 | * The "__xxx" versions of the user access functions do not verify the address |
| 249 | * space - it must have been done previously with a separate "access_ok()" |
| 250 | * call. |
| 251 | * |
| 252 | * The "__xxx_error" versions set the third argument to -EFAULT if an error |
| 253 | * occurs, and leave it unchanged on success. |
| 254 | */ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 255 | #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 256 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 257 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 258 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 259 | "2:\n" \ |
| 260 | " .section .fixup, \"ax\"\n" \ |
| 261 | " .align 2\n" \ |
| 262 | "3: mov %w0, %3\n" \ |
| 263 | " mov %1, #0\n" \ |
| 264 | " b 2b\n" \ |
| 265 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 266 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 267 | : "+r" (err), "=&r" (x) \ |
| 268 | : "r" (addr), "i" (-EFAULT)) |
| 269 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 270 | #define __raw_get_user(x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 271 | do { \ |
| 272 | unsigned long __gu_val; \ |
James Morse | 3b82a6e | 2018-10-10 16:55:44 +0100 | [diff] [blame] | 273 | __chk_user_ptr(ptr); \ |
| 274 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 275 | switch (sizeof(*(ptr))) { \ |
| 276 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 277 | __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \ |
| 278 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 279 | break; \ |
| 280 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 281 | __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \ |
| 282 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 283 | break; \ |
| 284 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 285 | __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \ |
| 286 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 287 | break; \ |
| 288 | case 8: \ |
Mark Rutland | d135b8b | 2017-05-03 16:09:38 +0100 | [diff] [blame] | 289 | __get_user_asm("ldr", "ldtr", "%x", __gu_val, (ptr), \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 290 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 291 | break; \ |
| 292 | default: \ |
| 293 | BUILD_BUG(); \ |
| 294 | } \ |
James Morse | 3b82a6e | 2018-10-10 16:55:44 +0100 | [diff] [blame] | 295 | uaccess_disable_not_uao(); \ |
Michael S. Tsirkin | 58fff51 | 2014-12-12 01:56:04 +0200 | [diff] [blame] | 296 | (x) = (__force __typeof__(*(ptr)))__gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 297 | } while (0) |
| 298 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 299 | #define __get_user_error(x, ptr, err) \ |
| 300 | do { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 301 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 302 | might_fault(); \ |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 303 | if (access_ok(__p, sizeof(*__p))) { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 304 | __p = uaccess_mask_ptr(__p); \ |
Catalin Marinas | 3cd0ddb | 2019-03-01 14:19:06 +0000 | [diff] [blame] | 305 | __raw_get_user((x), __p, (err)); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 306 | } else { \ |
Al Viro | 8cfb347 | 2020-05-22 15:23:21 +0100 | [diff] [blame] | 307 | (x) = (__force __typeof__(x))0; (err) = -EFAULT; \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 308 | } \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 309 | } while (0) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 310 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 311 | #define __get_user(x, ptr) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 312 | ({ \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 313 | int __gu_err = 0; \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 314 | __get_user_error((x), (ptr), __gu_err); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 315 | __gu_err; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 316 | }) |
| 317 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 318 | #define get_user __get_user |
| 319 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 320 | #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 321 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 322 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 323 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 324 | "2:\n" \ |
| 325 | " .section .fixup,\"ax\"\n" \ |
| 326 | " .align 2\n" \ |
| 327 | "3: mov %w0, %3\n" \ |
| 328 | " b 2b\n" \ |
| 329 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 330 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 331 | : "+r" (err) \ |
| 332 | : "r" (x), "r" (addr), "i" (-EFAULT)) |
| 333 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 334 | #define __raw_put_user(x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 335 | do { \ |
| 336 | __typeof__(*(ptr)) __pu_val = (x); \ |
James Morse | 3b82a6e | 2018-10-10 16:55:44 +0100 | [diff] [blame] | 337 | __chk_user_ptr(ptr); \ |
| 338 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 339 | switch (sizeof(*(ptr))) { \ |
| 340 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 341 | __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \ |
| 342 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 343 | break; \ |
| 344 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 345 | __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \ |
| 346 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 347 | break; \ |
| 348 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 349 | __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \ |
| 350 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 351 | break; \ |
| 352 | case 8: \ |
Mark Rutland | d135b8b | 2017-05-03 16:09:38 +0100 | [diff] [blame] | 353 | __put_user_asm("str", "sttr", "%x", __pu_val, (ptr), \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 354 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 355 | break; \ |
| 356 | default: \ |
| 357 | BUILD_BUG(); \ |
| 358 | } \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 359 | uaccess_disable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 360 | } while (0) |
| 361 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 362 | #define __put_user_error(x, ptr, err) \ |
| 363 | do { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 364 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 365 | might_fault(); \ |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 366 | if (access_ok(__p, sizeof(*__p))) { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 367 | __p = uaccess_mask_ptr(__p); \ |
Catalin Marinas | 3cd0ddb | 2019-03-01 14:19:06 +0000 | [diff] [blame] | 368 | __raw_put_user((x), __p, (err)); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 369 | } else { \ |
| 370 | (err) = -EFAULT; \ |
| 371 | } \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 372 | } while (0) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 373 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 374 | #define __put_user(x, ptr) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 375 | ({ \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 376 | int __pu_err = 0; \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 377 | __put_user_error((x), (ptr), __pu_err); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 378 | __pu_err; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 379 | }) |
| 380 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 381 | #define put_user __put_user |
| 382 | |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 383 | extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 384 | #define raw_copy_from_user(to, from, n) \ |
| 385 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 386 | unsigned long __acfu_ret; \ |
| 387 | uaccess_enable_not_uao(); \ |
| 388 | __acfu_ret = __arch_copy_from_user((to), \ |
| 389 | __uaccess_mask_ptr(from), (n)); \ |
| 390 | uaccess_disable_not_uao(); \ |
| 391 | __acfu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 392 | }) |
| 393 | |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 394 | extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 395 | #define raw_copy_to_user(to, from, n) \ |
| 396 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 397 | unsigned long __actu_ret; \ |
| 398 | uaccess_enable_not_uao(); \ |
| 399 | __actu_ret = __arch_copy_to_user(__uaccess_mask_ptr(to), \ |
| 400 | (from), (n)); \ |
| 401 | uaccess_disable_not_uao(); \ |
| 402 | __actu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 403 | }) |
| 404 | |
| 405 | extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); |
| 406 | #define raw_copy_in_user(to, from, n) \ |
| 407 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 408 | unsigned long __aciu_ret; \ |
| 409 | uaccess_enable_not_uao(); \ |
| 410 | __aciu_ret = __arch_copy_in_user(__uaccess_mask_ptr(to), \ |
| 411 | __uaccess_mask_ptr(from), (n)); \ |
| 412 | uaccess_disable_not_uao(); \ |
| 413 | __aciu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 414 | }) |
| 415 | |
Al Viro | 92430da | 2017-03-21 08:40:57 -0400 | [diff] [blame] | 416 | #define INLINE_COPY_TO_USER |
| 417 | #define INLINE_COPY_FROM_USER |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 418 | |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 419 | extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); |
| 420 | static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 421 | { |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 422 | if (access_ok(to, n)) { |
| 423 | uaccess_enable_not_uao(); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 424 | n = __arch_clear_user(__uaccess_mask_ptr(to), n); |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 425 | uaccess_disable_not_uao(); |
| 426 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 427 | return n; |
| 428 | } |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 429 | #define clear_user __clear_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 430 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 431 | extern long strncpy_from_user(char *dest, const char __user *src, long count); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 432 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 433 | extern __must_check long strnlen_user(const char __user *str, long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 434 | |
Robin Murphy | 5d7bdeb | 2017-07-25 11:55:43 +0100 | [diff] [blame] | 435 | #ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE |
| 436 | struct page; |
| 437 | void memcpy_page_flushcache(char *to, struct page *page, size_t offset, size_t len); |
| 438 | extern unsigned long __must_check __copy_user_flushcache(void *to, const void __user *from, unsigned long n); |
| 439 | |
| 440 | static inline int __copy_from_user_flushcache(void *dst, const void __user *src, unsigned size) |
| 441 | { |
| 442 | kasan_check_write(dst, size); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 443 | return __copy_user_flushcache(dst, __uaccess_mask_ptr(src), size); |
Robin Murphy | 5d7bdeb | 2017-07-25 11:55:43 +0100 | [diff] [blame] | 444 | } |
| 445 | #endif |
| 446 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 447 | #endif /* __ASM_UACCESS_H */ |