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Catalin Marinas0aea86a2012-03-05 11:49:32 +00001/*
2 * Based on arch/arm/include/asm/uaccess.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __ASM_UACCESS_H
19#define __ASM_UACCESS_H
20
Catalin Marinasbd389672016-07-01 14:58:21 +010021#include <asm/alternative.h>
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010022#include <asm/kernel-pgtable.h>
Catalin Marinasbd389672016-07-01 14:58:21 +010023#include <asm/sysreg.h>
24
Catalin Marinas0aea86a2012-03-05 11:49:32 +000025/*
26 * User space memory access functions
27 */
Andre Przywara87261d12016-10-19 14:40:54 +010028#include <linux/bitops.h>
Yang Shibffe1ba2016-06-08 14:40:56 -070029#include <linux/kasan-checks.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000030#include <linux/string.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000031
James Morse338d4f42015-07-22 19:05:54 +010032#include <asm/cpufeature.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000033#include <asm/ptrace.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000034#include <asm/memory.h>
35#include <asm/compiler.h>
Al Viro46583932016-12-25 14:00:03 -050036#include <asm/extable.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000037
Catalin Marinas0aea86a2012-03-05 11:49:32 +000038#define get_ds() (KERNEL_DS)
Catalin Marinas0aea86a2012-03-05 11:49:32 +000039#define get_fs() (current_thread_info()->addr_limit)
40
41static inline void set_fs(mm_segment_t fs)
42{
43 current_thread_info()->addr_limit = fs;
James Morse57f49592016-02-05 14:58:48 +000044
Will Deaconc2f0ad42018-02-05 15:34:21 +000045 /*
46 * Prevent a mispredicted conditional call to set_fs from forwarding
47 * the wrong address limit to access_ok under speculation.
48 */
49 dsb(nsh);
50 isb();
51
Thomas Garniercf7de272017-06-14 18:12:03 -070052 /* On user-mode return, check fs is correct */
53 set_thread_flag(TIF_FSCHECK);
54
James Morse57f49592016-02-05 14:58:48 +000055 /*
56 * Enable/disable UAO so that copy_to_user() etc can access
57 * kernel memory with the unprivileged instructions.
58 */
59 if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS)
60 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
61 else
62 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO,
63 CONFIG_ARM64_UAO));
Catalin Marinas0aea86a2012-03-05 11:49:32 +000064}
65
Michael S. Tsirkin967f0e52015-01-06 15:11:13 +020066#define segment_eq(a, b) ((a) == (b))
Catalin Marinas0aea86a2012-03-05 11:49:32 +000067
68/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +000069 * Test whether a block of memory is a valid user space address.
70 * Returns 1 if the range is valid, 0 otherwise.
71 *
72 * This is equivalent to the following test:
Robin Murphy51369e32018-02-05 15:34:18 +000073 * (u65)addr + (u65)size <= (u65)current->addr_limit + 1
Catalin Marinas0aea86a2012-03-05 11:49:32 +000074 */
Robin Murphy51369e32018-02-05 15:34:18 +000075static inline unsigned long __range_ok(unsigned long addr, unsigned long size)
76{
77 unsigned long limit = current_thread_info()->addr_limit;
78
79 __chk_user_ptr(addr);
80 asm volatile(
81 // A + B <= C + 1 for all A,B,C, in four easy steps:
82 // 1: X = A + B; X' = X % 2^64
83 " adds %0, %0, %2\n"
84 // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4
85 " csel %1, xzr, %1, hi\n"
86 // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X'
87 // to compensate for the carry flag being set in step 4. For
88 // X > 2^64, X' merely has to remain nonzero, which it does.
89 " csinv %0, %0, xzr, cc\n"
90 // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1
91 // comes from the carry in being clear. Otherwise, we are
92 // testing X' - C == 0, subject to the previous adjustments.
93 " sbcs xzr, %0, %1\n"
94 " cset %0, ls\n"
95 : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc");
96
97 return addr;
98}
Catalin Marinas0aea86a2012-03-05 11:49:32 +000099
Andre Przywara87261d12016-10-19 14:40:54 +0100100/*
Kristina Martsenko7dcd9dd82017-05-03 16:37:46 +0100101 * When dealing with data aborts, watchpoints, or instruction traps we may end
102 * up with a tagged userland pointer. Clear the tag to get a sane pointer to
103 * pass on to access_ok(), for instance.
Andre Przywara87261d12016-10-19 14:40:54 +0100104 */
105#define untagged_addr(addr) sign_extend64(addr, 55)
106
Robin Murphy51369e32018-02-05 15:34:18 +0000107#define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size)
Will Deacon12a0ef72013-11-06 17:20:22 +0000108#define user_addr_max get_fs
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000109
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100110#define _ASM_EXTABLE(from, to) \
111 " .pushsection __ex_table, \"a\"\n" \
112 " .align 3\n" \
113 " .long (" #from " - .), (" #to " - .)\n" \
114 " .popsection\n"
115
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000116/*
Catalin Marinasbd389672016-07-01 14:58:21 +0100117 * User access enabling/disabling.
118 */
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100119#ifdef CONFIG_ARM64_SW_TTBR0_PAN
120static inline void __uaccess_ttbr0_disable(void)
121{
Catalin Marinas6b88a322018-01-10 13:18:30 +0000122 unsigned long flags, ttbr;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100123
Catalin Marinas6b88a322018-01-10 13:18:30 +0000124 local_irq_save(flags);
Will Deacon27a921e2017-08-10 13:58:16 +0100125 ttbr = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000126 ttbr &= ~TTBR_ASID_MASK;
Steve Capper9dfe4822018-01-11 10:11:57 +0000127 /* reserved_ttbr0 placed before swapper_pg_dir */
128 write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1);
Will Deacon27a921e2017-08-10 13:58:16 +0100129 isb();
130 /* Set reserved ASID */
Will Deacon27a921e2017-08-10 13:58:16 +0100131 write_sysreg(ttbr, ttbr1_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100132 isb();
Catalin Marinas6b88a322018-01-10 13:18:30 +0000133 local_irq_restore(flags);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100134}
135
136static inline void __uaccess_ttbr0_enable(void)
137{
Will Deacon27a921e2017-08-10 13:58:16 +0100138 unsigned long flags, ttbr0, ttbr1;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100139
140 /*
141 * Disable interrupts to avoid preemption between reading the 'ttbr0'
142 * variable and the MSR. A context switch could trigger an ASID
143 * roll-over and an update of 'ttbr0'.
144 */
145 local_irq_save(flags);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000146 ttbr0 = READ_ONCE(current_thread_info()->ttbr0);
Will Deacon27a921e2017-08-10 13:58:16 +0100147
148 /* Restore active ASID */
149 ttbr1 = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000150 ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */
Will Deaconb5195382017-12-01 17:33:48 +0000151 ttbr1 |= ttbr0 & TTBR_ASID_MASK;
Will Deacon27a921e2017-08-10 13:58:16 +0100152 write_sysreg(ttbr1, ttbr1_el1);
153 isb();
154
155 /* Restore user page table */
156 write_sysreg(ttbr0, ttbr0_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100157 isb();
158 local_irq_restore(flags);
159}
160
161static inline bool uaccess_ttbr0_disable(void)
162{
163 if (!system_uses_ttbr0_pan())
164 return false;
165 __uaccess_ttbr0_disable();
166 return true;
167}
168
169static inline bool uaccess_ttbr0_enable(void)
170{
171 if (!system_uses_ttbr0_pan())
172 return false;
173 __uaccess_ttbr0_enable();
174 return true;
175}
176#else
177static inline bool uaccess_ttbr0_disable(void)
178{
179 return false;
180}
181
182static inline bool uaccess_ttbr0_enable(void)
183{
184 return false;
185}
186#endif
187
James Morsee1281f52018-01-08 15:38:11 +0000188static inline void __uaccess_disable_hw_pan(void)
189{
190 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,
191 CONFIG_ARM64_PAN));
192}
193
194static inline void __uaccess_enable_hw_pan(void)
195{
196 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
197 CONFIG_ARM64_PAN));
198}
199
Catalin Marinasbd389672016-07-01 14:58:21 +0100200#define __uaccess_disable(alt) \
201do { \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100202 if (!uaccess_ttbr0_disable()) \
203 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \
204 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100205} while (0)
206
207#define __uaccess_enable(alt) \
208do { \
Marc Zyngier75037122016-12-12 13:50:26 +0000209 if (!uaccess_ttbr0_enable()) \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100210 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \
211 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100212} while (0)
213
214static inline void uaccess_disable(void)
215{
216 __uaccess_disable(ARM64_HAS_PAN);
217}
218
219static inline void uaccess_enable(void)
220{
221 __uaccess_enable(ARM64_HAS_PAN);
222}
223
224/*
225 * These functions are no-ops when UAO is present.
226 */
227static inline void uaccess_disable_not_uao(void)
228{
229 __uaccess_disable(ARM64_ALT_PAN_NOT_UAO);
230}
231
232static inline void uaccess_enable_not_uao(void)
233{
234 __uaccess_enable(ARM64_ALT_PAN_NOT_UAO);
235}
236
237/*
Robin Murphy4d8efc22018-02-05 15:34:19 +0000238 * Sanitise a uaccess pointer such that it becomes NULL if above the
239 * current addr_limit.
240 */
241#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
242static inline void __user *__uaccess_mask_ptr(const void __user *ptr)
243{
244 void __user *safe_ptr;
245
246 asm volatile(
247 " bics xzr, %1, %2\n"
248 " csel %0, %1, xzr, eq\n"
249 : "=&r" (safe_ptr)
250 : "r" (ptr), "r" (current_thread_info()->addr_limit)
251 : "cc");
252
253 csdb();
254 return safe_ptr;
255}
256
257/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000258 * The "__xxx" versions of the user access functions do not verify the address
259 * space - it must have been done previously with a separate "access_ok()"
260 * call.
261 *
262 * The "__xxx_error" versions set the third argument to -EFAULT if an error
263 * occurs, and leave it unchanged on success.
264 */
James Morse57f49592016-02-05 14:58:48 +0000265#define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000266 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000267 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
268 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000269 "2:\n" \
270 " .section .fixup, \"ax\"\n" \
271 " .align 2\n" \
272 "3: mov %w0, %3\n" \
273 " mov %1, #0\n" \
274 " b 2b\n" \
275 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100276 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000277 : "+r" (err), "=&r" (x) \
278 : "r" (addr), "i" (-EFAULT))
279
280#define __get_user_err(x, ptr, err) \
281do { \
282 unsigned long __gu_val; \
283 __chk_user_ptr(ptr); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100284 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000285 switch (sizeof(*(ptr))) { \
286 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000287 __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \
288 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000289 break; \
290 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000291 __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \
292 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000293 break; \
294 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000295 __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \
296 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000297 break; \
298 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100299 __get_user_asm("ldr", "ldtr", "%x", __gu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000300 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000301 break; \
302 default: \
303 BUILD_BUG(); \
304 } \
Catalin Marinasbd389672016-07-01 14:58:21 +0100305 uaccess_disable_not_uao(); \
Michael S. Tsirkin58fff512014-12-12 01:56:04 +0200306 (x) = (__force __typeof__(*(ptr)))__gu_val; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000307} while (0)
308
Will Deacon84624082018-02-05 15:34:22 +0000309#define __get_user_check(x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000310({ \
Will Deacon84624082018-02-05 15:34:22 +0000311 __typeof__(*(ptr)) __user *__p = (ptr); \
312 might_fault(); \
313 if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \
314 __p = uaccess_mask_ptr(__p); \
315 __get_user_err((x), __p, (err)); \
316 } else { \
317 (x) = 0; (err) = -EFAULT; \
318 } \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000319})
320
321#define __get_user_error(x, ptr, err) \
322({ \
Will Deacon84624082018-02-05 15:34:22 +0000323 __get_user_check((x), (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000324 (void)0; \
325})
326
Will Deacon84624082018-02-05 15:34:22 +0000327#define __get_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000328({ \
Will Deacon84624082018-02-05 15:34:22 +0000329 int __gu_err = 0; \
330 __get_user_check((x), (ptr), __gu_err); \
331 __gu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000332})
333
Will Deacon84624082018-02-05 15:34:22 +0000334#define get_user __get_user
335
James Morse57f49592016-02-05 14:58:48 +0000336#define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000337 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000338 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
339 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000340 "2:\n" \
341 " .section .fixup,\"ax\"\n" \
342 " .align 2\n" \
343 "3: mov %w0, %3\n" \
344 " b 2b\n" \
345 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100346 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000347 : "+r" (err) \
348 : "r" (x), "r" (addr), "i" (-EFAULT))
349
350#define __put_user_err(x, ptr, err) \
351do { \
352 __typeof__(*(ptr)) __pu_val = (x); \
353 __chk_user_ptr(ptr); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100354 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000355 switch (sizeof(*(ptr))) { \
356 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000357 __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \
358 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000359 break; \
360 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000361 __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \
362 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000363 break; \
364 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000365 __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \
366 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000367 break; \
368 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100369 __put_user_asm("str", "sttr", "%x", __pu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000370 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000371 break; \
372 default: \
373 BUILD_BUG(); \
374 } \
Catalin Marinasbd389672016-07-01 14:58:21 +0100375 uaccess_disable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000376} while (0)
377
Will Deacon84624082018-02-05 15:34:22 +0000378#define __put_user_check(x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000379({ \
Will Deacon84624082018-02-05 15:34:22 +0000380 __typeof__(*(ptr)) __user *__p = (ptr); \
381 might_fault(); \
382 if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \
383 __p = uaccess_mask_ptr(__p); \
384 __put_user_err((x), __p, (err)); \
385 } else { \
386 (err) = -EFAULT; \
387 } \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000388})
389
390#define __put_user_error(x, ptr, err) \
391({ \
Will Deacon84624082018-02-05 15:34:22 +0000392 __put_user_check((x), (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000393 (void)0; \
394})
395
Will Deacon84624082018-02-05 15:34:22 +0000396#define __put_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000397({ \
Will Deacon84624082018-02-05 15:34:22 +0000398 int __pu_err = 0; \
399 __put_user_check((x), (ptr), __pu_err); \
400 __pu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000401})
402
Will Deacon84624082018-02-05 15:34:22 +0000403#define put_user __put_user
404
Yang Shibffe1ba2016-06-08 14:40:56 -0700405extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000406#define raw_copy_from_user(to, from, n) \
407({ \
408 __arch_copy_from_user((to), __uaccess_mask_ptr(from), (n)); \
409})
410
Yang Shibffe1ba2016-06-08 14:40:56 -0700411extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000412#define raw_copy_to_user(to, from, n) \
413({ \
414 __arch_copy_to_user(__uaccess_mask_ptr(to), (from), (n)); \
415})
416
417extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n);
418#define raw_copy_in_user(to, from, n) \
419({ \
420 __arch_copy_in_user(__uaccess_mask_ptr(to), \
421 __uaccess_mask_ptr(from), (n)); \
422})
423
Al Viro92430da2017-03-21 08:40:57 -0400424#define INLINE_COPY_TO_USER
425#define INLINE_COPY_FROM_USER
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000426
Will Deaconf71c2ff2018-02-05 15:34:23 +0000427extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n);
428static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000429{
430 if (access_ok(VERIFY_WRITE, to, n))
Will Deaconf71c2ff2018-02-05 15:34:23 +0000431 n = __arch_clear_user(__uaccess_mask_ptr(to), n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000432 return n;
433}
Will Deaconf71c2ff2018-02-05 15:34:23 +0000434#define clear_user __clear_user
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000435
Will Deacon12a0ef72013-11-06 17:20:22 +0000436extern long strncpy_from_user(char *dest, const char __user *src, long count);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000437
Will Deacon12a0ef72013-11-06 17:20:22 +0000438extern __must_check long strnlen_user(const char __user *str, long n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000439
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100440#ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE
441struct page;
442void memcpy_page_flushcache(char *to, struct page *page, size_t offset, size_t len);
443extern unsigned long __must_check __copy_user_flushcache(void *to, const void __user *from, unsigned long n);
444
445static inline int __copy_from_user_flushcache(void *dst, const void __user *src, unsigned size)
446{
447 kasan_check_write(dst, size);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000448 return __copy_user_flushcache(dst, __uaccess_mask_ptr(src), size);
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100449}
450#endif
451
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000452#endif /* __ASM_UACCESS_H */