Blame - drivers/reset/Kconfig - SHIFTPHONES/mainline/linux

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Thomas Gleixner	ec8f24b	2019-05-19 13:07:45 +0100	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Philipp Zabel	61fc413	2012-11-19 17:23:13 +0100	[diff] [blame]	2	config ARCH_HAS_RESET_CONTROLLER
				3	bool
				4
				5	menuconfig RESET_CONTROLLER
				6	bool "Reset Controller Support"
				7	default y if ARCH_HAS_RESET_CONTROLLER
				8	help
				9	Generic Reset Controller support.
				10
				11	This framework is designed to abstract reset handling of devices
				12	via GPIOs or SoC-internal reset controller modules.
				13
				14	If unsure, say no.
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	15
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	16	if RESET_CONTROLLER
				17
Thor Thayer	6270068	2017-02-22 11:10:17 -0600	[diff] [blame]	18	config RESET_A10SR
				19	tristate "Altera Arria10 System Resource Reset"
				20	depends on MFD_ALTERA_A10SR
				21	help
				22	This option enables support for the external reset functions for
				23	peripheral PHYs on the Altera Arria10 System Resource Chip.
				24
Philipp Zabel	e27b4a6	2016-07-28 15:30:08 +0200	[diff] [blame]	25	config RESET_ATH79
				26	bool "AR71xx Reset Driver" if COMPILE_TEST
				27	default ATH79
				28	help
				29	This enables the ATH79 reset controller driver that supports the
				30	AR71xx SoC reset controller.
				31
Eugeniy Paltsev	3763492	2017-09-14 17:28:42 +0300	[diff] [blame]	32	config RESET_AXS10X
				33	bool "AXS10x Reset Driver" if COMPILE_TEST
				34	default ARC_PLAT_AXS10X
				35	help
				36	This enables the reset controller driver for AXS10x.
				37
Álvaro Fernández Rojas	aac0254	2020-06-17 12:50:35 +0200	[diff] [blame]	38	config RESET_BCM6345
				39	bool "BCM6345 Reset Controller"
				40	depends on BMIPS_GENERIC \|\| COMPILE_TEST
				41	default BMIPS_GENERIC
				42	help
				43	This enables the reset controller driver for BCM6345 SoCs.
				44
Philipp Zabel	70d467e	2016-07-28 15:31:12 +0200	[diff] [blame]	45	config RESET_BERLIN
Jisheng Zhang	5e787cd	2021-06-07 18:10:15 +0800	[diff] [blame]	46	tristate "Berlin Reset Driver"
				47	depends on ARCH_BERLIN \|\| COMPILE_TEST
				48	default m if ARCH_BERLIN
Philipp Zabel	70d467e	2016-07-28 15:31:12 +0200	[diff] [blame]	49	help
				50	This enables the reset controller driver for Marvell Berlin SoCs.
				51
Florian Fainelli	77750bc	2019-01-23 14:54:36 -0800	[diff] [blame]	52	config RESET_BRCMSTB
				53	tristate "Broadcom STB reset controller"
				54	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
				55	default ARCH_BRCMSTB
				56	help
				57	This enables the reset controller driver for Broadcom STB SoCs using
				58	a SUN_TOP_CTRL_SW_INIT style controller.
				59
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	60	config RESET_BRCMSTB_RESCAL
Florian Fainelli	5694ca2	2021-09-23 20:08:40 -0700	[diff] [blame]	61	tristate "Broadcom STB RESCAL reset controller"
Brendan Higgins	7fbcc53	2020-01-27 15:53:53 -0800	[diff] [blame]	62	depends on HAS_IOMEM
Geert Uytterhoeven	42f6a76	2021-03-16 14:37:33 +0100	[diff] [blame]	63	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
				64	default ARCH_BRCMSTB
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	65	help
				66	This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
				67	BCM7216.
				68
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	69	config RESET_HSDK
				70	bool "Synopsys HSDK Reset Driver"
Thomas Meyer	2d48a23	2017-09-09 06:02:46 +0200	[diff] [blame]	71	depends on HAS_IOMEM
Geert Uytterhoeven	544e3bf	2017-09-11 14:22:08 +0200	[diff] [blame]	72	depends on ARC_SOC_HSDK \|\| COMPILE_TEST
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	73	help
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	74	This enables the reset controller driver for HSDK board.
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	75
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	76	config RESET_IMX7
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame]	77	tristate "i.MX7/8 Reset Driver"
Masahiro Yamada	8fa5662	2018-03-06 20:15:11 +0900	[diff] [blame]	78	depends on HAS_IOMEM
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame]	79	depends on SOC_IMX7D \|\| (ARM64 && ARCH_MXC) \|\| COMPILE_TEST
				80	default y if SOC_IMX7D
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	81	select MFD_SYSCON
				82	help
				83	This enables the reset controller driver for i.MX7 SoCs.
				84
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	85	config RESET_INTEL_GW
				86	bool "Intel Reset Controller Driver"
Geert Uytterhoeven	6ab9d62	2021-03-31 10:15:19 +0200	[diff] [blame]	87	depends on X86 \|\| COMPILE_TEST
Brendan Higgins	b460e0a	2020-01-27 15:53:54 -0800	[diff] [blame]	88	depends on OF && HAS_IOMEM
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	89	select REGMAP_MMIO
				90	help
				91	This enables the reset controller driver for Intel Gateway SoCs.
				92	Say Y to control the reset signals provided by reset controller.
				93	Otherwise, say N.
				94
Damien Le Moal	5a2308d	2020-12-13 22:50:47 +0900	[diff] [blame]	95	config RESET_K210
				96	bool "Reset controller driver for Canaan Kendryte K210 SoC"
				97	depends on (SOC_CANAAN \|\| COMPILE_TEST) && OF
				98	select MFD_SYSCON
				99	default SOC_CANAAN
				100	help
				101	Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
				102	Say Y if you want to control reset signals provided by this
				103	controller.
				104
Martin Blumenstingl	79797b6	2017-08-20 00:18:17 +0200	[diff] [blame]	105	config RESET_LANTIQ
				106	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
				107	default SOC_TYPE_XWAY
				108	help
				109	This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
				110
Philipp Zabel	cd7f4b8	2016-07-28 15:32:01 +0200	[diff] [blame]	111	config RESET_LPC18XX
				112	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
				113	default ARCH_LPC18XX
				114	help
				115	This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
				116
Steen Hegelund	453ed42	2021-04-16 10:40:53 +0200	[diff] [blame]	117	config RESET_MCHP_SPARX5
				118	bool "Microchip Sparx5 reset driver"
Horatiu Vultur	8c81620	2021-10-18 11:15:22 +0200	[diff] [blame]	119	depends on ARCH_SPARX5 \|\| SOC_LAN966 \|\| COMPILE_TEST
Steen Hegelund	453ed42	2021-04-16 10:40:53 +0200	[diff] [blame]	120	default y if SPARX5_SWITCH
				121	select MFD_SYSCON
				122	help
				123	This driver supports switch core reset for the Microchip Sparx5 SoC.
				124
Philipp Zabel	44336c2	2016-07-28 15:32:36 +0200	[diff] [blame]	125	config RESET_MESON
Neil Armstrong	3bfe893	2020-10-19 16:48:09 +0200	[diff] [blame]	126	tristate "Meson Reset Driver"
				127	depends on ARCH_MESON \|\| COMPILE_TEST
Philipp Zabel	44336c2	2016-07-28 15:32:36 +0200	[diff] [blame]	128	default ARCH_MESON
				129	help
				130	This enables the reset driver for Amlogic Meson SoCs.
				131
Jerome Brunet	d903779	2018-07-20 17:26:33 +0200	[diff] [blame]	132	config RESET_MESON_AUDIO_ARB
				133	tristate "Meson Audio Memory Arbiter Reset Driver"
				134	depends on ARCH_MESON \|\| COMPILE_TEST
				135	help
				136	This enables the reset driver for Audio Memory Arbiter of
				137	Amlogic's A113 based SoCs
				138
Tomer Maimon	9c81b2c	2019-11-06 16:53:31 +0200	[diff] [blame]	139	config RESET_NPCM
				140	bool "NPCM BMC Reset Driver" if COMPILE_TEST
				141	default ARCH_NPCM
				142	help
				143	This enables the reset controller driver for Nuvoton NPCM
				144	BMC SoCs.
				145
Neil Armstrong	6e667fa	2016-04-01 16:16:13 +0200	[diff] [blame]	146	config RESET_OXNAS
				147	bool
				148
Philipp Zabel	fab3f73	2016-07-28 15:33:07 +0200	[diff] [blame]	149	config RESET_PISTACHIO
Geert Uytterhoeven	4af1607	2021-09-14 11:15:59 +0200	[diff] [blame]	150	bool "Pistachio Reset Driver"
				151	depends on MIPS \|\| COMPILE_TEST
Philipp Zabel	fab3f73	2016-07-28 15:33:07 +0200	[diff] [blame]	152	help
				153	This enables the reset driver for ImgTec Pistachio SoCs.
				154
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	155	config RESET_QCOM_AOSS
John Stultz	e2d5e83	2020-01-08 00:19:13 +0000	[diff] [blame]	156	tristate "Qcom AOSS Reset Driver"
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	157	depends on ARCH_QCOM \|\| COMPILE_TEST
				158	help
				159	This enables the AOSS (always on subsystem) reset driver
				160	for Qualcomm SDM845 SoCs. Say Y if you want to control
				161	reset signals provided by AOSS for Modem, Venus, ADSP,
				162	GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
				163
Sibi Sankar	eea2926	2018-08-30 00:42:11 +0530	[diff] [blame]	164	config RESET_QCOM_PDC
				165	tristate "Qualcomm PDC Reset Driver"
				166	depends on ARCH_QCOM \|\| COMPILE_TEST
				167	help
				168	This enables the PDC (Power Domain Controller) reset driver
				169	for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
				170	to control reset signals provided by PDC for Modem, Compute,
				171	Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
				172
Nicolas Saenz Julienne	abffc82	2020-06-29 18:18:38 +0200	[diff] [blame]	173	config RESET_RASPBERRYPI
				174	tristate "Raspberry Pi 4 Firmware Reset Driver"
				175	depends on RASPBERRYPI_FIRMWARE \|\| (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
				176	default USB_XHCI_PCI
				177	help
				178	Raspberry Pi 4's co-processor controls some of the board's HW
				179	initialization process, but it's up to Linux to trigger it when
				180	relevant. This driver provides a reset controller capable of
				181	interfacing with RPi4's co-processor and model these firmware
				182	initialization routines as reset lines.
				183
Biju Das	bee0855	2021-07-19 13:19:32 +0100	[diff] [blame]	184	config RESET_RZG2L_USBPHY_CTRL
				185	tristate "Renesas RZ/G2L USBPHY control driver"
				186	depends on ARCH_R9A07G044 \|\| COMPILE_TEST
				187	help
				188	Support for USBPHY Control found on RZ/G2L family. It mainly
				189	controls reset and power down of the USB/PHY.
				190
Sudeep Holla	c8ae9c2d	2019-07-08 09:41:08 +0100	[diff] [blame]	191	config RESET_SCMI
				192	tristate "Reset driver controlled via ARM SCMI interface"
				193	depends on ARM_SCMI_PROTOCOL \|\| COMPILE_TEST
				194	default ARM_SCMI_PROTOCOL
				195	help
				196	This driver provides support for reset signal/domains that are
				197	controlled by firmware that implements the SCMI interface.
				198
				199	This driver uses SCMI Message Protocol to interact with the
				200	firmware controlling all the reset signals.
				201
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	202	config RESET_SIMPLE
				203	bool "Simple Reset Controller Driver" if COMPILE_TEST
Krzysztof Kozlowski	4a9a1a5	2021-03-11 16:25:38 +0100	[diff] [blame]	204	default ARCH_ASPEED \|\| ARCH_BCM4908 \|\| ARCH_BITMAIN \|\| ARCH_REALTEK \|\| ARCH_STM32 \|\| (ARCH_INTEL_SOCFPGA && ARM64) \|\| ARCH_SUNXI \|\| ARC
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	205	help
				206	This enables a simple reset controller driver for reset lines that
				207	that can be asserted and deasserted by toggling bits in a contiguous,
				208	exclusive register space.
				209
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	210	Currently this driver supports:
				211	- Altera SoCFPGAs
				212	- ASPEED BMC SoCs
Andreas Färber	5ac33ee	2019-10-23 12:13:09 +0200	[diff] [blame]	213	- Bitmain BM1880 SoC
Andreas Färber	3ab831e	2019-10-23 12:13:10 +0200	[diff] [blame]	214	- Realtek SoCs
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	215	- RCC reset controller in STM32 MCUs
				216	- Allwinner SoCs
Greentime Hu	e4d368e	2021-05-04 18:59:36 +0800	[diff] [blame]	217	- SiFive FU740 SoCs
Philipp Zabel	7e0e901	2016-07-28 15:34:15 +0200	[diff] [blame]	218
Dinh Nguyen	b3ca988	2018-11-13 12:50:48 -0600	[diff] [blame]	219	config RESET_SOCFPGA
Krzysztof Kozlowski	225c13f	2021-03-11 16:27:41 +0100	[diff] [blame]	220	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM \|\| !ARCH_INTEL_SOCFPGA)
				221	default ARM && ARCH_INTEL_SOCFPGA
Dinh Nguyen	b3ca988	2018-11-13 12:50:48 -0600	[diff] [blame]	222	select RESET_SIMPLE
				223	help
				224	This enables the reset driver for the SoCFPGA ARMv7 platforms. This
				225	driver gets initialized early during platform init calls.
				226
Emil Renner Berthing	0be3a15	2021-09-19 14:21:05 +0200	[diff] [blame]	227	config RESET_STARFIVE_JH7100
				228	bool "StarFive JH7100 Reset Driver"
				229	depends on SOC_STARFIVE \|\| COMPILE_TEST
				230	default SOC_STARFIVE
				231	help
				232	This enables the reset controller driver for the StarFive JH7100 SoC.
				233
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	234	config RESET_SUNXI
				235	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
				236	default ARCH_SUNXI
Philipp Zabel	e13c205	2017-08-11 12:58:43 +0200	[diff] [blame]	237	select RESET_SIMPLE
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	238	help
				239	This enables the reset driver for Allwinner SoCs.
				240
Andrew F. Davis	28df169	2017-05-24 13:09:30 -0500	[diff] [blame]	241	config RESET_TI_SCI
				242	tristate "TI System Control Interface (TI-SCI) reset driver"
				243	depends on TI_SCI_PROTOCOL
				244	help
				245	This enables the reset driver support over TI System Control Interface
				246	available on some new TI's SoCs. If you wish to use reset resources
				247	managed by the TI System Controller, say Y here. Otherwise, say N.
				248
Suman Anna	dd9bf86	2017-05-23 22:00:12 -0500	[diff] [blame]	249	config RESET_TI_SYSCON
Andrew F. Davis	cc7c2bb	2016-06-27 12:12:17 -0500	[diff] [blame]	250	tristate "TI SYSCON Reset Driver"
				251	depends on HAS_IOMEM
				252	select MFD_SYSCON
				253	help
				254	This enables the reset driver support for TI devices with
				255	memory-mapped reset registers as part of a syscon device node. If
				256	you wish to use the reset framework for such memory-mapped devices,
				257	say Y here. Otherwise, say N.
				258
Masahiro Yamada	54e991b	2016-08-02 13:18:29 +0900	[diff] [blame]	259	config RESET_UNIPHIER
				260	tristate "Reset controller driver for UniPhier SoCs"
				261	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
				262	depends on OF && MFD_SYSCON
				263	default ARCH_UNIPHIER
				264	help
				265	Support for reset controllers on UniPhier SoCs.
				266	Say Y if you want to control reset signals provided by System Control
				267	block, Media I/O block, Peripheral Block.
				268
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	269	config RESET_UNIPHIER_GLUE
				270	tristate "Reset driver in glue layer for UniPhier SoCs"
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	271	depends on (ARCH_UNIPHIER \|\| COMPILE_TEST) && OF
				272	default ARCH_UNIPHIER
				273	select RESET_SIMPLE
				274	help
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	275	Support for peripheral core reset included in its own glue layer
				276	on UniPhier SoCs. Say Y if you want to control reset signals
				277	provided by the glue layer.
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	278
Philipp Zabel	6f51b86	2016-08-09 09:28:54 +0200	[diff] [blame]	279	config RESET_ZYNQ
				280	bool "ZYNQ Reset Driver" if COMPILE_TEST
				281	default ARCH_ZYNQ
				282	help
				283	This enables the reset controller driver for Xilinx Zynq SoCs.
				284
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	285	source "drivers/reset/sti/Kconfig"
Chen Feng	f59d23c	2015-11-20 10:10:05 +0800	[diff] [blame]	286	source "drivers/reset/hisilicon/Kconfig"
Thierry Reding	dc606c5	2016-08-18 15:50:09 +0200	[diff] [blame]	287	source "drivers/reset/tegra/Kconfig"
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	288
				289	endif