Blame - drivers/reset/Kconfig - SHIFTPHONES/mainline/linux

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Thomas Gleixner	ec8f24b	2019-05-19 13:07:45 +0100	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Philipp Zabel	61fc413	2012-11-19 17:23:13 +0100	[diff] [blame]	2	config ARCH_HAS_RESET_CONTROLLER
				3	bool
				4
				5	menuconfig RESET_CONTROLLER
				6	bool "Reset Controller Support"
				7	default y if ARCH_HAS_RESET_CONTROLLER
				8	help
				9	Generic Reset Controller support.
				10
				11	This framework is designed to abstract reset handling of devices
				12	via GPIOs or SoC-internal reset controller modules.
				13
				14	If unsure, say no.
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	15
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	16	if RESET_CONTROLLER
				17
Thor Thayer	6270068	2017-02-22 11:10:17 -0600	[diff] [blame]	18	config RESET_A10SR
				19	tristate "Altera Arria10 System Resource Reset"
				20	depends on MFD_ALTERA_A10SR
				21	help
				22	This option enables support for the external reset functions for
				23	peripheral PHYs on the Altera Arria10 System Resource Chip.
				24
Philipp Zabel	e27b4a6	2016-07-28 15:30:08 +0200	[diff] [blame]	25	config RESET_ATH79
				26	bool "AR71xx Reset Driver" if COMPILE_TEST
				27	default ATH79
				28	help
				29	This enables the ATH79 reset controller driver that supports the
				30	AR71xx SoC reset controller.
				31
Eugeniy Paltsev	3763492	2017-09-14 17:28:42 +0300	[diff] [blame]	32	config RESET_AXS10X
				33	bool "AXS10x Reset Driver" if COMPILE_TEST
				34	default ARC_PLAT_AXS10X
				35	help
				36	This enables the reset controller driver for AXS10x.
				37
Philipp Zabel	70d467e	2016-07-28 15:31:12 +0200	[diff] [blame]	38	config RESET_BERLIN
				39	bool "Berlin Reset Driver" if COMPILE_TEST
				40	default ARCH_BERLIN
				41	help
				42	This enables the reset controller driver for Marvell Berlin SoCs.
				43
Florian Fainelli	77750bc	2019-01-23 14:54:36 -0800	[diff] [blame]	44	config RESET_BRCMSTB
				45	tristate "Broadcom STB reset controller"
				46	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
				47	default ARCH_BRCMSTB
				48	help
				49	This enables the reset controller driver for Broadcom STB SoCs using
				50	a SUN_TOP_CTRL_SW_INIT style controller.
				51
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	52	config RESET_BRCMSTB_RESCAL
				53	bool "Broadcom STB RESCAL reset controller"
Brendan Higgins	7fbcc53	2020-01-27 15:53:53 -0800	[diff] [blame]	54	depends on HAS_IOMEM
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	55	default ARCH_BRCMSTB \|\| COMPILE_TEST
				56	help
				57	This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
				58	BCM7216.
				59
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	60	config RESET_HSDK
				61	bool "Synopsys HSDK Reset Driver"
Thomas Meyer	2d48a23	2017-09-09 06:02:46 +0200	[diff] [blame]	62	depends on HAS_IOMEM
Geert Uytterhoeven	544e3bf	2017-09-11 14:22:08 +0200	[diff] [blame]	63	depends on ARC_SOC_HSDK \|\| COMPILE_TEST
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	64	help
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	65	This enables the reset controller driver for HSDK board.
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	66
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	67	config RESET_IMX7
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame^]	68	tristate "i.MX7/8 Reset Driver"
Masahiro Yamada	8fa5662	2018-03-06 20:15:11 +0900	[diff] [blame]	69	depends on HAS_IOMEM
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame^]	70	depends on SOC_IMX7D \|\| (ARM64 && ARCH_MXC) \|\| COMPILE_TEST
				71	default y if SOC_IMX7D
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	72	select MFD_SYSCON
				73	help
				74	This enables the reset controller driver for i.MX7 SoCs.
				75
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	76	config RESET_INTEL_GW
				77	bool "Intel Reset Controller Driver"
Brendan Higgins	b460e0a	2020-01-27 15:53:54 -0800	[diff] [blame]	78	depends on OF && HAS_IOMEM
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	79	select REGMAP_MMIO
				80	help
				81	This enables the reset controller driver for Intel Gateway SoCs.
				82	Say Y to control the reset signals provided by reset controller.
				83	Otherwise, say N.
				84
Martin Blumenstingl	79797b6	2017-08-20 00:18:17 +0200	[diff] [blame]	85	config RESET_LANTIQ
				86	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
				87	default SOC_TYPE_XWAY
				88	help
				89	This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
				90
Philipp Zabel	cd7f4b8	2016-07-28 15:32:01 +0200	[diff] [blame]	91	config RESET_LPC18XX
				92	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
				93	default ARCH_LPC18XX
				94	help
				95	This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
				96
Philipp Zabel	44336c2	2016-07-28 15:32:36 +0200	[diff] [blame]	97	config RESET_MESON
				98	bool "Meson Reset Driver" if COMPILE_TEST
				99	default ARCH_MESON
				100	help
				101	This enables the reset driver for Amlogic Meson SoCs.
				102
Jerome Brunet	d903779	2018-07-20 17:26:33 +0200	[diff] [blame]	103	config RESET_MESON_AUDIO_ARB
				104	tristate "Meson Audio Memory Arbiter Reset Driver"
				105	depends on ARCH_MESON \|\| COMPILE_TEST
				106	help
				107	This enables the reset driver for Audio Memory Arbiter of
				108	Amlogic's A113 based SoCs
				109
Tomer Maimon	9c81b2c	2019-11-06 16:53:31 +0200	[diff] [blame]	110	config RESET_NPCM
				111	bool "NPCM BMC Reset Driver" if COMPILE_TEST
				112	default ARCH_NPCM
				113	help
				114	This enables the reset controller driver for Nuvoton NPCM
				115	BMC SoCs.
				116
Neil Armstrong	6e667fa	2016-04-01 16:16:13 +0200	[diff] [blame]	117	config RESET_OXNAS
				118	bool
				119
Philipp Zabel	fab3f73	2016-07-28 15:33:07 +0200	[diff] [blame]	120	config RESET_PISTACHIO
				121	bool "Pistachio Reset Driver" if COMPILE_TEST
				122	default MACH_PISTACHIO
				123	help
				124	This enables the reset driver for ImgTec Pistachio SoCs.
				125
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	126	config RESET_QCOM_AOSS
John Stultz	e2d5e83	2020-01-08 00:19:13 +0000	[diff] [blame]	127	tristate "Qcom AOSS Reset Driver"
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	128	depends on ARCH_QCOM \|\| COMPILE_TEST
				129	help
				130	This enables the AOSS (always on subsystem) reset driver
				131	for Qualcomm SDM845 SoCs. Say Y if you want to control
				132	reset signals provided by AOSS for Modem, Venus, ADSP,
				133	GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
				134
Sibi Sankar	eea2926	2018-08-30 00:42:11 +0530	[diff] [blame]	135	config RESET_QCOM_PDC
				136	tristate "Qualcomm PDC Reset Driver"
				137	depends on ARCH_QCOM \|\| COMPILE_TEST
				138	help
				139	This enables the PDC (Power Domain Controller) reset driver
				140	for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
				141	to control reset signals provided by PDC for Modem, Compute,
				142	Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
				143
Sudeep Holla	c8ae9c2d	2019-07-08 09:41:08 +0100	[diff] [blame]	144	config RESET_SCMI
				145	tristate "Reset driver controlled via ARM SCMI interface"
				146	depends on ARM_SCMI_PROTOCOL \|\| COMPILE_TEST
				147	default ARM_SCMI_PROTOCOL
				148	help
				149	This driver provides support for reset signal/domains that are
				150	controlled by firmware that implements the SCMI interface.
				151
				152	This driver uses SCMI Message Protocol to interact with the
				153	firmware controlling all the reset signals.
				154
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	155	config RESET_SIMPLE
				156	bool "Simple Reset Controller Driver" if COMPILE_TEST
Andreas Färber	3ab831e	2019-10-23 12:13:10 +0200	[diff] [blame]	157	default ARCH_AGILEX \|\| ARCH_ASPEED \|\| ARCH_BITMAIN \|\| ARCH_REALTEK \|\| ARCH_STM32 \|\| ARCH_STRATIX10 \|\| ARCH_SUNXI \|\| ARCH_ZX \|\| ARC
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	158	help
				159	This enables a simple reset controller driver for reset lines that
				160	that can be asserted and deasserted by toggling bits in a contiguous,
				161	exclusive register space.
				162
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	163	Currently this driver supports:
				164	- Altera SoCFPGAs
				165	- ASPEED BMC SoCs
Andreas Färber	5ac33ee	2019-10-23 12:13:09 +0200	[diff] [blame]	166	- Bitmain BM1880 SoC
Andreas Färber	3ab831e	2019-10-23 12:13:10 +0200	[diff] [blame]	167	- Realtek SoCs
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	168	- RCC reset controller in STM32 MCUs
				169	- Allwinner SoCs
				170	- ZTE's zx2967 family
Philipp Zabel	7e0e901	2016-07-28 15:34:15 +0200	[diff] [blame]	171
Gabriel Fernandez	197858b	2018-03-19 08:25:51 +0100	[diff] [blame]	172	config RESET_STM32MP157
				173	bool "STM32MP157 Reset Driver" if COMPILE_TEST
				174	default MACH_STM32MP157
				175	help
				176	This enables the RCC reset controller driver for STM32 MPUs.
				177
Dinh Nguyen	b3ca988	2018-11-13 12:50:48 -0600	[diff] [blame]	178	config RESET_SOCFPGA
				179	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
				180	default ARCH_SOCFPGA
				181	select RESET_SIMPLE
				182	help
				183	This enables the reset driver for the SoCFPGA ARMv7 platforms. This
				184	driver gets initialized early during platform init calls.
				185
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	186	config RESET_SUNXI
				187	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
				188	default ARCH_SUNXI
Philipp Zabel	e13c205	2017-08-11 12:58:43 +0200	[diff] [blame]	189	select RESET_SIMPLE
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	190	help
				191	This enables the reset driver for Allwinner SoCs.
				192
Andrew F. Davis	28df169	2017-05-24 13:09:30 -0500	[diff] [blame]	193	config RESET_TI_SCI
				194	tristate "TI System Control Interface (TI-SCI) reset driver"
				195	depends on TI_SCI_PROTOCOL
				196	help
				197	This enables the reset driver support over TI System Control Interface
				198	available on some new TI's SoCs. If you wish to use reset resources
				199	managed by the TI System Controller, say Y here. Otherwise, say N.
				200
Suman Anna	dd9bf86	2017-05-23 22:00:12 -0500	[diff] [blame]	201	config RESET_TI_SYSCON
Andrew F. Davis	cc7c2bb	2016-06-27 12:12:17 -0500	[diff] [blame]	202	tristate "TI SYSCON Reset Driver"
				203	depends on HAS_IOMEM
				204	select MFD_SYSCON
				205	help
				206	This enables the reset driver support for TI devices with
				207	memory-mapped reset registers as part of a syscon device node. If
				208	you wish to use the reset framework for such memory-mapped devices,
				209	say Y here. Otherwise, say N.
				210
Masahiro Yamada	54e991b	2016-08-02 13:18:29 +0900	[diff] [blame]	211	config RESET_UNIPHIER
				212	tristate "Reset controller driver for UniPhier SoCs"
				213	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
				214	depends on OF && MFD_SYSCON
				215	default ARCH_UNIPHIER
				216	help
				217	Support for reset controllers on UniPhier SoCs.
				218	Say Y if you want to control reset signals provided by System Control
				219	block, Media I/O block, Peripheral Block.
				220
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	221	config RESET_UNIPHIER_GLUE
				222	tristate "Reset driver in glue layer for UniPhier SoCs"
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	223	depends on (ARCH_UNIPHIER \|\| COMPILE_TEST) && OF
				224	default ARCH_UNIPHIER
				225	select RESET_SIMPLE
				226	help
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	227	Support for peripheral core reset included in its own glue layer
				228	on UniPhier SoCs. Say Y if you want to control reset signals
				229	provided by the glue layer.
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	230
Philipp Zabel	6f51b86	2016-08-09 09:28:54 +0200	[diff] [blame]	231	config RESET_ZYNQ
				232	bool "ZYNQ Reset Driver" if COMPILE_TEST
				233	default ARCH_ZYNQ
				234	help
				235	This enables the reset controller driver for Xilinx Zynq SoCs.
				236
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	237	source "drivers/reset/sti/Kconfig"
Chen Feng	f59d23c	2015-11-20 10:10:05 +0800	[diff] [blame]	238	source "drivers/reset/hisilicon/Kconfig"
Thierry Reding	dc606c5	2016-08-18 15:50:09 +0200	[diff] [blame]	239	source "drivers/reset/tegra/Kconfig"
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	240
				241	endif