Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Thierry Reding | 7793426 | 2015-11-23 16:20:35 +0100 | [diff] [blame] | 2 | #include <dt-bindings/mfd/max77620.h> |
| 3 | |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 4 | #include "tegra210.dtsi" |
| 5 | |
| 6 | / { |
| 7 | model = "NVIDIA Jetson TX1"; |
| 8 | compatible = "nvidia,p2180", "nvidia,tegra210"; |
| 9 | |
| 10 | aliases { |
Thierry Reding | 7793426 | 2015-11-23 16:20:35 +0100 | [diff] [blame] | 11 | rtc0 = "/i2c@7000d000/pmic@3c"; |
Thierry Reding | be70771 | 2016-04-11 15:35:06 +0200 | [diff] [blame] | 12 | rtc1 = "/rtc@7000e000"; |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 13 | serial0 = &uarta; |
| 14 | }; |
| 15 | |
Thierry Reding | 5593eb7 | 2016-06-02 14:07:47 +0200 | [diff] [blame] | 16 | chosen { |
| 17 | stdout-path = "serial0:115200n8"; |
| 18 | }; |
| 19 | |
Thierry Reding | 772a6a7 | 2020-06-11 20:06:44 +0200 | [diff] [blame] | 20 | memory@80000000 { |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 21 | device_type = "memory"; |
| 22 | reg = <0x0 0x80000000 0x1 0x0>; |
| 23 | }; |
| 24 | |
Alexandre Courbot | 5e6b9a8 | 2016-12-02 20:57:55 +0100 | [diff] [blame] | 25 | gpu@57000000 { |
| 26 | vdd-supply = <&vdd_gpu>; |
| 27 | }; |
| 28 | |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 29 | /* debug port */ |
Thierry Reding | be70771 | 2016-04-11 15:35:06 +0200 | [diff] [blame] | 30 | serial@70006000 { |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 31 | status = "okay"; |
| 32 | }; |
| 33 | |
Thierry Reding | 7793426 | 2015-11-23 16:20:35 +0100 | [diff] [blame] | 34 | i2c@7000d000 { |
| 35 | status = "okay"; |
| 36 | clock-frequency = <400000>; |
| 37 | |
| 38 | pmic: pmic@3c { |
| 39 | compatible = "maxim,max77620"; |
| 40 | reg = <0x3c>; |
Jon Hunter | 358a677 | 2020-05-20 16:13:18 +0100 | [diff] [blame] | 41 | interrupt-parent = <&tegra_pmc>; |
| 42 | interrupts = <51 IRQ_TYPE_LEVEL_LOW>; |
Thierry Reding | 7793426 | 2015-11-23 16:20:35 +0100 | [diff] [blame] | 43 | |
| 44 | #interrupt-cells = <2>; |
| 45 | interrupt-controller; |
| 46 | |
| 47 | #gpio-cells = <2>; |
| 48 | gpio-controller; |
| 49 | |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&max77620_default>; |
| 52 | |
| 53 | max77620_default: pinmux { |
| 54 | gpio0 { |
| 55 | pins = "gpio0"; |
| 56 | function = "gpio"; |
| 57 | }; |
| 58 | |
| 59 | gpio1 { |
| 60 | pins = "gpio1"; |
| 61 | function = "fps-out"; |
| 62 | drive-push-pull = <1>; |
| 63 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 64 | maxim,active-fps-power-up-slot = <7>; |
| 65 | maxim,active-fps-power-down-slot = <0>; |
| 66 | }; |
| 67 | |
| 68 | gpio2_3 { |
| 69 | pins = "gpio2", "gpio3"; |
| 70 | function = "fps-out"; |
| 71 | drive-open-drain = <1>; |
| 72 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 73 | }; |
| 74 | |
| 75 | gpio4 { |
| 76 | pins = "gpio4"; |
| 77 | function = "32k-out1"; |
| 78 | }; |
| 79 | |
| 80 | gpio5_6_7 { |
| 81 | pins = "gpio5", "gpio6", "gpio7"; |
| 82 | function = "gpio"; |
| 83 | drive-push-pull = <1>; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | fps { |
| 88 | fps0 { |
| 89 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| 90 | maxim,suspend-fps-time-period-us = <1280>; |
| 91 | }; |
| 92 | |
| 93 | fps1 { |
| 94 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; |
| 95 | maxim,suspend-fps-time-period-us = <1280>; |
| 96 | }; |
| 97 | |
| 98 | fps2 { |
| 99 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| 100 | }; |
| 101 | }; |
| 102 | |
| 103 | regulators { |
| 104 | in-ldo0-1-supply = <&vdd_pre>; |
| 105 | in-ldo7-8-supply = <&vdd_pre>; |
| 106 | in-sd3-supply = <&vdd_5v0_sys>; |
| 107 | |
| 108 | vdd_soc: sd0 { |
| 109 | regulator-name = "VDD_SOC"; |
| 110 | regulator-min-microvolt = <600000>; |
| 111 | regulator-max-microvolt = <1400000>; |
| 112 | regulator-always-on; |
| 113 | regulator-boot-on; |
| 114 | |
| 115 | regulator-enable-ramp-delay = <146>; |
| 116 | regulator-ramp-delay = <27500>; |
| 117 | |
| 118 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 119 | }; |
| 120 | |
| 121 | vdd_ddr: sd1 { |
| 122 | regulator-name = "VDD_DDR_1V1_PMIC"; |
| 123 | regulator-always-on; |
| 124 | regulator-boot-on; |
| 125 | |
| 126 | regulator-enable-ramp-delay = <130>; |
| 127 | regulator-ramp-delay = <27500>; |
| 128 | |
| 129 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 130 | }; |
| 131 | |
| 132 | vdd_pre: sd2 { |
| 133 | regulator-name = "VDD_PRE_REG_1V35"; |
| 134 | regulator-min-microvolt = <1350000>; |
| 135 | regulator-max-microvolt = <1350000>; |
| 136 | |
| 137 | regulator-enable-ramp-delay = <176>; |
| 138 | regulator-ramp-delay = <27500>; |
| 139 | |
| 140 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 141 | }; |
| 142 | |
| 143 | vdd_1v8: sd3 { |
| 144 | regulator-name = "VDD_1V8"; |
| 145 | regulator-min-microvolt = <1800000>; |
| 146 | regulator-max-microvolt = <1800000>; |
| 147 | regulator-always-on; |
| 148 | regulator-boot-on; |
| 149 | |
| 150 | regulator-enable-ramp-delay = <242>; |
| 151 | regulator-ramp-delay = <27500>; |
| 152 | |
| 153 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 154 | }; |
| 155 | |
| 156 | vdd_sys_1v2: ldo0 { |
| 157 | regulator-name = "AVDD_SYS_1V2"; |
| 158 | regulator-min-microvolt = <1200000>; |
| 159 | regulator-max-microvolt = <1200000>; |
| 160 | regulator-always-on; |
| 161 | regulator-boot-on; |
| 162 | |
| 163 | regulator-enable-ramp-delay = <26>; |
| 164 | regulator-ramp-delay = <100000>; |
| 165 | |
| 166 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| 167 | }; |
| 168 | |
| 169 | vdd_pex_1v05: ldo1 { |
| 170 | regulator-name = "VDD_PEX_1V05"; |
| 171 | regulator-min-microvolt = <1050000>; |
| 172 | regulator-max-microvolt = <1050000>; |
| 173 | |
| 174 | regulator-enable-ramp-delay = <22>; |
| 175 | regulator-ramp-delay = <100000>; |
| 176 | |
| 177 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 178 | }; |
| 179 | |
| 180 | vddio_sdmmc: ldo2 { |
| 181 | regulator-name = "VDDIO_SDMMC"; |
Aapo Vienamo | 41cc377 | 2018-08-10 21:08:34 +0300 | [diff] [blame] | 182 | regulator-min-microvolt = <1800000>; |
Thierry Reding | 7793426 | 2015-11-23 16:20:35 +0100 | [diff] [blame] | 183 | regulator-max-microvolt = <3300000>; |
| 184 | regulator-always-on; |
| 185 | regulator-boot-on; |
| 186 | |
| 187 | regulator-enable-ramp-delay = <62>; |
| 188 | regulator-ramp-delay = <100000>; |
| 189 | |
| 190 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| 191 | }; |
| 192 | |
| 193 | vdd_cam_hv: ldo3 { |
| 194 | regulator-name = "VDD_CAM_HV"; |
| 195 | regulator-min-microvolt = <2800000>; |
| 196 | regulator-max-microvolt = <2800000>; |
| 197 | |
| 198 | regulator-enable-ramp-delay = <50>; |
| 199 | regulator-ramp-delay = <100000>; |
| 200 | |
| 201 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| 202 | }; |
| 203 | |
| 204 | vdd_rtc: ldo4 { |
| 205 | regulator-name = "VDD_RTC"; |
| 206 | regulator-min-microvolt = <850000>; |
| 207 | regulator-max-microvolt = <850000>; |
| 208 | regulator-always-on; |
| 209 | regulator-boot-on; |
| 210 | |
| 211 | regulator-enable-ramp-delay = <22>; |
| 212 | regulator-ramp-delay = <100000>; |
| 213 | |
| 214 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 215 | }; |
| 216 | |
| 217 | vdd_ts_hv: ldo5 { |
| 218 | regulator-name = "VDD_TS_HV"; |
| 219 | regulator-min-microvolt = <3300000>; |
| 220 | regulator-max-microvolt = <3300000>; |
| 221 | |
| 222 | regulator-enable-ramp-delay = <62>; |
| 223 | regulator-ramp-delay = <100000>; |
| 224 | |
| 225 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| 226 | }; |
| 227 | |
| 228 | vdd_ts: ldo6 { |
| 229 | regulator-name = "VDD_TS_1V8"; |
| 230 | regulator-min-microvolt = <1800000>; |
| 231 | regulator-max-microvolt = <1800000>; |
| 232 | |
| 233 | regulator-enable-ramp-delay = <36>; |
| 234 | regulator-ramp-delay = <100000>; |
| 235 | |
| 236 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 237 | maxim,active-fps-power-up-slot = <7>; |
| 238 | maxim,active-fps-power-down-slot = <0>; |
| 239 | }; |
| 240 | |
| 241 | avdd_1v05_pll: ldo7 { |
| 242 | regulator-name = "AVDD_1V05_PLL"; |
| 243 | regulator-min-microvolt = <1050000>; |
| 244 | regulator-max-microvolt = <1050000>; |
| 245 | regulator-always-on; |
| 246 | regulator-boot-on; |
| 247 | |
| 248 | regulator-enable-ramp-delay = <24>; |
| 249 | regulator-ramp-delay = <100000>; |
| 250 | |
| 251 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 252 | }; |
| 253 | |
| 254 | avdd_1v05: ldo8 { |
| 255 | regulator-name = "AVDD_SATA_HDMI_DP_1V05"; |
| 256 | regulator-min-microvolt = <1050000>; |
| 257 | regulator-max-microvolt = <1050000>; |
| 258 | |
| 259 | regulator-enable-ramp-delay = <22>; |
| 260 | regulator-ramp-delay = <100000>; |
| 261 | |
| 262 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 263 | }; |
| 264 | }; |
| 265 | }; |
| 266 | }; |
| 267 | |
Thierry Reding | a5b6b67 | 2019-06-13 18:53:30 +0200 | [diff] [blame] | 268 | i2c@7000c500 { |
Jon Hunter | 9995f92 | 2020-02-24 14:34:33 +0000 | [diff] [blame] | 269 | status = "okay"; |
| 270 | |
Thierry Reding | a5b6b67 | 2019-06-13 18:53:30 +0200 | [diff] [blame] | 271 | /* module ID EEPROM */ |
| 272 | eeprom@50 { |
| 273 | compatible = "atmel,24c02"; |
| 274 | reg = <0x50>; |
| 275 | |
Jon Hunter | a4387f2 | 2020-09-16 10:49:51 +0100 | [diff] [blame] | 276 | label = "module"; |
Jon Hunter | ec5fd19 | 2020-02-24 14:34:34 +0000 | [diff] [blame] | 277 | vcc-supply = <&vdd_1v8>; |
Thierry Reding | 9efa0fc | 2020-06-12 09:34:27 +0200 | [diff] [blame] | 278 | address-width = <8>; |
| 279 | pagesize = <8>; |
Thierry Reding | a5b6b67 | 2019-06-13 18:53:30 +0200 | [diff] [blame] | 280 | size = <256>; |
| 281 | read-only; |
| 282 | }; |
| 283 | }; |
| 284 | |
Thierry Reding | be70771 | 2016-04-11 15:35:06 +0200 | [diff] [blame] | 285 | pmc@7000e400 { |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 286 | nvidia,invert-interrupt; |
Sowjanya Komatineni | 106f7a0 | 2019-08-16 12:42:06 -0700 | [diff] [blame] | 287 | nvidia,suspend-mode = <0>; |
| 288 | nvidia,cpu-pwr-good-time = <0>; |
| 289 | nvidia,cpu-pwr-off-time = <0>; |
| 290 | nvidia,core-pwr-good-time = <4587 3876>; |
| 291 | nvidia,core-pwr-off-time = <39065>; |
| 292 | nvidia,core-power-req-active-high; |
| 293 | nvidia,sys-clock-req-active-high; |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | /* eMMC */ |
Thierry Reding | 67bb17f | 2020-06-11 20:12:59 +0200 | [diff] [blame] | 297 | mmc@700b0600 { |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 298 | status = "okay"; |
| 299 | bus-width = <8>; |
| 300 | non-removable; |
Aapo Vienamo | 6ff7705 | 2018-08-10 21:08:35 +0300 | [diff] [blame] | 301 | vqmmc-supply = <&vdd_1v8>; |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 302 | }; |
| 303 | |
Thierry Reding | 4cc3e3e | 2021-12-06 17:58:55 +0100 | [diff] [blame] | 304 | clk32k_in: clock-32k { |
Thierry Reding | 393a403 | 2020-06-12 08:57:05 +0200 | [diff] [blame] | 305 | compatible = "fixed-clock"; |
| 306 | clock-frequency = <32768>; |
| 307 | #clock-cells = <0>; |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 308 | }; |
Alexandre Courbot | 5e6b9a8 | 2016-12-02 20:57:55 +0100 | [diff] [blame] | 309 | |
Jon Hunter | 2fdb74f | 2017-03-28 12:48:38 +0100 | [diff] [blame] | 310 | cpus { |
| 311 | cpu@0 { |
| 312 | enable-method = "psci"; |
| 313 | }; |
| 314 | |
| 315 | cpu@1 { |
| 316 | enable-method = "psci"; |
| 317 | }; |
| 318 | |
| 319 | cpu@2 { |
| 320 | enable-method = "psci"; |
| 321 | }; |
| 322 | |
| 323 | cpu@3 { |
| 324 | enable-method = "psci"; |
| 325 | }; |
Joseph Lo | d2c19dd | 2019-02-21 15:21:48 +0800 | [diff] [blame] | 326 | |
| 327 | idle-states { |
| 328 | cpu-sleep { |
| 329 | status = "okay"; |
| 330 | }; |
| 331 | }; |
Jon Hunter | 2fdb74f | 2017-03-28 12:48:38 +0100 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | psci { |
| 335 | compatible = "arm,psci-0.2"; |
| 336 | method = "smc"; |
| 337 | }; |
| 338 | |
Thierry Reding | 097e01c | 2021-12-06 18:02:18 +0100 | [diff] [blame] | 339 | vdd_gpu: regulator-vdd-gpu { |
Thierry Reding | 7517248 | 2020-06-12 09:02:05 +0200 | [diff] [blame] | 340 | compatible = "pwm-regulator"; |
Thierry Reding | 562da8b | 2020-08-06 17:42:45 +0200 | [diff] [blame] | 341 | pwms = <&pwm 1 8000>; |
Thierry Reding | 7517248 | 2020-06-12 09:02:05 +0200 | [diff] [blame] | 342 | regulator-name = "VDD_GPU"; |
| 343 | regulator-min-microvolt = <710000>; |
| 344 | regulator-max-microvolt = <1320000>; |
| 345 | enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; |
| 346 | regulator-ramp-delay = <80>; |
| 347 | regulator-enable-ramp-delay = <2000>; |
| 348 | regulator-settling-time-us = <160>; |
Alexandre Courbot | 5e6b9a8 | 2016-12-02 20:57:55 +0100 | [diff] [blame] | 349 | }; |
Thierry Reding | 9e71045 | 2015-09-09 16:25:05 +0200 | [diff] [blame] | 350 | }; |