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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / b24413180f5600bcb3bb70fbed5cf186b60864bd / . / arch / arm / boot / dts / tegra124-jetson-tk1.dts
blob: e8e777b8ef1b33658f773b36fe0b064b15121d3c [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra124.dtsi"
6
Mikko Perttunen6e72cf02015-03-12 15:48:01 +0100[diff] [blame]7#include "tegra124-jetson-tk1-emc.dtsi"
8
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]9/ {
10 model = "NVIDIA Tegra124 Jetson TK1";
11 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
12
13 aliases {
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]14 rtc0 = "/i2c@7000d000/pmic@40";
15 rtc1 = "/rtc@7000e000";
Ralf Ramsauerc90bb7b2016-01-26 17:59:18 +0100[diff] [blame]16
17 /* This order keeps the mapping DB9 connector <-> ttyS0 */
Olof Johanssonc4574aa2014-11-11 12:49:30 -0800[diff] [blame]18 serial0 = &uartd;
Ralf Ramsauerc90bb7b2016-01-26 17:59:18 +0100[diff] [blame]19 serial1 = &uarta;
20 serial2 = &uartb;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]21 };
22
Jon Hunterf5bbb322016-02-09 13:51:59 +0000[diff] [blame]23 chosen {
24 stdout-path = "serial0:115200n8";
25 };
26
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]27 memory {
28 reg = <0x0 0x80000000 0x0 0x80000000>;
29 };
30
Rob Herring508d6902017-03-21 21:03:06 -0500[diff] [blame]31 pcie@1003000 {
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]32 status = "okay";
33
34 avddio-pex-supply = <&vdd_1v05_run>;
35 dvddio-pex-supply = <&vdd_1v05_run>;
36 avdd-pex-pll-supply = <&vdd_1v05_run>;
37 hvdd-pex-supply = <&vdd_3v3_lp0>;
38 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
39 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
40 avdd-pll-erefe-supply = <&avdd_1v05_run>;
41
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]42 /* Mini PCIe */
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]43 pci@1,0 {
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]44 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]45 phy-names = "pcie-0";
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]46 status = "okay";
47 };
48
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]49 /* Gigabit Ethernet */
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]50 pci@2,0 {
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]52 phy-names = "pcie-0";
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]53 status = "okay";
54 };
55 };
56
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]57 host1x@50000000 {
58 hdmi@54280000 {
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]59 status = "okay";
60
61 hdmi-supply = <&vdd_5v0_hdmi>;
62 pll-supply = <&vdd_hdmi_pll>;
63 vdd-supply = <&vdd_3v3_hdmi>;
64
65 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
66 nvidia,hpd-gpio =
67 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
68 };
69 };
70
Alexandre Courbot21fa1962015-07-01 18:13:47 +0900[diff] [blame]71 gpu@0,57000000 {
72 /*
73 * Node left disabled on purpose - the bootloader will enable
74 * it after having set the VPR up
75 */
76 vdd-supply = <&vdd_gpu>;
77 };
78
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]79 pinmux: pinmux@70000868 {
Stephen Warren6dbaff22014-09-03 09:42:06 -0600[diff] [blame]80 pinctrl-names = "boot";
81 pinctrl-0 = <&state_boot>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]82
Stephen Warren6dbaff22014-09-03 09:42:06 -0600[diff] [blame]83 state_boot: pinmux {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]84 clk_32k_out_pa0 {
85 nvidia,pins = "clk_32k_out_pa0";
86 nvidia,function = "soc";
87 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]88 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]89 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
90 };
91 uart3_cts_n_pa1 {
92 nvidia,pins = "uart3_cts_n_pa1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]93 nvidia,function = "gmi";
94 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
95 nvidia,tristate = <TEGRA_PIN_ENABLE>;
96 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]97 };
98 dap2_fs_pa2 {
99 nvidia,pins = "dap2_fs_pa2";
100 nvidia,function = "i2s1";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]104 };
105 dap2_sclk_pa3 {
106 nvidia,pins = "dap2_sclk_pa3";
107 nvidia,function = "i2s1";
108 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
109 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]110 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]111 };
112 dap2_din_pa4 {
113 nvidia,pins = "dap2_din_pa4";
114 nvidia,function = "i2s1";
115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]116 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]117 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
118 };
119 dap2_dout_pa5 {
120 nvidia,pins = "dap2_dout_pa5";
121 nvidia,function = "i2s1";
122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]124 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]125 };
126 sdmmc3_clk_pa6 {
127 nvidia,pins = "sdmmc3_clk_pa6";
128 nvidia,function = "sdmmc3";
129 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]131 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]132 };
133 sdmmc3_cmd_pa7 {
134 nvidia,pins = "sdmmc3_cmd_pa7";
135 nvidia,function = "sdmmc3";
136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
139 };
140 pb0 {
141 nvidia,pins = "pb0";
142 nvidia,function = "uartd";
143 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]144 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]145 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
146 };
147 pb1 {
148 nvidia,pins = "pb1";
149 nvidia,function = "uartd";
150 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]151 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153 };
154 sdmmc3_dat3_pb4 {
155 nvidia,pins = "sdmmc3_dat3_pb4";
156 nvidia,function = "sdmmc3";
157 nvidia,pull = <TEGRA_PIN_PULL_UP>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
160 };
161 sdmmc3_dat2_pb5 {
162 nvidia,pins = "sdmmc3_dat2_pb5";
163 nvidia,function = "sdmmc3";
164 nvidia,pull = <TEGRA_PIN_PULL_UP>;
165 nvidia,tristate = <TEGRA_PIN_DISABLE>;
166 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
167 };
168 sdmmc3_dat1_pb6 {
169 nvidia,pins = "sdmmc3_dat1_pb6";
170 nvidia,function = "sdmmc3";
171 nvidia,pull = <TEGRA_PIN_PULL_UP>;
172 nvidia,tristate = <TEGRA_PIN_DISABLE>;
173 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
174 };
175 sdmmc3_dat0_pb7 {
176 nvidia,pins = "sdmmc3_dat0_pb7";
177 nvidia,function = "sdmmc3";
178 nvidia,pull = <TEGRA_PIN_PULL_UP>;
179 nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
181 };
182 uart3_rts_n_pc0 {
183 nvidia,pins = "uart3_rts_n_pc0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]184 nvidia,function = "gmi";
185 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
186 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188 };
189 uart2_txd_pc2 {
190 nvidia,pins = "uart2_txd_pc2";
191 nvidia,function = "irda";
192 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
195 };
196 uart2_rxd_pc3 {
197 nvidia,pins = "uart2_rxd_pc3";
198 nvidia,function = "irda";
199 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]200 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 };
203 gen1_i2c_scl_pc4 {
204 nvidia,pins = "gen1_i2c_scl_pc4";
205 nvidia,function = "i2c1";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
210 };
211 gen1_i2c_sda_pc5 {
212 nvidia,pins = "gen1_i2c_sda_pc5";
213 nvidia,function = "i2c1";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
218 };
219 pc7 {
220 nvidia,pins = "pc7";
221 nvidia,function = "rsvd1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]222 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
224 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]225 };
226 pg0 {
227 nvidia,pins = "pg0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]228 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
230 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]231 };
232 pg1 {
233 nvidia,pins = "pg1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]237 };
238 pg2 {
239 nvidia,pins = "pg2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]242 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
243 };
244 pg3 {
245 nvidia,pins = "pg3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]246 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]248 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
249 };
250 pg4 {
251 nvidia,pins = "pg4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]253 nvidia,tristate = <TEGRA_PIN_ENABLE>;
254 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]255 };
256 pg5 {
257 nvidia,pins = "pg5";
258 nvidia,function = "spi4";
259 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260 nvidia,tristate = <TEGRA_PIN_DISABLE>;
261 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
262 };
263 pg6 {
264 nvidia,pins = "pg6";
265 nvidia,function = "spi4";
266 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
268 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
269 };
270 pg7 {
271 nvidia,pins = "pg7";
272 nvidia,function = "spi4";
273 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 };
277 ph0 {
278 nvidia,pins = "ph0";
279 nvidia,function = "gmi";
280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
281 nvidia,tristate = <TEGRA_PIN_ENABLE>;
282 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
283 };
284 ph1 {
285 nvidia,pins = "ph1";
286 nvidia,function = "pwm1";
287 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
288 nvidia,tristate = <TEGRA_PIN_DISABLE>;
289 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
290 };
291 ph2 {
292 nvidia,pins = "ph2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]293 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
295 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
296 };
297 ph3 {
298 nvidia,pins = "ph3";
299 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]300 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
301 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]302 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
303 };
304 ph4 {
305 nvidia,pins = "ph4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]306 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
307 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]308 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
309 };
310 ph5 {
311 nvidia,pins = "ph5";
312 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]313 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]315 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
316 };
317 ph6 {
318 nvidia,pins = "ph6";
319 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]320 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
321 nvidia,tristate = <TEGRA_PIN_ENABLE>;
322 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]323 };
324 ph7 {
325 nvidia,pins = "ph7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]328 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]329 };
330 pi0 {
331 nvidia,pins = "pi0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
334 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
335 };
336 pi1 {
337 nvidia,pins = "pi1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]339 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]340 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]341 };
342 pi2 {
343 nvidia,pins = "pi2";
344 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]345 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
346 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]347 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348 };
349 pi3 {
350 nvidia,pins = "pi3";
351 nvidia,function = "spi4";
352 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>;
354 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
355 };
356 pi4 {
357 nvidia,pins = "pi4";
358 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]359 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
360 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]361 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
362 };
363 pi5 {
364 nvidia,pins = "pi5";
365 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]366 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
367 nvidia,tristate = <TEGRA_PIN_ENABLE>;
368 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]369 };
370 pi6 {
371 nvidia,pins = "pi6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]372 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
373 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]374 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 };
376 pi7 {
377 nvidia,pins = "pi7";
378 nvidia,function = "rsvd1";
379 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
380 nvidia,tristate = <TEGRA_PIN_ENABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 };
383 pj0 {
384 nvidia,pins = "pj0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]385 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
386 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]387 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
388 };
389 pj2 {
390 nvidia,pins = "pj2";
391 nvidia,function = "rsvd1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]392 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
393 nvidia,tristate = <TEGRA_PIN_ENABLE>;
394 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]395 };
396 uart2_cts_n_pj5 {
397 nvidia,pins = "uart2_cts_n_pj5";
398 nvidia,function = "uartb";
399 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]400 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]401 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
402 };
403 uart2_rts_n_pj6 {
404 nvidia,pins = "uart2_rts_n_pj6";
405 nvidia,function = "uartb";
406 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
409 };
410 pj7 {
411 nvidia,pins = "pj7";
412 nvidia,function = "uartd";
413 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
416 };
417 pk0 {
418 nvidia,pins = "pk0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]419 nvidia,function = "rsvd1";
420 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
422 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]423 };
424 pk1 {
425 nvidia,pins = "pk1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]426 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
427 nvidia,tristate = <TEGRA_PIN_DISABLE>;
428 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
429 };
430 pk2 {
431 nvidia,pins = "pk2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
435 };
436 pk3 {
437 nvidia,pins = "pk3";
438 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]439 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
440 nvidia,tristate = <TEGRA_PIN_ENABLE>;
441 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]442 };
443 pk4 {
444 nvidia,pins = "pk4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
448 };
449 spdif_out_pk5 {
450 nvidia,pins = "spdif_out_pk5";
451 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]452 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
453 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]454 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
455 };
456 spdif_in_pk6 {
457 nvidia,pins = "spdif_in_pk6";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
460 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
461 };
462 pk7 {
463 nvidia,pins = "pk7";
464 nvidia,function = "uartd";
465 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
466 nvidia,tristate = <TEGRA_PIN_DISABLE>;
467 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
468 };
469 dap1_fs_pn0 {
470 nvidia,pins = "dap1_fs_pn0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]471 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]472 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]473 nvidia,tristate = <TEGRA_PIN_ENABLE>;
474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]475 };
476 dap1_din_pn1 {
477 nvidia,pins = "dap1_din_pn1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]478 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]479 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]480 nvidia,tristate = <TEGRA_PIN_ENABLE>;
481 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]482 };
483 dap1_dout_pn2 {
484 nvidia,pins = "dap1_dout_pn2";
485 nvidia,function = "sata";
486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
489 };
490 dap1_sclk_pn3 {
491 nvidia,pins = "dap1_sclk_pn3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]492 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]493 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]494 nvidia,tristate = <TEGRA_PIN_ENABLE>;
495 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]496 };
497 usb_vbus_en0_pn4 {
498 nvidia,pins = "usb_vbus_en0_pn4";
499 nvidia,function = "usb";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]500 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]501 nvidia,tristate = <TEGRA_PIN_DISABLE>;
502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]503 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]504 };
505 usb_vbus_en1_pn5 {
506 nvidia,pins = "usb_vbus_en1_pn5";
507 nvidia,function = "usb";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]508 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]509 nvidia,tristate = <TEGRA_PIN_DISABLE>;
510 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]511 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]512 };
513 hdmi_int_pn7 {
514 nvidia,pins = "hdmi_int_pn7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]515 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]516 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]517 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
518 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
519 };
520 ulpi_data7_po0 {
521 nvidia,pins = "ulpi_data7_po0";
522 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]523 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
524 nvidia,tristate = <TEGRA_PIN_ENABLE>;
525 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]526 };
527 ulpi_data0_po1 {
528 nvidia,pins = "ulpi_data0_po1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]529 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
530 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]531 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
532 };
533 ulpi_data1_po2 {
534 nvidia,pins = "ulpi_data1_po2";
535 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]536 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
537 nvidia,tristate = <TEGRA_PIN_ENABLE>;
538 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]539 };
540 ulpi_data2_po3 {
541 nvidia,pins = "ulpi_data2_po3";
542 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]543 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
544 nvidia,tristate = <TEGRA_PIN_ENABLE>;
545 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]546 };
547 ulpi_data3_po4 {
548 nvidia,pins = "ulpi_data3_po4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]549 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
550 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]551 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
552 };
553 ulpi_data4_po5 {
554 nvidia,pins = "ulpi_data4_po5";
555 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]556 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
557 nvidia,tristate = <TEGRA_PIN_ENABLE>;
558 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]559 };
560 ulpi_data5_po6 {
561 nvidia,pins = "ulpi_data5_po6";
562 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]563 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
564 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]565 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
566 };
567 ulpi_data6_po7 {
568 nvidia,pins = "ulpi_data6_po7";
569 nvidia,function = "ulpi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]570 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
571 nvidia,tristate = <TEGRA_PIN_ENABLE>;
572 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]573 };
574 dap3_fs_pp0 {
575 nvidia,pins = "dap3_fs_pp0";
576 nvidia,function = "i2s2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]577 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
578 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]579 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
580 };
581 dap3_din_pp1 {
582 nvidia,pins = "dap3_din_pp1";
583 nvidia,function = "i2s2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]584 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
585 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]586 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
587 };
588 dap3_dout_pp2 {
589 nvidia,pins = "dap3_dout_pp2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]590 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
591 nvidia,tristate = <TEGRA_PIN_DISABLE>;
592 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
593 };
594 dap3_sclk_pp3 {
595 nvidia,pins = "dap3_sclk_pp3";
596 nvidia,function = "rsvd3";
597 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
598 nvidia,tristate = <TEGRA_PIN_ENABLE>;
599 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
600 };
601 dap4_fs_pp4 {
602 nvidia,pins = "dap4_fs_pp4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]603 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]604 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]605 nvidia,tristate = <TEGRA_PIN_ENABLE>;
606 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]607 };
608 dap4_din_pp5 {
609 nvidia,pins = "dap4_din_pp5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]610 nvidia,function = "rsvd3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]611 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]612 nvidia,tristate = <TEGRA_PIN_ENABLE>;
613 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]614 };
615 dap4_dout_pp6 {
616 nvidia,pins = "dap4_dout_pp6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]617 nvidia,function = "rsvd4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]618 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]619 nvidia,tristate = <TEGRA_PIN_ENABLE>;
620 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]621 };
622 dap4_sclk_pp7 {
623 nvidia,pins = "dap4_sclk_pp7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]624 nvidia,function = "rsvd3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]625 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]626 nvidia,tristate = <TEGRA_PIN_ENABLE>;
627 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]628 };
629 kb_col0_pq0 {
630 nvidia,pins = "kb_col0_pq0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]631 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]632 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]633 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 };
635 kb_col1_pq1 {
636 nvidia,pins = "kb_col1_pq1";
637 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]638 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
639 nvidia,tristate = <TEGRA_PIN_ENABLE>;
640 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]641 };
642 kb_col2_pq2 {
643 nvidia,pins = "kb_col2_pq2";
644 nvidia,function = "rsvd2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]645 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
646 nvidia,tristate = <TEGRA_PIN_ENABLE>;
647 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
648 };
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]649 kb_col3_pq3 {
650 nvidia,pins = "kb_col3_pq3";
651 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
652 nvidia,tristate = <TEGRA_PIN_ENABLE>;
653 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
654 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]655 kb_col4_pq4 {
656 nvidia,pins = "kb_col4_pq4";
657 nvidia,function = "sdmmc3";
658 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]659 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]660 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
661 };
662 kb_col5_pq5 {
663 nvidia,pins = "kb_col5_pq5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]666 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667 };
668 kb_col6_pq6 {
669 nvidia,pins = "kb_col6_pq6";
670 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]671 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
672 nvidia,tristate = <TEGRA_PIN_ENABLE>;
673 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]674 };
675 kb_col7_pq7 {
676 nvidia,pins = "kb_col7_pq7";
677 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]678 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
679 nvidia,tristate = <TEGRA_PIN_ENABLE>;
680 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]681 };
682 kb_row0_pr0 {
683 nvidia,pins = "kb_row0_pr0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]684 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
685 nvidia,tristate = <TEGRA_PIN_DISABLE>;
686 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
687 };
688 kb_row1_pr1 {
689 nvidia,pins = "kb_row1_pr1";
690 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]691 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
692 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 };
695 kb_row2_pr2 {
696 nvidia,pins = "kb_row2_pr2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]697 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
698 nvidia,tristate = <TEGRA_PIN_DISABLE>;
699 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
700 };
701 kb_row3_pr3 {
702 nvidia,pins = "kb_row3_pr3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]703 nvidia,function = "kbc";
704 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
705 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]706 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
707 };
708 kb_row4_pr4 {
709 nvidia,pins = "kb_row4_pr4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]712 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713 };
714 kb_row5_pr5 {
715 nvidia,pins = "kb_row5_pr5";
716 nvidia,function = "rsvd3";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]717 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
718 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]719 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
720 };
721 kb_row6_pr6 {
722 nvidia,pins = "kb_row6_pr6";
723 nvidia,function = "displaya_alt";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]724 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
725 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]726 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
727 };
728 kb_row7_pr7 {
729 nvidia,pins = "kb_row7_pr7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]730 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
731 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]732 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
733 };
734 kb_row8_ps0 {
735 nvidia,pins = "kb_row8_ps0";
736 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]737 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
738 nvidia,tristate = <TEGRA_PIN_ENABLE>;
739 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]740 };
741 kb_row9_ps1 {
742 nvidia,pins = "kb_row9_ps1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]743 nvidia,function = "uarta";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]744 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
745 nvidia,tristate = <TEGRA_PIN_DISABLE>;
746 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
747 };
748 kb_row10_ps2 {
749 nvidia,pins = "kb_row10_ps2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]750 nvidia,function = "uarta";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]751 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]752 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]753 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
754 };
755 kb_row11_ps3 {
756 nvidia,pins = "kb_row11_ps3";
757 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]758 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
759 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]760 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
761 };
762 kb_row12_ps4 {
763 nvidia,pins = "kb_row12_ps4";
764 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]765 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
766 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]767 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
768 };
769 kb_row13_ps5 {
770 nvidia,pins = "kb_row13_ps5";
771 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]772 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
773 nvidia,tristate = <TEGRA_PIN_ENABLE>;
774 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]775 };
776 kb_row14_ps6 {
777 nvidia,pins = "kb_row14_ps6";
778 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]779 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
780 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]781 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782 };
783 kb_row15_ps7 {
784 nvidia,pins = "kb_row15_ps7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]785 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
786 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]787 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
788 };
789 kb_row16_pt0 {
790 nvidia,pins = "kb_row16_pt0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]791 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
793 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
794 };
795 kb_row17_pt1 {
796 nvidia,pins = "kb_row17_pt1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]797 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]798 nvidia,tristate = <TEGRA_PIN_ENABLE>;
799 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]800 };
801 gen2_i2c_scl_pt5 {
802 nvidia,pins = "gen2_i2c_scl_pt5";
803 nvidia,function = "i2c2";
804 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
805 nvidia,tristate = <TEGRA_PIN_DISABLE>;
806 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
807 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
808 };
809 gen2_i2c_sda_pt6 {
810 nvidia,pins = "gen2_i2c_sda_pt6";
811 nvidia,function = "i2c2";
812 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
816 };
817 sdmmc4_cmd_pt7 {
818 nvidia,pins = "sdmmc4_cmd_pt7";
819 nvidia,function = "sdmmc4";
820 nvidia,pull = <TEGRA_PIN_PULL_UP>;
821 nvidia,tristate = <TEGRA_PIN_DISABLE>;
822 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
823 };
824 pu0 {
825 nvidia,pins = "pu0";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]826 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
827 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]828 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]829 };
830 pu1 {
831 nvidia,pins = "pu1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]832 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]833 nvidia,tristate = <TEGRA_PIN_DISABLE>;
834 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
835 };
836 pu2 {
837 nvidia,pins = "pu2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]838 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]839 nvidia,tristate = <TEGRA_PIN_DISABLE>;
840 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
841 };
842 pu3 {
843 nvidia,pins = "pu3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]844 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
845 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]846 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]847 };
848 pu4 {
849 nvidia,pins = "pu4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]850 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
851 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]852 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]853 };
854 pu5 {
855 nvidia,pins = "pu5";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]856 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]857 nvidia,tristate = <TEGRA_PIN_DISABLE>;
858 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
859 };
860 pu6 {
861 nvidia,pins = "pu6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]862 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]863 nvidia,tristate = <TEGRA_PIN_DISABLE>;
864 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
865 };
866 pv0 {
867 nvidia,pins = "pv0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]868 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
869 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]870 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
871 };
872 pv1 {
873 nvidia,pins = "pv1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]874 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
875 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]876 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
877 };
878 sdmmc3_cd_n_pv2 {
879 nvidia,pins = "sdmmc3_cd_n_pv2";
880 nvidia,function = "sdmmc3";
881 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]882 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]883 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
884 };
885 sdmmc1_wp_n_pv3 {
886 nvidia,pins = "sdmmc1_wp_n_pv3";
887 nvidia,function = "sdmmc1";
888 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
889 nvidia,tristate = <TEGRA_PIN_ENABLE>;
890 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
891 };
892 ddc_scl_pv4 {
893 nvidia,pins = "ddc_scl_pv4";
894 nvidia,function = "i2c4";
895 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896 nvidia,tristate = <TEGRA_PIN_DISABLE>;
897 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
898 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
899 };
900 ddc_sda_pv5 {
901 nvidia,pins = "ddc_sda_pv5";
902 nvidia,function = "i2c4";
903 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904 nvidia,tristate = <TEGRA_PIN_DISABLE>;
905 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
907 };
908 gpio_w2_aud_pw2 {
909 nvidia,pins = "gpio_w2_aud_pw2";
910 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]911 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
912 nvidia,tristate = <TEGRA_PIN_ENABLE>;
913 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]914 };
915 gpio_w3_aud_pw3 {
916 nvidia,pins = "gpio_w3_aud_pw3";
917 nvidia,function = "spi6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]918 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
919 nvidia,tristate = <TEGRA_PIN_ENABLE>;
920 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]921 };
922 dap_mclk1_pw4 {
923 nvidia,pins = "dap_mclk1_pw4";
924 nvidia,function = "extperiph1";
925 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
926 nvidia,tristate = <TEGRA_PIN_DISABLE>;
927 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
928 };
929 clk2_out_pw5 {
930 nvidia,pins = "clk2_out_pw5";
931 nvidia,function = "extperiph2";
932 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
933 nvidia,tristate = <TEGRA_PIN_DISABLE>;
934 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
935 };
936 uart3_txd_pw6 {
937 nvidia,pins = "uart3_txd_pw6";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]938 nvidia,function = "rsvd2";
939 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
940 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]941 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
942 };
943 uart3_rxd_pw7 {
944 nvidia,pins = "uart3_rxd_pw7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]945 nvidia,function = "rsvd2";
946 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
947 nvidia,tristate = <TEGRA_PIN_ENABLE>;
948 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]949 };
950 dvfs_pwm_px0 {
951 nvidia,pins = "dvfs_pwm_px0";
952 nvidia,function = "cldvfs";
953 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
954 nvidia,tristate = <TEGRA_PIN_DISABLE>;
955 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
956 };
957 gpio_x1_aud_px1 {
958 nvidia,pins = "gpio_x1_aud_px1";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]959 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]960 nvidia,tristate = <TEGRA_PIN_ENABLE>;
961 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]962 };
963 dvfs_clk_px2 {
964 nvidia,pins = "dvfs_clk_px2";
965 nvidia,function = "cldvfs";
966 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
967 nvidia,tristate = <TEGRA_PIN_DISABLE>;
968 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
969 };
970 gpio_x3_aud_px3 {
971 nvidia,pins = "gpio_x3_aud_px3";
972 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]973 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
974 nvidia,tristate = <TEGRA_PIN_ENABLE>;
975 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]976 };
977 gpio_x4_aud_px4 {
978 nvidia,pins = "gpio_x4_aud_px4";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]979 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]980 nvidia,tristate = <TEGRA_PIN_ENABLE>;
981 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]982 };
983 gpio_x5_aud_px5 {
984 nvidia,pins = "gpio_x5_aud_px5";
985 nvidia,function = "rsvd4";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]986 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
987 nvidia,tristate = <TEGRA_PIN_ENABLE>;
988 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]989 };
990 gpio_x6_aud_px6 {
991 nvidia,pins = "gpio_x6_aud_px6";
992 nvidia,function = "gmi";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]993 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
994 nvidia,tristate = <TEGRA_PIN_ENABLE>;
995 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]996 };
997 gpio_x7_aud_px7 {
998 nvidia,pins = "gpio_x7_aud_px7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]999 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1000 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1001 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1002 };
1003 ulpi_clk_py0 {
1004 nvidia,pins = "ulpi_clk_py0";
1005 nvidia,function = "spi1";
1006 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1007 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1008 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1009 };
1010 ulpi_dir_py1 {
1011 nvidia,pins = "ulpi_dir_py1";
1012 nvidia,function = "spi1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1013 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1014 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1015 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1016 };
1017 ulpi_nxt_py2 {
1018 nvidia,pins = "ulpi_nxt_py2";
1019 nvidia,function = "spi1";
1020 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1021 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1022 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1023 };
1024 ulpi_stp_py3 {
1025 nvidia,pins = "ulpi_stp_py3";
1026 nvidia,function = "spi1";
1027 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1028 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1029 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1030 };
1031 sdmmc1_dat3_py4 {
1032 nvidia,pins = "sdmmc1_dat3_py4";
1033 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1034 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1035 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1036 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1037 };
1038 sdmmc1_dat2_py5 {
1039 nvidia,pins = "sdmmc1_dat2_py5";
1040 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1041 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1042 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1043 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1044 };
1045 sdmmc1_dat1_py6 {
1046 nvidia,pins = "sdmmc1_dat1_py6";
1047 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1048 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1049 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1050 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1051 };
1052 sdmmc1_dat0_py7 {
1053 nvidia,pins = "sdmmc1_dat0_py7";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1054 nvidia,function = "rsvd2";
1055 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1056 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1057 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1058 };
1059 sdmmc1_clk_pz0 {
1060 nvidia,pins = "sdmmc1_clk_pz0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1061 nvidia,function = "rsvd3";
1062 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1063 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1064 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1065 };
1066 sdmmc1_cmd_pz1 {
1067 nvidia,pins = "sdmmc1_cmd_pz1";
1068 nvidia,function = "sdmmc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1069 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1070 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1071 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1072 };
1073 pwr_i2c_scl_pz6 {
1074 nvidia,pins = "pwr_i2c_scl_pz6";
1075 nvidia,function = "i2cpwr";
1076 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1077 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1078 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1079 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1080 };
1081 pwr_i2c_sda_pz7 {
1082 nvidia,pins = "pwr_i2c_sda_pz7";
1083 nvidia,function = "i2cpwr";
1084 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1085 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1086 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1087 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1088 };
1089 sdmmc4_dat0_paa0 {
1090 nvidia,pins = "sdmmc4_dat0_paa0";
1091 nvidia,function = "sdmmc4";
1092 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1093 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1094 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1095 };
1096 sdmmc4_dat1_paa1 {
1097 nvidia,pins = "sdmmc4_dat1_paa1";
1098 nvidia,function = "sdmmc4";
1099 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1100 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1102 };
1103 sdmmc4_dat2_paa2 {
1104 nvidia,pins = "sdmmc4_dat2_paa2";
1105 nvidia,function = "sdmmc4";
1106 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1108 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1109 };
1110 sdmmc4_dat3_paa3 {
1111 nvidia,pins = "sdmmc4_dat3_paa3";
1112 nvidia,function = "sdmmc4";
1113 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1115 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1116 };
1117 sdmmc4_dat4_paa4 {
1118 nvidia,pins = "sdmmc4_dat4_paa4";
1119 nvidia,function = "sdmmc4";
1120 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1122 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1123 };
1124 sdmmc4_dat5_paa5 {
1125 nvidia,pins = "sdmmc4_dat5_paa5";
1126 nvidia,function = "sdmmc4";
1127 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1128 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1129 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1130 };
1131 sdmmc4_dat6_paa6 {
1132 nvidia,pins = "sdmmc4_dat6_paa6";
1133 nvidia,function = "sdmmc4";
1134 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1135 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1136 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1137 };
1138 sdmmc4_dat7_paa7 {
1139 nvidia,pins = "sdmmc4_dat7_paa7";
1140 nvidia,function = "sdmmc4";
1141 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1143 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1144 };
1145 pbb0 {
1146 nvidia,pins = "pbb0";
1147 nvidia,function = "vimclk2_alt";
1148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1150 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1151 };
1152 cam_i2c_scl_pbb1 {
1153 nvidia,pins = "cam_i2c_scl_pbb1";
1154 nvidia,function = "i2c3";
1155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1157 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1158 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1159 };
1160 cam_i2c_sda_pbb2 {
1161 nvidia,pins = "cam_i2c_sda_pbb2";
1162 nvidia,function = "i2c3";
1163 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1165 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1166 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1167 };
1168 pbb3 {
1169 nvidia,pins = "pbb3";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1170 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1171 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1172 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1173 };
1174 pbb4 {
1175 nvidia,pins = "pbb4";
1176 nvidia,function = "vgp4";
1177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1179 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1180 };
1181 pbb5 {
1182 nvidia,pins = "pbb5";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1185 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1186 };
1187 pbb6 {
1188 nvidia,pins = "pbb6";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1191 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1192 };
1193 pbb7 {
1194 nvidia,pins = "pbb7";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1196 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1198 };
1199 cam_mclk_pcc0 {
1200 nvidia,pins = "cam_mclk_pcc0";
1201 nvidia,function = "vi_alt3";
1202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1204 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1205 };
1206 pcc1 {
1207 nvidia,pins = "pcc1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1210 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1211 };
1212 pcc2 {
1213 nvidia,pins = "pcc2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1217 };
1218 sdmmc4_clk_pcc4 {
1219 nvidia,pins = "sdmmc4_clk_pcc4";
1220 nvidia,function = "sdmmc4";
1221 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1223 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1224 };
1225 clk2_req_pcc5 {
1226 nvidia,pins = "clk2_req_pcc5";
1227 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1228 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1230 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1231 };
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1232 pex_l0_rst_n_pdd1 {
1233 nvidia,pins = "pex_l0_rst_n_pdd1";
1234 nvidia,function = "pe0";
1235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1237 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1238 };
1239 pex_l0_clkreq_n_pdd2 {
1240 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1241 nvidia,function = "pe0";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1242 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1243 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1244 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1245 };
1246 pex_wake_n_pdd3 {
1247 nvidia,pins = "pex_wake_n_pdd3";
1248 nvidia,function = "pe";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1249 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1250 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1251 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1252 };
1253 pex_l1_rst_n_pdd5 {
1254 nvidia,pins = "pex_l1_rst_n_pdd5";
1255 nvidia,function = "pe1";
1256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1258 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1259 };
1260 pex_l1_clkreq_n_pdd6 {
1261 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1262 nvidia,function = "pe1";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenb0da12d2014-08-22 15:07:13 -0600[diff] [blame]1265 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1266 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1267 clk3_out_pee0 {
1268 nvidia,pins = "clk3_out_pee0";
1269 nvidia,function = "extperiph3";
1270 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1271 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1272 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1273 };
1274 clk3_req_pee1 {
1275 nvidia,pins = "clk3_req_pee1";
1276 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1277 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1278 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1279 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1280 };
1281 dap_mclk1_req_pee2 {
1282 nvidia,pins = "dap_mclk1_req_pee2";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1285 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1286 };
1287 hdmi_cec_pee3 {
1288 nvidia,pins = "hdmi_cec_pee3";
1289 nvidia,function = "cec";
1290 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1291 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1292 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1293 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1294 };
1295 sdmmc3_clk_lb_out_pee4 {
1296 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1297 nvidia,function = "sdmmc3";
1298 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1299 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1300 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1301 };
1302 sdmmc3_clk_lb_in_pee5 {
1303 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
1304 nvidia,function = "sdmmc3";
1305 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1306 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1308 };
1309 dp_hpd_pff0 {
1310 nvidia,pins = "dp_hpd_pff0";
1311 nvidia,function = "dp";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1313 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1314 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1315 };
1316 usb_vbus_en2_pff1 {
1317 nvidia,pins = "usb_vbus_en2_pff1";
1318 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1319 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1320 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1321 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1322 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1323 };
1324 pff2 {
1325 nvidia,pins = "pff2";
1326 nvidia,function = "rsvd2";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1327 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1328 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1329 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1330 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1331 };
1332 core_pwr_req {
1333 nvidia,pins = "core_pwr_req";
1334 nvidia,function = "pwron";
1335 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1336 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1337 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1338 };
1339 cpu_pwr_req {
1340 nvidia,pins = "cpu_pwr_req";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1341 nvidia,function = "cpu";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1342 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1343 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1345 };
1346 pwr_int_n {
1347 nvidia,pins = "pwr_int_n";
1348 nvidia,function = "pmi";
1349 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1350 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1351 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1352 };
1353 reset_out_n {
1354 nvidia,pins = "reset_out_n";
1355 nvidia,function = "reset_out_n";
1356 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1359 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1360 clk_32k_in {
1361 nvidia,pins = "clk_32k_in";
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1362 nvidia,function = "clk";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1363 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenfb816642015-02-17 11:57:45 -0700[diff] [blame]1364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1365 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1366 };
1367 jtag_rtck {
1368 nvidia,pins = "jtag_rtck";
1369 nvidia,function = "rtck";
1370 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1373 };
Stephen Warrenaee7a742016-06-21 12:51:49 -0600[diff] [blame]1374 dsi_b {
1375 nvidia,pins = "mipi_pad_ctrl_dsi_b";
1376 nvidia,function = "dsi_b";
1377 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1378 };
1379 };
1380
Ralf Ramsauerc90bb7b2016-01-26 17:59:18 +0100[diff] [blame]1381 /*
1382 * First high speed UART, exposed on the expansion connector J3A2
1383 * Pin 41: BR_UART1_TXD
1384 * Pin 44: BR_UART1_RXD
1385 */
Olof Johanssond8b795f2016-09-07 21:16:40 -0700[diff] [blame]1386 serial@70006000 {
Ralf Ramsauerc90bb7b2016-01-26 17:59:18 +0100[diff] [blame]1387 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1388 status = "okay";
1389 };
1390
1391 /*
1392 * Second high speed UART, exposed on the expansion connector J3A2
1393 * Pin 65: UART2_RXD
1394 * Pin 68: UART2_TXD
1395 * Pin 71: UART2_CTS_L
1396 * Pin 74: UART2_RTS_L
1397 */
Olof Johanssond8b795f2016-09-07 21:16:40 -0700[diff] [blame]1398 serial@70006040 {
Ralf Ramsauerc90bb7b2016-01-26 17:59:18 +0100[diff] [blame]1399 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1400 status = "okay";
1401 };
1402
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1403 /* DB9 serial port */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1404 serial@70006300 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1405 status = "okay";
1406 };
1407
1408 /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1409 i2c@7000c000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1410 status = "okay";
1411 clock-frequency = <100000>;
1412
Stephen Warren98de7442014-04-25 10:12:42 -0600[diff] [blame]1413 rt5639: audio-codec@1c {
1414 compatible = "realtek,rt5639";
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1415 reg = <0x1c>;
1416 interrupt-parent = <&gpio>;
1417 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
1418 realtek,ldo1-en-gpios =
1419 <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
1420 };
1421
1422 temperature-sensor@4c {
1423 compatible = "ti,tmp451";
1424 reg = <0x4c>;
1425 interrupt-parent = <&gpio>;
1426 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1427 };
1428
1429 eeprom@56 {
1430 compatible = "atmel,24c02";
1431 reg = <0x56>;
1432 pagesize = <8>;
1433 };
1434 };
1435
1436 /* Expansion GEN2_I2C_* */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1437 i2c@7000c400 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1438 status = "okay";
1439 clock-frequency = <100000>;
1440 };
1441
1442 /* Expansion CAM_I2C_* */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1443 i2c@7000c500 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1444 status = "okay";
1445 clock-frequency = <100000>;
1446 };
1447
1448 /* HDMI DDC */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1449 hdmi_ddc: i2c@7000c700 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1450 status = "okay";
1451 clock-frequency = <100000>;
1452 };
1453
1454 /* Expansion PWR_I2C_*, on-board components */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1455 i2c@7000d000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1456 status = "okay";
1457 clock-frequency = <400000>;
1458
1459 pmic: pmic@40 {
1460 compatible = "ams,as3722";
1461 reg = <0x40>;
1462 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1463
1464 ams,system-power-controller;
1465
1466 #interrupt-cells = <2>;
1467 interrupt-controller;
1468
1469 gpio-controller;
1470 #gpio-cells = <2>;
1471
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&as3722_default>;
1474
1475 as3722_default: pinmux {
1476 gpio0 {
1477 pins = "gpio0";
1478 function = "gpio";
1479 bias-pull-down;
1480 };
1481
1482 gpio1_2_4_7 {
1483 pins = "gpio1", "gpio2", "gpio4", "gpio7";
1484 function = "gpio";
1485 bias-pull-up;
1486 };
1487
1488 gpio3_5_6 {
1489 pins = "gpio3", "gpio5", "gpio6";
1490 bias-high-impedance;
1491 };
1492 };
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1493
1494 regulators {
1495 vsup-sd2-supply = <&vdd_5v0_sys>;
1496 vsup-sd3-supply = <&vdd_5v0_sys>;
1497 vsup-sd4-supply = <&vdd_5v0_sys>;
1498 vsup-sd5-supply = <&vdd_5v0_sys>;
1499 vin-ldo0-supply = <&vdd_1v35_lp0>;
1500 vin-ldo1-6-supply = <&vdd_3v3_run>;
1501 vin-ldo2-5-7-supply = <&vddio_1v8>;
1502 vin-ldo3-4-supply = <&vdd_3v3_sys>;
1503 vin-ldo9-10-supply = <&vdd_5v0_sys>;
1504 vin-ldo11-supply = <&vdd_3v3_run>;
1505
Tuomas Tynkkynen9be1e472015-05-13 17:58:45 +0300[diff] [blame]1506 vdd_cpu: sd0 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1507 regulator-name = "+VDD_CPU_AP";
1508 regulator-min-microvolt = <700000>;
1509 regulator-max-microvolt = <1400000>;
1510 regulator-min-microamp = <3500000>;
1511 regulator-max-microamp = <3500000>;
1512 regulator-always-on;
1513 regulator-boot-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1514 ams,ext-control = <2>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1515 };
1516
1517 sd1 {
1518 regulator-name = "+VDD_CORE";
1519 regulator-min-microvolt = <700000>;
1520 regulator-max-microvolt = <1350000>;
1521 regulator-min-microamp = <2500000>;
1522 regulator-max-microamp = <2500000>;
1523 regulator-always-on;
1524 regulator-boot-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1525 ams,ext-control = <1>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1526 };
1527
1528 vdd_1v35_lp0: sd2 {
1529 regulator-name = "+1.35V_LP0(sd2)";
1530 regulator-min-microvolt = <1350000>;
1531 regulator-max-microvolt = <1350000>;
1532 regulator-always-on;
1533 regulator-boot-on;
1534 };
1535
1536 sd3 {
1537 regulator-name = "+1.35V_LP0(sd3)";
1538 regulator-min-microvolt = <1350000>;
1539 regulator-max-microvolt = <1350000>;
1540 regulator-always-on;
1541 regulator-boot-on;
1542 };
1543
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]1544 vdd_1v05_run: sd4 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1545 regulator-name = "+1.05V_RUN";
1546 regulator-min-microvolt = <1050000>;
1547 regulator-max-microvolt = <1050000>;
1548 };
1549
1550 vddio_1v8: sd5 {
1551 regulator-name = "+1.8V_VDDIO";
1552 regulator-min-microvolt = <1800000>;
1553 regulator-max-microvolt = <1800000>;
1554 regulator-boot-on;
1555 regulator-always-on;
1556 };
1557
Alexandre Courbot21fa1962015-07-01 18:13:47 +0900[diff] [blame]1558 vdd_gpu: sd6 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1559 regulator-name = "+VDD_GPU_AP";
1560 regulator-min-microvolt = <650000>;
1561 regulator-max-microvolt = <1200000>;
1562 regulator-min-microamp = <3500000>;
1563 regulator-max-microamp = <3500000>;
1564 regulator-boot-on;
1565 regulator-always-on;
1566 };
1567
Thierry Reding8e2b9e42014-09-17 10:02:45 -0600[diff] [blame]1568 avdd_1v05_run: ldo0 {
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1569 regulator-name = "+1.05V_RUN_AVDD";
1570 regulator-min-microvolt = <1050000>;
1571 regulator-max-microvolt = <1050000>;
1572 regulator-boot-on;
1573 regulator-always-on;
Tuomas Tynkkynenee913f72014-07-09 21:53:17 +0300[diff] [blame]1574 ams,ext-control = <1>;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1575 };
1576
1577 ldo1 {
1578 regulator-name = "+1.8V_RUN_CAM";
1579 regulator-min-microvolt = <1800000>;
1580 regulator-max-microvolt = <1800000>;
1581 };
1582
1583 ldo2 {
1584 regulator-name = "+1.2V_GEN_AVDD";
1585 regulator-min-microvolt = <1200000>;
1586 regulator-max-microvolt = <1200000>;
1587 regulator-boot-on;
1588 regulator-always-on;
1589 };
1590
1591 ldo3 {
1592 regulator-name = "+1.05V_LP0_VDD_RTC";
1593 regulator-min-microvolt = <1000000>;
1594 regulator-max-microvolt = <1000000>;
1595 regulator-boot-on;
1596 regulator-always-on;
1597 ams,enable-tracking;
1598 };
1599
1600 ldo4 {
1601 regulator-name = "+2.8V_RUN_CAM";
1602 regulator-min-microvolt = <2800000>;
1603 regulator-max-microvolt = <2800000>;
1604 };
1605
1606 ldo5 {
1607 regulator-name = "+1.2V_RUN_CAM_FRONT";
1608 regulator-min-microvolt = <1200000>;
1609 regulator-max-microvolt = <1200000>;
1610 };
1611
1612 vddio_sdmmc3: ldo6 {
1613 regulator-name = "+VDDIO_SDMMC3";
1614 regulator-min-microvolt = <1800000>;
1615 regulator-max-microvolt = <3300000>;
1616 };
1617
1618 ldo7 {
1619 regulator-name = "+1.05V_RUN_CAM_REAR";
1620 regulator-min-microvolt = <1050000>;
1621 regulator-max-microvolt = <1050000>;
1622 };
1623
1624 ldo9 {
1625 regulator-name = "+3.3V_RUN_TOUCH";
1626 regulator-min-microvolt = <2800000>;
1627 regulator-max-microvolt = <2800000>;
1628 };
1629
1630 ldo10 {
1631 regulator-name = "+2.8V_RUN_CAM_AF";
1632 regulator-min-microvolt = <2800000>;
1633 regulator-max-microvolt = <2800000>;
1634 };
1635
1636 ldo11 {
1637 regulator-name = "+1.8V_RUN_VPP_FUSE";
1638 regulator-min-microvolt = <1800000>;
1639 regulator-max-microvolt = <1800000>;
1640 };
1641 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1642 };
1643 };
1644
1645 /* Expansion TS_SPI_* */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1646 spi@7000d400 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1647 status = "okay";
1648 };
1649
1650 /* Internal SPI */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1651 spi@7000da00 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1652 status = "okay";
1653 spi-max-frequency = <25000000>;
1654 spi-flash@0 {
1655 compatible = "winbond,w25q32dw";
1656 reg = <0>;
1657 spi-max-frequency = <20000000>;
1658 };
1659 };
1660
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1661 pmc@7000e400 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1662 nvidia,invert-interrupt;
1663 nvidia,suspend-mode = <1>;
1664 nvidia,cpu-pwr-good-time = <500>;
1665 nvidia,cpu-pwr-off-time = <300>;
1666 nvidia,core-pwr-good-time = <641 3845>;
1667 nvidia,core-pwr-off-time = <61036>;
1668 nvidia,core-power-req-active-high;
1669 nvidia,sys-clock-req-active-high;
Mikko Perttunen9c963302015-01-06 12:52:57 +0200[diff] [blame]1670
1671 i2c-thermtrip {
1672 nvidia,i2c-controller-id = <4>;
1673 nvidia,bus-addr = <0x40>;
1674 nvidia,reg-addr = <0x36>;
1675 nvidia,reg-data = <0x2>;
1676 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1677 };
1678
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]1679 /* Serial ATA */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1680 sata@70020000 {
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]1681 status = "okay";
1682
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1683 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1684 phy-names = "sata-0";
1685
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]1686 hvdd-supply = <&vdd_3v3_lp0>;
1687 vddio-supply = <&vdd_1v05_run>;
1688 avdd-supply = <&vdd_1v05_run>;
1689
1690 target-5v-supply = <&vdd_5v0_sata>;
1691 target-12v-supply = <&vdd_12v0_sata>;
1692 };
1693
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1694 hda@70030000 {
Thierry Reding4c844722014-05-22 09:38:31 +0200[diff] [blame]1695 status = "okay";
1696 };
1697
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1698 usb@70090000 {
1699 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
1700 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
1701 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
1702 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1703 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
Thierry Reding62b8db02014-06-19 13:37:10 +0200[diff] [blame]1704
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1705 avddio-pex-supply = <&vdd_1v05_run>;
1706 dvddio-pex-supply = <&vdd_1v05_run>;
1707 avdd-usb-supply = <&vdd_3v3_lp0>;
1708 avdd-pll-utmip-supply = <&vddio_1v8>;
1709 avdd-pll-erefe-supply = <&avdd_1v05_run>;
1710 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
1711 hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
1712 hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
1713
1714 status = "okay";
1715 };
1716
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1717 padctl@7009f000 {
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1718 status = "okay";
1719
1720 pads {
1721 usb2 {
1722 status = "okay";
1723
1724 lanes {
1725 usb2-0 {
Thierry Reding96f1abf2017-08-16 13:32:44 +0300[diff] [blame]1726 nvidia,function = "snps";
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1727 status = "okay";
1728 };
1729
1730 usb2-1 {
1731 nvidia,function = "xusb";
1732 status = "okay";
1733 };
1734
1735 usb2-2 {
1736 nvidia,function = "xusb";
1737 status = "okay";
1738 };
1739 };
Thierry Reding62b8db02014-06-19 13:37:10 +0200[diff] [blame]1740 };
1741
1742 pcie {
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1743 status = "okay";
1744
1745 lanes {
1746 pcie-0 {
1747 nvidia,function = "usb3-ss";
1748 status = "okay";
1749 };
1750
1751 pcie-2 {
1752 nvidia,function = "pcie";
1753 status = "okay";
1754 };
1755
1756 pcie-4 {
1757 nvidia,function = "pcie";
1758 status = "okay";
1759 };
1760 };
Thierry Reding62b8db02014-06-19 13:37:10 +0200[diff] [blame]1761 };
1762
1763 sata {
Thierry Reding87c68112015-11-11 18:22:27 +0100[diff] [blame]1764 status = "okay";
1765
1766 lanes {
1767 sata-0 {
1768 nvidia,function = "sata";
1769 status = "okay";
1770 };
1771 };
1772 };
1773 };
1774
1775 ports {
1776 /* Micro A/B */
1777 usb2-0 {
1778 status = "okay";
1779 mode = "otg";
1780 };
1781
1782 /* Mini PCIe */
1783 usb2-1 {
1784 status = "okay";
1785 mode = "host";
1786 };
1787
1788 /* USB3 */
1789 usb2-2 {
1790 status = "okay";
1791 mode = "host";
1792
1793 vbus-supply = <&vdd_usb3_vbus>;
1794 };
1795
1796 usb3-0 {
1797 nvidia,usb2-companion = <2>;
1798 status = "okay";
Thierry Reding62b8db02014-06-19 13:37:10 +0200[diff] [blame]1799 };
1800 };
1801 };
1802
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1803 /* SD card */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1804 sdhci@700b0400 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1805 status = "okay";
1806 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1807 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
Stephen Warren215f21c2014-04-28 11:05:57 -0600[diff] [blame]1808 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1809 bus-width = <4>;
Stephen Warren92607642014-04-16 10:34:18 -0600[diff] [blame]1810 vqmmc-supply = <&vddio_sdmmc3>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1811 };
1812
1813 /* eMMC */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1814 sdhci@700b0600 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1815 status = "okay";
1816 bus-width = <8>;
Lucas Stach33f34f02014-06-03 14:48:46 +0200[diff] [blame]1817 non-removable;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1818 };
1819
Tuomas Tynkkynen9be1e472015-05-13 17:58:45 +0300[diff] [blame]1820 /* CPU DFLL clock */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1821 clock@70110000 {
Tuomas Tynkkynen9be1e472015-05-13 17:58:45 +0300[diff] [blame]1822 status = "okay";
1823 vdd-cpu-supply = <&vdd_cpu>;
1824 nvidia,i2c-fs-rate = <400000>;
1825 };
1826
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1827 ahub@70300000 {
1828 i2s@70301100 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1829 status = "okay";
1830 };
1831 };
1832
Thierry Reding96f1abf2017-08-16 13:32:44 +0300[diff] [blame]1833 usb@7d000000 {
1834 compatible = "nvidia,tegra124-udc";
1835 status = "okay";
1836 dr_mode = "peripheral";
1837 };
1838
1839 usb-phy@7d000000 {
1840 status = "okay";
1841 };
1842
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1843 /* mini-PCIe USB */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1844 usb@7d004000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1845 status = "okay";
1846 };
1847
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1848 usb-phy@7d004000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1849 status = "okay";
1850 };
1851
1852 /* USB A connector */
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1853 usb@7d008000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1854 status = "okay";
1855 };
1856
Marcel Ziswilerb5896f62016-06-30 00:21:37 +0200[diff] [blame]1857 usb-phy@7d008000 {
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1858 status = "okay";
1859 vbus-supply = <&vdd_usb3_vbus>;
1860 };
1861
1862 clocks {
1863 compatible = "simple-bus";
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1866
1867 clk32k_in: clock@0 {
1868 compatible = "fixed-clock";
1869 reg = <0>;
1870 #clock-cells = <0>;
1871 clock-frequency = <32768>;
1872 };
1873 };
1874
Mikko Perttunenee9f1062015-05-13 17:58:50 +0300[diff] [blame]1875 cpus {
1876 cpu@0 {
1877 vdd-cpu-supply = <&vdd_cpu>;
1878 };
1879 };
1880
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1881 gpio-keys {
1882 compatible = "gpio-keys";
1883
1884 power {
1885 label = "Power";
1886 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1887 linux,code = <KEY_POWER>;
1888 debounce-interval = <10>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000[diff] [blame]1889 wakeup-source;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1890 };
1891 };
1892
1893 regulators {
1894 compatible = "simple-bus";
1895 #address-cells = <1>;
1896 #size-cells = <0>;
1897
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1898 vdd_mux: regulator@0 {
1899 compatible = "regulator-fixed";
1900 reg = <0>;
1901 regulator-name = "+VDD_MUX";
1902 regulator-min-microvolt = <12000000>;
1903 regulator-max-microvolt = <12000000>;
1904 regulator-always-on;
1905 regulator-boot-on;
1906 };
1907
1908 vdd_5v0_sys: regulator@1 {
1909 compatible = "regulator-fixed";
1910 reg = <1>;
1911 regulator-name = "+5V_SYS";
1912 regulator-min-microvolt = <5000000>;
1913 regulator-max-microvolt = <5000000>;
1914 regulator-always-on;
1915 regulator-boot-on;
1916 vin-supply = <&vdd_mux>;
1917 };
1918
1919 vdd_3v3_sys: regulator@2 {
1920 compatible = "regulator-fixed";
1921 reg = <2>;
1922 regulator-name = "+3.3V_SYS";
1923 regulator-min-microvolt = <3300000>;
1924 regulator-max-microvolt = <3300000>;
1925 regulator-always-on;
1926 regulator-boot-on;
1927 vin-supply = <&vdd_mux>;
1928 };
1929
1930 vdd_3v3_run: regulator@3 {
1931 compatible = "regulator-fixed";
1932 reg = <3>;
1933 regulator-name = "+3.3V_RUN";
1934 regulator-min-microvolt = <3300000>;
1935 regulator-max-microvolt = <3300000>;
1936 regulator-always-on;
1937 regulator-boot-on;
1938 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1939 enable-active-high;
1940 vin-supply = <&vdd_3v3_sys>;
1941 };
1942
1943 vdd_3v3_hdmi: regulator@4 {
1944 compatible = "regulator-fixed";
1945 reg = <4>;
1946 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1947 regulator-min-microvolt = <3300000>;
1948 regulator-max-microvolt = <3300000>;
1949 vin-supply = <&vdd_3v3_run>;
1950 };
1951
1952 vdd_usb1_vbus: regulator@7 {
1953 compatible = "regulator-fixed";
1954 reg = <7>;
1955 regulator-name = "+USB0_VBUS_SW";
1956 regulator-min-microvolt = <5000000>;
1957 regulator-max-microvolt = <5000000>;
1958 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1959 enable-active-high;
1960 gpio-open-drain;
1961 vin-supply = <&vdd_5v0_sys>;
1962 };
1963
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1964 vdd_usb3_vbus: regulator@8 {
1965 compatible = "regulator-fixed";
1966 reg = <8>;
1967 regulator-name = "+5V_USB_HS";
1968 regulator-min-microvolt = <5000000>;
1969 regulator-max-microvolt = <5000000>;
1970 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1971 enable-active-high;
1972 gpio-open-drain;
Stephen Warren22b35772014-03-24 18:04:43 -0600[diff] [blame]1973 vin-supply = <&vdd_5v0_sys>;
1974 };
1975
1976 vdd_3v3_lp0: regulator@10 {
1977 compatible = "regulator-fixed";
1978 reg = <10>;
1979 regulator-name = "+3.3V_LP0";
1980 regulator-min-microvolt = <3300000>;
1981 regulator-max-microvolt = <3300000>;
1982 regulator-always-on;
1983 regulator-boot-on;
1984 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1985 enable-active-high;
1986 vin-supply = <&vdd_3v3_sys>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]1987 };
Thierry Reding6054dd32014-04-25 17:44:47 +0200[diff] [blame]1988
1989 vdd_hdmi_pll: regulator@11 {
1990 compatible = "regulator-fixed";
1991 reg = <11>;
1992 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1993 regulator-min-microvolt = <1050000>;
1994 regulator-max-microvolt = <1050000>;
1995 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1996 vin-supply = <&vdd_1v05_run>;
1997 };
1998
1999 vdd_5v0_hdmi: regulator@12 {
2000 compatible = "regulator-fixed";
2001 reg = <12>;
2002 regulator-name = "+5V_HDMI_CON";
2003 regulator-min-microvolt = <5000000>;
2004 regulator-max-microvolt = <5000000>;
2005 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
2006 enable-active-high;
2007 vin-supply = <&vdd_5v0_sys>;
2008 };
Mikko Perttunen1b3ce992014-07-16 11:54:18 +0300[diff] [blame]2009
2010 /* Molex power connector */
2011 vdd_5v0_sata: regulator@13 {
2012 compatible = "regulator-fixed";
2013 reg = <13>;
2014 regulator-name = "+5V_SATA";
2015 regulator-min-microvolt = <5000000>;
2016 regulator-max-microvolt = <5000000>;
2017 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
2018 enable-active-high;
2019 vin-supply = <&vdd_5v0_sys>;
2020 };
2021
2022 vdd_12v0_sata: regulator@14 {
2023 compatible = "regulator-fixed";
2024 reg = <14>;
2025 regulator-name = "+12V_SATA";
2026 regulator-min-microvolt = <12000000>;
2027 regulator-max-microvolt = <12000000>;
2028 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
2029 enable-active-high;
2030 vin-supply = <&vdd_mux>;
2031 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]2032 };
2033
2034 sound {
2035 compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
2036 "nvidia,tegra-audio-rt5640";
2037 nvidia,model = "NVIDIA Tegra Jetson TK1";
2038
2039 nvidia,audio-routing =
2040 "Headphones", "HPOR",
2041 "Headphones", "HPOL",
2042 "Mic Jack", "MICBIAS1",
2043 "IN2P", "Mic Jack";
2044
2045 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren98de7442014-04-25 10:12:42 -0600[diff] [blame]2046 nvidia,audio-codec = <&rt5639>;
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]2047
2048 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
2049
2050 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2051 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2052 <&tegra_car TEGRA124_CLK_EXTERN1>;
2053 clock-names = "pll_a", "pll_a_out0", "mclk";
2054 };
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2055
2056 thermal-zones {
2057 cpu {
2058 trips {
Wei Ni40823f82016-05-11 18:20:19 +0800[diff] [blame]2059 cpu-shutdown-trip {
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2060 temperature = <101000>;
2061 hysteresis = <0>;
2062 type = "critical";
2063 };
2064 };
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2065 };
2066
2067 mem {
2068 trips {
Wei Ni40823f82016-05-11 18:20:19 +0800[diff] [blame]2069 mem-shutdown-trip {
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2070 temperature = <101000>;
2071 hysteresis = <0>;
2072 type = "critical";
2073 };
2074 };
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2075 };
2076
2077 gpu {
2078 trips {
Wei Ni40823f82016-05-11 18:20:19 +0800[diff] [blame]2079 gpu-shutdown-trip {
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2080 temperature = <101000>;
2081 hysteresis = <0>;
2082 type = "critical";
2083 };
2084 };
Mikko Perttunened7eac32014-09-26 12:43:12 +0300[diff] [blame]2085 };
2086 };
Stephen Warren15e524a2014-03-19 15:47:53 -0600[diff] [blame]2087};