Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | #include <dt-bindings/input/input.h> |
| 4 | #include "tegra124.dtsi" |
| 5 | |
Mikko Perttunen | 6e72cf0 | 2015-03-12 15:48:01 +0100 | [diff] [blame] | 6 | #include "tegra124-jetson-tk1-emc.dtsi" |
| 7 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 8 | / { |
| 9 | model = "NVIDIA Tegra124 Jetson TK1"; |
| 10 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; |
| 11 | |
| 12 | aliases { |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 13 | rtc0 = "/i2c@7000d000/pmic@40"; |
| 14 | rtc1 = "/rtc@7000e000"; |
Ralf Ramsauer | c90bb7b | 2016-01-26 17:59:18 +0100 | [diff] [blame] | 15 | |
| 16 | /* This order keeps the mapping DB9 connector <-> ttyS0 */ |
Olof Johansson | c4574aa | 2014-11-11 12:49:30 -0800 | [diff] [blame] | 17 | serial0 = &uartd; |
Ralf Ramsauer | c90bb7b | 2016-01-26 17:59:18 +0100 | [diff] [blame] | 18 | serial1 = &uarta; |
| 19 | serial2 = &uartb; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 20 | }; |
| 21 | |
Jon Hunter | f5bbb32 | 2016-02-09 13:51:59 +0000 | [diff] [blame] | 22 | chosen { |
| 23 | stdout-path = "serial0:115200n8"; |
| 24 | }; |
| 25 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 26 | memory { |
| 27 | reg = <0x0 0x80000000 0x0 0x80000000>; |
| 28 | }; |
| 29 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 30 | pcie-controller@01003000 { |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 31 | status = "okay"; |
| 32 | |
| 33 | avddio-pex-supply = <&vdd_1v05_run>; |
| 34 | dvddio-pex-supply = <&vdd_1v05_run>; |
| 35 | avdd-pex-pll-supply = <&vdd_1v05_run>; |
| 36 | hvdd-pex-supply = <&vdd_3v3_lp0>; |
| 37 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; |
| 38 | vddio-pex-ctl-supply = <&vdd_3v3_lp0>; |
| 39 | avdd-pll-erefe-supply = <&avdd_1v05_run>; |
| 40 | |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 41 | /* Mini PCIe */ |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 42 | pci@1,0 { |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 43 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 44 | phy-names = "pcie-0"; |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 45 | status = "okay"; |
| 46 | }; |
| 47 | |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 48 | /* Gigabit Ethernet */ |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 49 | pci@2,0 { |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 50 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 51 | phy-names = "pcie-0"; |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 52 | status = "okay"; |
| 53 | }; |
| 54 | }; |
| 55 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 56 | host1x@50000000 { |
| 57 | hdmi@54280000 { |
Thierry Reding | 6054dd3 | 2014-04-25 17:44:47 +0200 | [diff] [blame] | 58 | status = "okay"; |
| 59 | |
| 60 | hdmi-supply = <&vdd_5v0_hdmi>; |
| 61 | pll-supply = <&vdd_hdmi_pll>; |
| 62 | vdd-supply = <&vdd_3v3_hdmi>; |
| 63 | |
| 64 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 65 | nvidia,hpd-gpio = |
| 66 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| 67 | }; |
| 68 | }; |
| 69 | |
Alexandre Courbot | 21fa196 | 2015-07-01 18:13:47 +0900 | [diff] [blame] | 70 | gpu@0,57000000 { |
| 71 | /* |
| 72 | * Node left disabled on purpose - the bootloader will enable |
| 73 | * it after having set the VPR up |
| 74 | */ |
| 75 | vdd-supply = <&vdd_gpu>; |
| 76 | }; |
| 77 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 78 | pinmux: pinmux@70000868 { |
Stephen Warren | 6dbaff2 | 2014-09-03 09:42:06 -0600 | [diff] [blame] | 79 | pinctrl-names = "boot"; |
| 80 | pinctrl-0 = <&state_boot>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 81 | |
Stephen Warren | 6dbaff2 | 2014-09-03 09:42:06 -0600 | [diff] [blame] | 82 | state_boot: pinmux { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 83 | clk_32k_out_pa0 { |
| 84 | nvidia,pins = "clk_32k_out_pa0"; |
| 85 | nvidia,function = "soc"; |
| 86 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 87 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 88 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 89 | }; |
| 90 | uart3_cts_n_pa1 { |
| 91 | nvidia,pins = "uart3_cts_n_pa1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 92 | nvidia,function = "gmi"; |
| 93 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 94 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 95 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 96 | }; |
| 97 | dap2_fs_pa2 { |
| 98 | nvidia,pins = "dap2_fs_pa2"; |
| 99 | nvidia,function = "i2s1"; |
| 100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 103 | }; |
| 104 | dap2_sclk_pa3 { |
| 105 | nvidia,pins = "dap2_sclk_pa3"; |
| 106 | nvidia,function = "i2s1"; |
| 107 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 109 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 110 | }; |
| 111 | dap2_din_pa4 { |
| 112 | nvidia,pins = "dap2_din_pa4"; |
| 113 | nvidia,function = "i2s1"; |
| 114 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 115 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 116 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 117 | }; |
| 118 | dap2_dout_pa5 { |
| 119 | nvidia,pins = "dap2_dout_pa5"; |
| 120 | nvidia,function = "i2s1"; |
| 121 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 123 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 124 | }; |
| 125 | sdmmc3_clk_pa6 { |
| 126 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 127 | nvidia,function = "sdmmc3"; |
| 128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 130 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 131 | }; |
| 132 | sdmmc3_cmd_pa7 { |
| 133 | nvidia,pins = "sdmmc3_cmd_pa7"; |
| 134 | nvidia,function = "sdmmc3"; |
| 135 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 138 | }; |
| 139 | pb0 { |
| 140 | nvidia,pins = "pb0"; |
| 141 | nvidia,function = "uartd"; |
| 142 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 143 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 144 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 145 | }; |
| 146 | pb1 { |
| 147 | nvidia,pins = "pb1"; |
| 148 | nvidia,function = "uartd"; |
| 149 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 150 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 152 | }; |
| 153 | sdmmc3_dat3_pb4 { |
| 154 | nvidia,pins = "sdmmc3_dat3_pb4"; |
| 155 | nvidia,function = "sdmmc3"; |
| 156 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 157 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 158 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 159 | }; |
| 160 | sdmmc3_dat2_pb5 { |
| 161 | nvidia,pins = "sdmmc3_dat2_pb5"; |
| 162 | nvidia,function = "sdmmc3"; |
| 163 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 164 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 166 | }; |
| 167 | sdmmc3_dat1_pb6 { |
| 168 | nvidia,pins = "sdmmc3_dat1_pb6"; |
| 169 | nvidia,function = "sdmmc3"; |
| 170 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 173 | }; |
| 174 | sdmmc3_dat0_pb7 { |
| 175 | nvidia,pins = "sdmmc3_dat0_pb7"; |
| 176 | nvidia,function = "sdmmc3"; |
| 177 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 179 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 180 | }; |
| 181 | uart3_rts_n_pc0 { |
| 182 | nvidia,pins = "uart3_rts_n_pc0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 183 | nvidia,function = "gmi"; |
| 184 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 185 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 187 | }; |
| 188 | uart2_txd_pc2 { |
| 189 | nvidia,pins = "uart2_txd_pc2"; |
| 190 | nvidia,function = "irda"; |
| 191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 193 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 194 | }; |
| 195 | uart2_rxd_pc3 { |
| 196 | nvidia,pins = "uart2_rxd_pc3"; |
| 197 | nvidia,function = "irda"; |
| 198 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 199 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 201 | }; |
| 202 | gen1_i2c_scl_pc4 { |
| 203 | nvidia,pins = "gen1_i2c_scl_pc4"; |
| 204 | nvidia,function = "i2c1"; |
| 205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 206 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 207 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 208 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 209 | }; |
| 210 | gen1_i2c_sda_pc5 { |
| 211 | nvidia,pins = "gen1_i2c_sda_pc5"; |
| 212 | nvidia,function = "i2c1"; |
| 213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 215 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 216 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 217 | }; |
| 218 | pc7 { |
| 219 | nvidia,pins = "pc7"; |
| 220 | nvidia,function = "rsvd1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 221 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 222 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 223 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 224 | }; |
| 225 | pg0 { |
| 226 | nvidia,pins = "pg0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 227 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 229 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 230 | }; |
| 231 | pg1 { |
| 232 | nvidia,pins = "pg1"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 233 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 235 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 236 | }; |
| 237 | pg2 { |
| 238 | nvidia,pins = "pg2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 239 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 240 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 241 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 242 | }; |
| 243 | pg3 { |
| 244 | nvidia,pins = "pg3"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 246 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 248 | }; |
| 249 | pg4 { |
| 250 | nvidia,pins = "pg4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 251 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 252 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 253 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 254 | }; |
| 255 | pg5 { |
| 256 | nvidia,pins = "pg5"; |
| 257 | nvidia,function = "spi4"; |
| 258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 261 | }; |
| 262 | pg6 { |
| 263 | nvidia,pins = "pg6"; |
| 264 | nvidia,function = "spi4"; |
| 265 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 266 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 267 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 268 | }; |
| 269 | pg7 { |
| 270 | nvidia,pins = "pg7"; |
| 271 | nvidia,function = "spi4"; |
| 272 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 273 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 274 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 275 | }; |
| 276 | ph0 { |
| 277 | nvidia,pins = "ph0"; |
| 278 | nvidia,function = "gmi"; |
| 279 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 280 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 282 | }; |
| 283 | ph1 { |
| 284 | nvidia,pins = "ph1"; |
| 285 | nvidia,function = "pwm1"; |
| 286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 289 | }; |
| 290 | ph2 { |
| 291 | nvidia,pins = "ph2"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 292 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 293 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 294 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 295 | }; |
| 296 | ph3 { |
| 297 | nvidia,pins = "ph3"; |
| 298 | nvidia,function = "gmi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 299 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 300 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 301 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 302 | }; |
| 303 | ph4 { |
| 304 | nvidia,pins = "ph4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 306 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 307 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 308 | }; |
| 309 | ph5 { |
| 310 | nvidia,pins = "ph5"; |
| 311 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 312 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 313 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 314 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 315 | }; |
| 316 | ph6 { |
| 317 | nvidia,pins = "ph6"; |
| 318 | nvidia,function = "gmi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 319 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 320 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 321 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 322 | }; |
| 323 | ph7 { |
| 324 | nvidia,pins = "ph7"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 328 | }; |
| 329 | pi0 { |
| 330 | nvidia,pins = "pi0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 331 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 332 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 333 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 334 | }; |
| 335 | pi1 { |
| 336 | nvidia,pins = "pi1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 338 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 340 | }; |
| 341 | pi2 { |
| 342 | nvidia,pins = "pi2"; |
| 343 | nvidia,function = "rsvd4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 344 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 345 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 346 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 347 | }; |
| 348 | pi3 { |
| 349 | nvidia,pins = "pi3"; |
| 350 | nvidia,function = "spi4"; |
| 351 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 352 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 353 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 354 | }; |
| 355 | pi4 { |
| 356 | nvidia,pins = "pi4"; |
| 357 | nvidia,function = "gmi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 358 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 359 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 360 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 361 | }; |
| 362 | pi5 { |
| 363 | nvidia,pins = "pi5"; |
| 364 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 365 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 366 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 367 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 368 | }; |
| 369 | pi6 { |
| 370 | nvidia,pins = "pi6"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 372 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 374 | }; |
| 375 | pi7 { |
| 376 | nvidia,pins = "pi7"; |
| 377 | nvidia,function = "rsvd1"; |
| 378 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 379 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 381 | }; |
| 382 | pj0 { |
| 383 | nvidia,pins = "pj0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 384 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 385 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 386 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 387 | }; |
| 388 | pj2 { |
| 389 | nvidia,pins = "pj2"; |
| 390 | nvidia,function = "rsvd1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 391 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 392 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 393 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 394 | }; |
| 395 | uart2_cts_n_pj5 { |
| 396 | nvidia,pins = "uart2_cts_n_pj5"; |
| 397 | nvidia,function = "uartb"; |
| 398 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 399 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 400 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 401 | }; |
| 402 | uart2_rts_n_pj6 { |
| 403 | nvidia,pins = "uart2_rts_n_pj6"; |
| 404 | nvidia,function = "uartb"; |
| 405 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 406 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 407 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 408 | }; |
| 409 | pj7 { |
| 410 | nvidia,pins = "pj7"; |
| 411 | nvidia,function = "uartd"; |
| 412 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 413 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 414 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 415 | }; |
| 416 | pk0 { |
| 417 | nvidia,pins = "pk0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 418 | nvidia,function = "rsvd1"; |
| 419 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 420 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 421 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 422 | }; |
| 423 | pk1 { |
| 424 | nvidia,pins = "pk1"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 425 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 426 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 427 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 428 | }; |
| 429 | pk2 { |
| 430 | nvidia,pins = "pk2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 431 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 432 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 433 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 434 | }; |
| 435 | pk3 { |
| 436 | nvidia,pins = "pk3"; |
| 437 | nvidia,function = "gmi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 438 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 439 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 440 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 441 | }; |
| 442 | pk4 { |
| 443 | nvidia,pins = "pk4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 444 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 445 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 446 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 447 | }; |
| 448 | spdif_out_pk5 { |
| 449 | nvidia,pins = "spdif_out_pk5"; |
| 450 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 451 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 452 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 453 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 454 | }; |
| 455 | spdif_in_pk6 { |
| 456 | nvidia,pins = "spdif_in_pk6"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 457 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 458 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 459 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 460 | }; |
| 461 | pk7 { |
| 462 | nvidia,pins = "pk7"; |
| 463 | nvidia,function = "uartd"; |
| 464 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 465 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 466 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 467 | }; |
| 468 | dap1_fs_pn0 { |
| 469 | nvidia,pins = "dap1_fs_pn0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 470 | nvidia,function = "rsvd4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 471 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 472 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 473 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 474 | }; |
| 475 | dap1_din_pn1 { |
| 476 | nvidia,pins = "dap1_din_pn1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 477 | nvidia,function = "rsvd4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 478 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 479 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 480 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 481 | }; |
| 482 | dap1_dout_pn2 { |
| 483 | nvidia,pins = "dap1_dout_pn2"; |
| 484 | nvidia,function = "sata"; |
| 485 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 486 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 487 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 488 | }; |
| 489 | dap1_sclk_pn3 { |
| 490 | nvidia,pins = "dap1_sclk_pn3"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 491 | nvidia,function = "rsvd4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 492 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 493 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 494 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 495 | }; |
| 496 | usb_vbus_en0_pn4 { |
| 497 | nvidia,pins = "usb_vbus_en0_pn4"; |
| 498 | nvidia,function = "usb"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 499 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 500 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 501 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 502 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 503 | }; |
| 504 | usb_vbus_en1_pn5 { |
| 505 | nvidia,pins = "usb_vbus_en1_pn5"; |
| 506 | nvidia,function = "usb"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 507 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 508 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 509 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 510 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 511 | }; |
| 512 | hdmi_int_pn7 { |
| 513 | nvidia,pins = "hdmi_int_pn7"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 514 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 515 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 516 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 517 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; |
| 518 | }; |
| 519 | ulpi_data7_po0 { |
| 520 | nvidia,pins = "ulpi_data7_po0"; |
| 521 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 522 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 523 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 524 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 525 | }; |
| 526 | ulpi_data0_po1 { |
| 527 | nvidia,pins = "ulpi_data0_po1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 528 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 529 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 530 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 531 | }; |
| 532 | ulpi_data1_po2 { |
| 533 | nvidia,pins = "ulpi_data1_po2"; |
| 534 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 535 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 536 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 537 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 538 | }; |
| 539 | ulpi_data2_po3 { |
| 540 | nvidia,pins = "ulpi_data2_po3"; |
| 541 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 542 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 543 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 544 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 545 | }; |
| 546 | ulpi_data3_po4 { |
| 547 | nvidia,pins = "ulpi_data3_po4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 548 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 549 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 550 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 551 | }; |
| 552 | ulpi_data4_po5 { |
| 553 | nvidia,pins = "ulpi_data4_po5"; |
| 554 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 555 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 556 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 557 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 558 | }; |
| 559 | ulpi_data5_po6 { |
| 560 | nvidia,pins = "ulpi_data5_po6"; |
| 561 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 562 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 563 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 564 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 565 | }; |
| 566 | ulpi_data6_po7 { |
| 567 | nvidia,pins = "ulpi_data6_po7"; |
| 568 | nvidia,function = "ulpi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 569 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 570 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 571 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 572 | }; |
| 573 | dap3_fs_pp0 { |
| 574 | nvidia,pins = "dap3_fs_pp0"; |
| 575 | nvidia,function = "i2s2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 576 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 577 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 578 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 579 | }; |
| 580 | dap3_din_pp1 { |
| 581 | nvidia,pins = "dap3_din_pp1"; |
| 582 | nvidia,function = "i2s2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 583 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 584 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 585 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 586 | }; |
| 587 | dap3_dout_pp2 { |
| 588 | nvidia,pins = "dap3_dout_pp2"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 589 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 590 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 591 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 592 | }; |
| 593 | dap3_sclk_pp3 { |
| 594 | nvidia,pins = "dap3_sclk_pp3"; |
| 595 | nvidia,function = "rsvd3"; |
| 596 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 597 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 598 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 599 | }; |
| 600 | dap4_fs_pp4 { |
| 601 | nvidia,pins = "dap4_fs_pp4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 602 | nvidia,function = "rsvd4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 603 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 604 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 605 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 606 | }; |
| 607 | dap4_din_pp5 { |
| 608 | nvidia,pins = "dap4_din_pp5"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 609 | nvidia,function = "rsvd3"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 610 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 611 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 612 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 613 | }; |
| 614 | dap4_dout_pp6 { |
| 615 | nvidia,pins = "dap4_dout_pp6"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 616 | nvidia,function = "rsvd4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 617 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 618 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 619 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 620 | }; |
| 621 | dap4_sclk_pp7 { |
| 622 | nvidia,pins = "dap4_sclk_pp7"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 623 | nvidia,function = "rsvd3"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 624 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 625 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 626 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 627 | }; |
| 628 | kb_col0_pq0 { |
| 629 | nvidia,pins = "kb_col0_pq0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 630 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 631 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 632 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 633 | }; |
| 634 | kb_col1_pq1 { |
| 635 | nvidia,pins = "kb_col1_pq1"; |
| 636 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 637 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 638 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 639 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 640 | }; |
| 641 | kb_col2_pq2 { |
| 642 | nvidia,pins = "kb_col2_pq2"; |
| 643 | nvidia,function = "rsvd2"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 644 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 645 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 646 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 647 | }; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 648 | kb_col3_pq3 { |
| 649 | nvidia,pins = "kb_col3_pq3"; |
| 650 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 651 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 652 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 653 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 654 | kb_col4_pq4 { |
| 655 | nvidia,pins = "kb_col4_pq4"; |
| 656 | nvidia,function = "sdmmc3"; |
| 657 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 658 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 659 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 660 | }; |
| 661 | kb_col5_pq5 { |
| 662 | nvidia,pins = "kb_col5_pq5"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 663 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 664 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 665 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 666 | }; |
| 667 | kb_col6_pq6 { |
| 668 | nvidia,pins = "kb_col6_pq6"; |
| 669 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 670 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 671 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 672 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 673 | }; |
| 674 | kb_col7_pq7 { |
| 675 | nvidia,pins = "kb_col7_pq7"; |
| 676 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 677 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 678 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 679 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 680 | }; |
| 681 | kb_row0_pr0 { |
| 682 | nvidia,pins = "kb_row0_pr0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 685 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 686 | }; |
| 687 | kb_row1_pr1 { |
| 688 | nvidia,pins = "kb_row1_pr1"; |
| 689 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 690 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 691 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 692 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 693 | }; |
| 694 | kb_row2_pr2 { |
| 695 | nvidia,pins = "kb_row2_pr2"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 696 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 697 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 698 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 699 | }; |
| 700 | kb_row3_pr3 { |
| 701 | nvidia,pins = "kb_row3_pr3"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 702 | nvidia,function = "kbc"; |
| 703 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 704 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 705 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 706 | }; |
| 707 | kb_row4_pr4 { |
| 708 | nvidia,pins = "kb_row4_pr4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 709 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 710 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 711 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 712 | }; |
| 713 | kb_row5_pr5 { |
| 714 | nvidia,pins = "kb_row5_pr5"; |
| 715 | nvidia,function = "rsvd3"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 716 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 717 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 718 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 719 | }; |
| 720 | kb_row6_pr6 { |
| 721 | nvidia,pins = "kb_row6_pr6"; |
| 722 | nvidia,function = "displaya_alt"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 723 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 724 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 725 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 726 | }; |
| 727 | kb_row7_pr7 { |
| 728 | nvidia,pins = "kb_row7_pr7"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 729 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 730 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 731 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 732 | }; |
| 733 | kb_row8_ps0 { |
| 734 | nvidia,pins = "kb_row8_ps0"; |
| 735 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 736 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 737 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 738 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 739 | }; |
| 740 | kb_row9_ps1 { |
| 741 | nvidia,pins = "kb_row9_ps1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 742 | nvidia,function = "uarta"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 743 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 744 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 745 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 746 | }; |
| 747 | kb_row10_ps2 { |
| 748 | nvidia,pins = "kb_row10_ps2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 749 | nvidia,function = "uarta"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 750 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 751 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 752 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 753 | }; |
| 754 | kb_row11_ps3 { |
| 755 | nvidia,pins = "kb_row11_ps3"; |
| 756 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 757 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 758 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 759 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 760 | }; |
| 761 | kb_row12_ps4 { |
| 762 | nvidia,pins = "kb_row12_ps4"; |
| 763 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 764 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 765 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 766 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 767 | }; |
| 768 | kb_row13_ps5 { |
| 769 | nvidia,pins = "kb_row13_ps5"; |
| 770 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 771 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 772 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 773 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 774 | }; |
| 775 | kb_row14_ps6 { |
| 776 | nvidia,pins = "kb_row14_ps6"; |
| 777 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 778 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 781 | }; |
| 782 | kb_row15_ps7 { |
| 783 | nvidia,pins = "kb_row15_ps7"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 784 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 785 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 786 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 787 | }; |
| 788 | kb_row16_pt0 { |
| 789 | nvidia,pins = "kb_row16_pt0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 790 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 791 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 792 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 793 | }; |
| 794 | kb_row17_pt1 { |
| 795 | nvidia,pins = "kb_row17_pt1"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 796 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 797 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 798 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 799 | }; |
| 800 | gen2_i2c_scl_pt5 { |
| 801 | nvidia,pins = "gen2_i2c_scl_pt5"; |
| 802 | nvidia,function = "i2c2"; |
| 803 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 806 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 807 | }; |
| 808 | gen2_i2c_sda_pt6 { |
| 809 | nvidia,pins = "gen2_i2c_sda_pt6"; |
| 810 | nvidia,function = "i2c2"; |
| 811 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 813 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 814 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 815 | }; |
| 816 | sdmmc4_cmd_pt7 { |
| 817 | nvidia,pins = "sdmmc4_cmd_pt7"; |
| 818 | nvidia,function = "sdmmc4"; |
| 819 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 821 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 822 | }; |
| 823 | pu0 { |
| 824 | nvidia,pins = "pu0"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 825 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 827 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 828 | }; |
| 829 | pu1 { |
| 830 | nvidia,pins = "pu1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 831 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 832 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 833 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 834 | }; |
| 835 | pu2 { |
| 836 | nvidia,pins = "pu2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 837 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 838 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 839 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 840 | }; |
| 841 | pu3 { |
| 842 | nvidia,pins = "pu3"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 843 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 844 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 845 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 846 | }; |
| 847 | pu4 { |
| 848 | nvidia,pins = "pu4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 849 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 850 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 851 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 852 | }; |
| 853 | pu5 { |
| 854 | nvidia,pins = "pu5"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 855 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 856 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 857 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 858 | }; |
| 859 | pu6 { |
| 860 | nvidia,pins = "pu6"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 861 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 862 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 863 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 864 | }; |
| 865 | pv0 { |
| 866 | nvidia,pins = "pv0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 867 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 868 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 869 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 870 | }; |
| 871 | pv1 { |
| 872 | nvidia,pins = "pv1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 873 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 874 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 875 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 876 | }; |
| 877 | sdmmc3_cd_n_pv2 { |
| 878 | nvidia,pins = "sdmmc3_cd_n_pv2"; |
| 879 | nvidia,function = "sdmmc3"; |
| 880 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 881 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 882 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 883 | }; |
| 884 | sdmmc1_wp_n_pv3 { |
| 885 | nvidia,pins = "sdmmc1_wp_n_pv3"; |
| 886 | nvidia,function = "sdmmc1"; |
| 887 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 888 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 889 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 890 | }; |
| 891 | ddc_scl_pv4 { |
| 892 | nvidia,pins = "ddc_scl_pv4"; |
| 893 | nvidia,function = "i2c4"; |
| 894 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 895 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 896 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 897 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; |
| 898 | }; |
| 899 | ddc_sda_pv5 { |
| 900 | nvidia,pins = "ddc_sda_pv5"; |
| 901 | nvidia,function = "i2c4"; |
| 902 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 903 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 904 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 905 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; |
| 906 | }; |
| 907 | gpio_w2_aud_pw2 { |
| 908 | nvidia,pins = "gpio_w2_aud_pw2"; |
| 909 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 910 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 911 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 912 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 913 | }; |
| 914 | gpio_w3_aud_pw3 { |
| 915 | nvidia,pins = "gpio_w3_aud_pw3"; |
| 916 | nvidia,function = "spi6"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 917 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 918 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 919 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 920 | }; |
| 921 | dap_mclk1_pw4 { |
| 922 | nvidia,pins = "dap_mclk1_pw4"; |
| 923 | nvidia,function = "extperiph1"; |
| 924 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 925 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 926 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 927 | }; |
| 928 | clk2_out_pw5 { |
| 929 | nvidia,pins = "clk2_out_pw5"; |
| 930 | nvidia,function = "extperiph2"; |
| 931 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 932 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 933 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 934 | }; |
| 935 | uart3_txd_pw6 { |
| 936 | nvidia,pins = "uart3_txd_pw6"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 937 | nvidia,function = "rsvd2"; |
| 938 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 939 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 940 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 941 | }; |
| 942 | uart3_rxd_pw7 { |
| 943 | nvidia,pins = "uart3_rxd_pw7"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 944 | nvidia,function = "rsvd2"; |
| 945 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 946 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 947 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 948 | }; |
| 949 | dvfs_pwm_px0 { |
| 950 | nvidia,pins = "dvfs_pwm_px0"; |
| 951 | nvidia,function = "cldvfs"; |
| 952 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 953 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 954 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 955 | }; |
| 956 | gpio_x1_aud_px1 { |
| 957 | nvidia,pins = "gpio_x1_aud_px1"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 958 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 959 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 960 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 961 | }; |
| 962 | dvfs_clk_px2 { |
| 963 | nvidia,pins = "dvfs_clk_px2"; |
| 964 | nvidia,function = "cldvfs"; |
| 965 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 966 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 967 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 968 | }; |
| 969 | gpio_x3_aud_px3 { |
| 970 | nvidia,pins = "gpio_x3_aud_px3"; |
| 971 | nvidia,function = "rsvd4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 972 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 973 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 974 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 975 | }; |
| 976 | gpio_x4_aud_px4 { |
| 977 | nvidia,pins = "gpio_x4_aud_px4"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 978 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 979 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 980 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 981 | }; |
| 982 | gpio_x5_aud_px5 { |
| 983 | nvidia,pins = "gpio_x5_aud_px5"; |
| 984 | nvidia,function = "rsvd4"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 985 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 986 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 987 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 988 | }; |
| 989 | gpio_x6_aud_px6 { |
| 990 | nvidia,pins = "gpio_x6_aud_px6"; |
| 991 | nvidia,function = "gmi"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 992 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 993 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 994 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 995 | }; |
| 996 | gpio_x7_aud_px7 { |
| 997 | nvidia,pins = "gpio_x7_aud_px7"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 998 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 999 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1000 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1001 | }; |
| 1002 | ulpi_clk_py0 { |
| 1003 | nvidia,pins = "ulpi_clk_py0"; |
| 1004 | nvidia,function = "spi1"; |
| 1005 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1006 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1007 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1008 | }; |
| 1009 | ulpi_dir_py1 { |
| 1010 | nvidia,pins = "ulpi_dir_py1"; |
| 1011 | nvidia,function = "spi1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1012 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1013 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1014 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1015 | }; |
| 1016 | ulpi_nxt_py2 { |
| 1017 | nvidia,pins = "ulpi_nxt_py2"; |
| 1018 | nvidia,function = "spi1"; |
| 1019 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1020 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1021 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1022 | }; |
| 1023 | ulpi_stp_py3 { |
| 1024 | nvidia,pins = "ulpi_stp_py3"; |
| 1025 | nvidia,function = "spi1"; |
| 1026 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1027 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1028 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1029 | }; |
| 1030 | sdmmc1_dat3_py4 { |
| 1031 | nvidia,pins = "sdmmc1_dat3_py4"; |
| 1032 | nvidia,function = "sdmmc1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1033 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1034 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1035 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1036 | }; |
| 1037 | sdmmc1_dat2_py5 { |
| 1038 | nvidia,pins = "sdmmc1_dat2_py5"; |
| 1039 | nvidia,function = "sdmmc1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1040 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1041 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1042 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1043 | }; |
| 1044 | sdmmc1_dat1_py6 { |
| 1045 | nvidia,pins = "sdmmc1_dat1_py6"; |
| 1046 | nvidia,function = "sdmmc1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1047 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1048 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1049 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1050 | }; |
| 1051 | sdmmc1_dat0_py7 { |
| 1052 | nvidia,pins = "sdmmc1_dat0_py7"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1053 | nvidia,function = "rsvd2"; |
| 1054 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1055 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1056 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1057 | }; |
| 1058 | sdmmc1_clk_pz0 { |
| 1059 | nvidia,pins = "sdmmc1_clk_pz0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1060 | nvidia,function = "rsvd3"; |
| 1061 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1062 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1063 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1064 | }; |
| 1065 | sdmmc1_cmd_pz1 { |
| 1066 | nvidia,pins = "sdmmc1_cmd_pz1"; |
| 1067 | nvidia,function = "sdmmc1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1068 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1069 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1070 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1071 | }; |
| 1072 | pwr_i2c_scl_pz6 { |
| 1073 | nvidia,pins = "pwr_i2c_scl_pz6"; |
| 1074 | nvidia,function = "i2cpwr"; |
| 1075 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1076 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1077 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1078 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1079 | }; |
| 1080 | pwr_i2c_sda_pz7 { |
| 1081 | nvidia,pins = "pwr_i2c_sda_pz7"; |
| 1082 | nvidia,function = "i2cpwr"; |
| 1083 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1084 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1085 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1086 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1087 | }; |
| 1088 | sdmmc4_dat0_paa0 { |
| 1089 | nvidia,pins = "sdmmc4_dat0_paa0"; |
| 1090 | nvidia,function = "sdmmc4"; |
| 1091 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1092 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1093 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1094 | }; |
| 1095 | sdmmc4_dat1_paa1 { |
| 1096 | nvidia,pins = "sdmmc4_dat1_paa1"; |
| 1097 | nvidia,function = "sdmmc4"; |
| 1098 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1099 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1100 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1101 | }; |
| 1102 | sdmmc4_dat2_paa2 { |
| 1103 | nvidia,pins = "sdmmc4_dat2_paa2"; |
| 1104 | nvidia,function = "sdmmc4"; |
| 1105 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1106 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1107 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1108 | }; |
| 1109 | sdmmc4_dat3_paa3 { |
| 1110 | nvidia,pins = "sdmmc4_dat3_paa3"; |
| 1111 | nvidia,function = "sdmmc4"; |
| 1112 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1114 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1115 | }; |
| 1116 | sdmmc4_dat4_paa4 { |
| 1117 | nvidia,pins = "sdmmc4_dat4_paa4"; |
| 1118 | nvidia,function = "sdmmc4"; |
| 1119 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1120 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1121 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1122 | }; |
| 1123 | sdmmc4_dat5_paa5 { |
| 1124 | nvidia,pins = "sdmmc4_dat5_paa5"; |
| 1125 | nvidia,function = "sdmmc4"; |
| 1126 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1128 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1129 | }; |
| 1130 | sdmmc4_dat6_paa6 { |
| 1131 | nvidia,pins = "sdmmc4_dat6_paa6"; |
| 1132 | nvidia,function = "sdmmc4"; |
| 1133 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1134 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1135 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1136 | }; |
| 1137 | sdmmc4_dat7_paa7 { |
| 1138 | nvidia,pins = "sdmmc4_dat7_paa7"; |
| 1139 | nvidia,function = "sdmmc4"; |
| 1140 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1143 | }; |
| 1144 | pbb0 { |
| 1145 | nvidia,pins = "pbb0"; |
| 1146 | nvidia,function = "vimclk2_alt"; |
| 1147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1149 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1150 | }; |
| 1151 | cam_i2c_scl_pbb1 { |
| 1152 | nvidia,pins = "cam_i2c_scl_pbb1"; |
| 1153 | nvidia,function = "i2c3"; |
| 1154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1157 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1158 | }; |
| 1159 | cam_i2c_sda_pbb2 { |
| 1160 | nvidia,pins = "cam_i2c_sda_pbb2"; |
| 1161 | nvidia,function = "i2c3"; |
| 1162 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1163 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1164 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1165 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1166 | }; |
| 1167 | pbb3 { |
| 1168 | nvidia,pins = "pbb3"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1169 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1170 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1171 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1172 | }; |
| 1173 | pbb4 { |
| 1174 | nvidia,pins = "pbb4"; |
| 1175 | nvidia,function = "vgp4"; |
| 1176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1178 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1179 | }; |
| 1180 | pbb5 { |
| 1181 | nvidia,pins = "pbb5"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1185 | }; |
| 1186 | pbb6 { |
| 1187 | nvidia,pins = "pbb6"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1190 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1191 | }; |
| 1192 | pbb7 { |
| 1193 | nvidia,pins = "pbb7"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1194 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1195 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1196 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1197 | }; |
| 1198 | cam_mclk_pcc0 { |
| 1199 | nvidia,pins = "cam_mclk_pcc0"; |
| 1200 | nvidia,function = "vi_alt3"; |
| 1201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1203 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1204 | }; |
| 1205 | pcc1 { |
| 1206 | nvidia,pins = "pcc1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1207 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1208 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1209 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1210 | }; |
| 1211 | pcc2 { |
| 1212 | nvidia,pins = "pcc2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1215 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1216 | }; |
| 1217 | sdmmc4_clk_pcc4 { |
| 1218 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 1219 | nvidia,function = "sdmmc4"; |
| 1220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1222 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1223 | }; |
| 1224 | clk2_req_pcc5 { |
| 1225 | nvidia,pins = "clk2_req_pcc5"; |
| 1226 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1227 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1229 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1230 | }; |
Stephen Warren | b0da12d | 2014-08-22 15:07:13 -0600 | [diff] [blame] | 1231 | pex_l0_rst_n_pdd1 { |
| 1232 | nvidia,pins = "pex_l0_rst_n_pdd1"; |
| 1233 | nvidia,function = "pe0"; |
| 1234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1236 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1237 | }; |
| 1238 | pex_l0_clkreq_n_pdd2 { |
| 1239 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; |
| 1240 | nvidia,function = "pe0"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1241 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1242 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | b0da12d | 2014-08-22 15:07:13 -0600 | [diff] [blame] | 1243 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1244 | }; |
| 1245 | pex_wake_n_pdd3 { |
| 1246 | nvidia,pins = "pex_wake_n_pdd3"; |
| 1247 | nvidia,function = "pe"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1249 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | b0da12d | 2014-08-22 15:07:13 -0600 | [diff] [blame] | 1250 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1251 | }; |
| 1252 | pex_l1_rst_n_pdd5 { |
| 1253 | nvidia,pins = "pex_l1_rst_n_pdd5"; |
| 1254 | nvidia,function = "pe1"; |
| 1255 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1257 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1258 | }; |
| 1259 | pex_l1_clkreq_n_pdd6 { |
| 1260 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; |
| 1261 | nvidia,function = "pe1"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1263 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | b0da12d | 2014-08-22 15:07:13 -0600 | [diff] [blame] | 1264 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1265 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1266 | clk3_out_pee0 { |
| 1267 | nvidia,pins = "clk3_out_pee0"; |
| 1268 | nvidia,function = "extperiph3"; |
| 1269 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1270 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1271 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1272 | }; |
| 1273 | clk3_req_pee1 { |
| 1274 | nvidia,pins = "clk3_req_pee1"; |
| 1275 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1276 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1277 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1278 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1279 | }; |
| 1280 | dap_mclk1_req_pee2 { |
| 1281 | nvidia,pins = "dap_mclk1_req_pee2"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1284 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1285 | }; |
| 1286 | hdmi_cec_pee3 { |
| 1287 | nvidia,pins = "hdmi_cec_pee3"; |
| 1288 | nvidia,function = "cec"; |
| 1289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1290 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1291 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1292 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1293 | }; |
| 1294 | sdmmc3_clk_lb_out_pee4 { |
| 1295 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; |
| 1296 | nvidia,function = "sdmmc3"; |
| 1297 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1300 | }; |
| 1301 | sdmmc3_clk_lb_in_pee5 { |
| 1302 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; |
| 1303 | nvidia,function = "sdmmc3"; |
| 1304 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1306 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1307 | }; |
| 1308 | dp_hpd_pff0 { |
| 1309 | nvidia,pins = "dp_hpd_pff0"; |
| 1310 | nvidia,function = "dp"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1311 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1312 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1313 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1314 | }; |
| 1315 | usb_vbus_en2_pff1 { |
| 1316 | nvidia,pins = "usb_vbus_en2_pff1"; |
| 1317 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1318 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1319 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1320 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1321 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1322 | }; |
| 1323 | pff2 { |
| 1324 | nvidia,pins = "pff2"; |
| 1325 | nvidia,function = "rsvd2"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1326 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1327 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1328 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1329 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1330 | }; |
| 1331 | core_pwr_req { |
| 1332 | nvidia,pins = "core_pwr_req"; |
| 1333 | nvidia,function = "pwron"; |
| 1334 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1335 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1336 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1337 | }; |
| 1338 | cpu_pwr_req { |
| 1339 | nvidia,pins = "cpu_pwr_req"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1340 | nvidia,function = "cpu"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1341 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1342 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1343 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1344 | }; |
| 1345 | pwr_int_n { |
| 1346 | nvidia,pins = "pwr_int_n"; |
| 1347 | nvidia,function = "pmi"; |
| 1348 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1349 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1350 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1351 | }; |
| 1352 | reset_out_n { |
| 1353 | nvidia,pins = "reset_out_n"; |
| 1354 | nvidia,function = "reset_out_n"; |
| 1355 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1358 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1359 | clk_32k_in { |
| 1360 | nvidia,pins = "clk_32k_in"; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1361 | nvidia,function = "clk"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1362 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | fb81664 | 2015-02-17 11:57:45 -0700 | [diff] [blame] | 1363 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1364 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1365 | }; |
| 1366 | jtag_rtck { |
| 1367 | nvidia,pins = "jtag_rtck"; |
| 1368 | nvidia,function = "rtck"; |
| 1369 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1371 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1372 | }; |
Stephen Warren | aee7a74 | 2016-06-21 12:51:49 -0600 | [diff] [blame] | 1373 | dsi_b { |
| 1374 | nvidia,pins = "mipi_pad_ctrl_dsi_b"; |
| 1375 | nvidia,function = "dsi_b"; |
| 1376 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1377 | }; |
| 1378 | }; |
| 1379 | |
Ralf Ramsauer | c90bb7b | 2016-01-26 17:59:18 +0100 | [diff] [blame] | 1380 | /* |
| 1381 | * First high speed UART, exposed on the expansion connector J3A2 |
| 1382 | * Pin 41: BR_UART1_TXD |
| 1383 | * Pin 44: BR_UART1_RXD |
| 1384 | */ |
Ralf Ramsauer | b5c86b7 | 2016-07-18 11:46:48 +0200 | [diff] [blame] | 1385 | serial@0,70006000 { |
Ralf Ramsauer | c90bb7b | 2016-01-26 17:59:18 +0100 | [diff] [blame] | 1386 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1387 | status = "okay"; |
| 1388 | }; |
| 1389 | |
| 1390 | /* |
| 1391 | * Second high speed UART, exposed on the expansion connector J3A2 |
| 1392 | * Pin 65: UART2_RXD |
| 1393 | * Pin 68: UART2_TXD |
| 1394 | * Pin 71: UART2_CTS_L |
| 1395 | * Pin 74: UART2_RTS_L |
| 1396 | */ |
Ralf Ramsauer | b5c86b7 | 2016-07-18 11:46:48 +0200 | [diff] [blame] | 1397 | serial@0,70006040 { |
Ralf Ramsauer | c90bb7b | 2016-01-26 17:59:18 +0100 | [diff] [blame] | 1398 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
| 1399 | status = "okay"; |
| 1400 | }; |
| 1401 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1402 | /* DB9 serial port */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1403 | serial@70006300 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1404 | status = "okay"; |
| 1405 | }; |
| 1406 | |
| 1407 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1408 | i2c@7000c000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1409 | status = "okay"; |
| 1410 | clock-frequency = <100000>; |
| 1411 | |
Stephen Warren | 98de744 | 2014-04-25 10:12:42 -0600 | [diff] [blame] | 1412 | rt5639: audio-codec@1c { |
| 1413 | compatible = "realtek,rt5639"; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1414 | reg = <0x1c>; |
| 1415 | interrupt-parent = <&gpio>; |
| 1416 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; |
| 1417 | realtek,ldo1-en-gpios = |
| 1418 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; |
| 1419 | }; |
| 1420 | |
| 1421 | temperature-sensor@4c { |
| 1422 | compatible = "ti,tmp451"; |
| 1423 | reg = <0x4c>; |
| 1424 | interrupt-parent = <&gpio>; |
| 1425 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; |
| 1426 | }; |
| 1427 | |
| 1428 | eeprom@56 { |
| 1429 | compatible = "atmel,24c02"; |
| 1430 | reg = <0x56>; |
| 1431 | pagesize = <8>; |
| 1432 | }; |
| 1433 | }; |
| 1434 | |
| 1435 | /* Expansion GEN2_I2C_* */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1436 | i2c@7000c400 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1437 | status = "okay"; |
| 1438 | clock-frequency = <100000>; |
| 1439 | }; |
| 1440 | |
| 1441 | /* Expansion CAM_I2C_* */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1442 | i2c@7000c500 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1443 | status = "okay"; |
| 1444 | clock-frequency = <100000>; |
| 1445 | }; |
| 1446 | |
| 1447 | /* HDMI DDC */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1448 | hdmi_ddc: i2c@7000c700 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1449 | status = "okay"; |
| 1450 | clock-frequency = <100000>; |
| 1451 | }; |
| 1452 | |
| 1453 | /* Expansion PWR_I2C_*, on-board components */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1454 | i2c@7000d000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1455 | status = "okay"; |
| 1456 | clock-frequency = <400000>; |
| 1457 | |
| 1458 | pmic: pmic@40 { |
| 1459 | compatible = "ams,as3722"; |
| 1460 | reg = <0x40>; |
| 1461 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1462 | |
| 1463 | ams,system-power-controller; |
| 1464 | |
| 1465 | #interrupt-cells = <2>; |
| 1466 | interrupt-controller; |
| 1467 | |
| 1468 | gpio-controller; |
| 1469 | #gpio-cells = <2>; |
| 1470 | |
| 1471 | pinctrl-names = "default"; |
| 1472 | pinctrl-0 = <&as3722_default>; |
| 1473 | |
| 1474 | as3722_default: pinmux { |
| 1475 | gpio0 { |
| 1476 | pins = "gpio0"; |
| 1477 | function = "gpio"; |
| 1478 | bias-pull-down; |
| 1479 | }; |
| 1480 | |
| 1481 | gpio1_2_4_7 { |
| 1482 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; |
| 1483 | function = "gpio"; |
| 1484 | bias-pull-up; |
| 1485 | }; |
| 1486 | |
| 1487 | gpio3_5_6 { |
| 1488 | pins = "gpio3", "gpio5", "gpio6"; |
| 1489 | bias-high-impedance; |
| 1490 | }; |
| 1491 | }; |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1492 | |
| 1493 | regulators { |
| 1494 | vsup-sd2-supply = <&vdd_5v0_sys>; |
| 1495 | vsup-sd3-supply = <&vdd_5v0_sys>; |
| 1496 | vsup-sd4-supply = <&vdd_5v0_sys>; |
| 1497 | vsup-sd5-supply = <&vdd_5v0_sys>; |
| 1498 | vin-ldo0-supply = <&vdd_1v35_lp0>; |
| 1499 | vin-ldo1-6-supply = <&vdd_3v3_run>; |
| 1500 | vin-ldo2-5-7-supply = <&vddio_1v8>; |
| 1501 | vin-ldo3-4-supply = <&vdd_3v3_sys>; |
| 1502 | vin-ldo9-10-supply = <&vdd_5v0_sys>; |
| 1503 | vin-ldo11-supply = <&vdd_3v3_run>; |
| 1504 | |
Tuomas Tynkkynen | 9be1e47 | 2015-05-13 17:58:45 +0300 | [diff] [blame] | 1505 | vdd_cpu: sd0 { |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1506 | regulator-name = "+VDD_CPU_AP"; |
| 1507 | regulator-min-microvolt = <700000>; |
| 1508 | regulator-max-microvolt = <1400000>; |
| 1509 | regulator-min-microamp = <3500000>; |
| 1510 | regulator-max-microamp = <3500000>; |
| 1511 | regulator-always-on; |
| 1512 | regulator-boot-on; |
Tuomas Tynkkynen | ee913f7 | 2014-07-09 21:53:17 +0300 | [diff] [blame] | 1513 | ams,ext-control = <2>; |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1514 | }; |
| 1515 | |
| 1516 | sd1 { |
| 1517 | regulator-name = "+VDD_CORE"; |
| 1518 | regulator-min-microvolt = <700000>; |
| 1519 | regulator-max-microvolt = <1350000>; |
| 1520 | regulator-min-microamp = <2500000>; |
| 1521 | regulator-max-microamp = <2500000>; |
| 1522 | regulator-always-on; |
| 1523 | regulator-boot-on; |
Tuomas Tynkkynen | ee913f7 | 2014-07-09 21:53:17 +0300 | [diff] [blame] | 1524 | ams,ext-control = <1>; |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1525 | }; |
| 1526 | |
| 1527 | vdd_1v35_lp0: sd2 { |
| 1528 | regulator-name = "+1.35V_LP0(sd2)"; |
| 1529 | regulator-min-microvolt = <1350000>; |
| 1530 | regulator-max-microvolt = <1350000>; |
| 1531 | regulator-always-on; |
| 1532 | regulator-boot-on; |
| 1533 | }; |
| 1534 | |
| 1535 | sd3 { |
| 1536 | regulator-name = "+1.35V_LP0(sd3)"; |
| 1537 | regulator-min-microvolt = <1350000>; |
| 1538 | regulator-max-microvolt = <1350000>; |
| 1539 | regulator-always-on; |
| 1540 | regulator-boot-on; |
| 1541 | }; |
| 1542 | |
Thierry Reding | 6054dd3 | 2014-04-25 17:44:47 +0200 | [diff] [blame] | 1543 | vdd_1v05_run: sd4 { |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1544 | regulator-name = "+1.05V_RUN"; |
| 1545 | regulator-min-microvolt = <1050000>; |
| 1546 | regulator-max-microvolt = <1050000>; |
| 1547 | }; |
| 1548 | |
| 1549 | vddio_1v8: sd5 { |
| 1550 | regulator-name = "+1.8V_VDDIO"; |
| 1551 | regulator-min-microvolt = <1800000>; |
| 1552 | regulator-max-microvolt = <1800000>; |
| 1553 | regulator-boot-on; |
| 1554 | regulator-always-on; |
| 1555 | }; |
| 1556 | |
Alexandre Courbot | 21fa196 | 2015-07-01 18:13:47 +0900 | [diff] [blame] | 1557 | vdd_gpu: sd6 { |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1558 | regulator-name = "+VDD_GPU_AP"; |
| 1559 | regulator-min-microvolt = <650000>; |
| 1560 | regulator-max-microvolt = <1200000>; |
| 1561 | regulator-min-microamp = <3500000>; |
| 1562 | regulator-max-microamp = <3500000>; |
| 1563 | regulator-boot-on; |
| 1564 | regulator-always-on; |
| 1565 | }; |
| 1566 | |
Thierry Reding | 8e2b9e4 | 2014-09-17 10:02:45 -0600 | [diff] [blame] | 1567 | avdd_1v05_run: ldo0 { |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1568 | regulator-name = "+1.05V_RUN_AVDD"; |
| 1569 | regulator-min-microvolt = <1050000>; |
| 1570 | regulator-max-microvolt = <1050000>; |
| 1571 | regulator-boot-on; |
| 1572 | regulator-always-on; |
Tuomas Tynkkynen | ee913f7 | 2014-07-09 21:53:17 +0300 | [diff] [blame] | 1573 | ams,ext-control = <1>; |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1574 | }; |
| 1575 | |
| 1576 | ldo1 { |
| 1577 | regulator-name = "+1.8V_RUN_CAM"; |
| 1578 | regulator-min-microvolt = <1800000>; |
| 1579 | regulator-max-microvolt = <1800000>; |
| 1580 | }; |
| 1581 | |
| 1582 | ldo2 { |
| 1583 | regulator-name = "+1.2V_GEN_AVDD"; |
| 1584 | regulator-min-microvolt = <1200000>; |
| 1585 | regulator-max-microvolt = <1200000>; |
| 1586 | regulator-boot-on; |
| 1587 | regulator-always-on; |
| 1588 | }; |
| 1589 | |
| 1590 | ldo3 { |
| 1591 | regulator-name = "+1.05V_LP0_VDD_RTC"; |
| 1592 | regulator-min-microvolt = <1000000>; |
| 1593 | regulator-max-microvolt = <1000000>; |
| 1594 | regulator-boot-on; |
| 1595 | regulator-always-on; |
| 1596 | ams,enable-tracking; |
| 1597 | }; |
| 1598 | |
| 1599 | ldo4 { |
| 1600 | regulator-name = "+2.8V_RUN_CAM"; |
| 1601 | regulator-min-microvolt = <2800000>; |
| 1602 | regulator-max-microvolt = <2800000>; |
| 1603 | }; |
| 1604 | |
| 1605 | ldo5 { |
| 1606 | regulator-name = "+1.2V_RUN_CAM_FRONT"; |
| 1607 | regulator-min-microvolt = <1200000>; |
| 1608 | regulator-max-microvolt = <1200000>; |
| 1609 | }; |
| 1610 | |
| 1611 | vddio_sdmmc3: ldo6 { |
| 1612 | regulator-name = "+VDDIO_SDMMC3"; |
| 1613 | regulator-min-microvolt = <1800000>; |
| 1614 | regulator-max-microvolt = <3300000>; |
| 1615 | }; |
| 1616 | |
| 1617 | ldo7 { |
| 1618 | regulator-name = "+1.05V_RUN_CAM_REAR"; |
| 1619 | regulator-min-microvolt = <1050000>; |
| 1620 | regulator-max-microvolt = <1050000>; |
| 1621 | }; |
| 1622 | |
| 1623 | ldo9 { |
| 1624 | regulator-name = "+3.3V_RUN_TOUCH"; |
| 1625 | regulator-min-microvolt = <2800000>; |
| 1626 | regulator-max-microvolt = <2800000>; |
| 1627 | }; |
| 1628 | |
| 1629 | ldo10 { |
| 1630 | regulator-name = "+2.8V_RUN_CAM_AF"; |
| 1631 | regulator-min-microvolt = <2800000>; |
| 1632 | regulator-max-microvolt = <2800000>; |
| 1633 | }; |
| 1634 | |
| 1635 | ldo11 { |
| 1636 | regulator-name = "+1.8V_RUN_VPP_FUSE"; |
| 1637 | regulator-min-microvolt = <1800000>; |
| 1638 | regulator-max-microvolt = <1800000>; |
| 1639 | }; |
| 1640 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1641 | }; |
| 1642 | }; |
| 1643 | |
| 1644 | /* Expansion TS_SPI_* */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1645 | spi@7000d400 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1646 | status = "okay"; |
| 1647 | }; |
| 1648 | |
| 1649 | /* Internal SPI */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1650 | spi@7000da00 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1651 | status = "okay"; |
| 1652 | spi-max-frequency = <25000000>; |
| 1653 | spi-flash@0 { |
| 1654 | compatible = "winbond,w25q32dw"; |
| 1655 | reg = <0>; |
| 1656 | spi-max-frequency = <20000000>; |
| 1657 | }; |
| 1658 | }; |
| 1659 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1660 | pmc@7000e400 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1661 | nvidia,invert-interrupt; |
| 1662 | nvidia,suspend-mode = <1>; |
| 1663 | nvidia,cpu-pwr-good-time = <500>; |
| 1664 | nvidia,cpu-pwr-off-time = <300>; |
| 1665 | nvidia,core-pwr-good-time = <641 3845>; |
| 1666 | nvidia,core-pwr-off-time = <61036>; |
| 1667 | nvidia,core-power-req-active-high; |
| 1668 | nvidia,sys-clock-req-active-high; |
Mikko Perttunen | 9c96330 | 2015-01-06 12:52:57 +0200 | [diff] [blame] | 1669 | |
| 1670 | i2c-thermtrip { |
| 1671 | nvidia,i2c-controller-id = <4>; |
| 1672 | nvidia,bus-addr = <0x40>; |
| 1673 | nvidia,reg-addr = <0x36>; |
| 1674 | nvidia,reg-data = <0x2>; |
| 1675 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1676 | }; |
| 1677 | |
Mikko Perttunen | 1b3ce99 | 2014-07-16 11:54:18 +0300 | [diff] [blame] | 1678 | /* Serial ATA */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1679 | sata@70020000 { |
Mikko Perttunen | 1b3ce99 | 2014-07-16 11:54:18 +0300 | [diff] [blame] | 1680 | status = "okay"; |
| 1681 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1682 | phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1683 | phy-names = "sata-0"; |
| 1684 | |
Mikko Perttunen | 1b3ce99 | 2014-07-16 11:54:18 +0300 | [diff] [blame] | 1685 | hvdd-supply = <&vdd_3v3_lp0>; |
| 1686 | vddio-supply = <&vdd_1v05_run>; |
| 1687 | avdd-supply = <&vdd_1v05_run>; |
| 1688 | |
| 1689 | target-5v-supply = <&vdd_5v0_sata>; |
| 1690 | target-12v-supply = <&vdd_12v0_sata>; |
| 1691 | }; |
| 1692 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1693 | hda@70030000 { |
Thierry Reding | 4c84472 | 2014-05-22 09:38:31 +0200 | [diff] [blame] | 1694 | status = "okay"; |
| 1695 | }; |
| 1696 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1697 | usb@70090000 { |
| 1698 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ |
| 1699 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ |
| 1700 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ |
| 1701 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1702 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; |
Thierry Reding | 62b8db0 | 2014-06-19 13:37:10 +0200 | [diff] [blame] | 1703 | |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1704 | avddio-pex-supply = <&vdd_1v05_run>; |
| 1705 | dvddio-pex-supply = <&vdd_1v05_run>; |
| 1706 | avdd-usb-supply = <&vdd_3v3_lp0>; |
| 1707 | avdd-pll-utmip-supply = <&vddio_1v8>; |
| 1708 | avdd-pll-erefe-supply = <&avdd_1v05_run>; |
| 1709 | avdd-usb-ss-pll-supply = <&vdd_1v05_run>; |
| 1710 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; |
| 1711 | hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; |
| 1712 | |
| 1713 | status = "okay"; |
| 1714 | }; |
| 1715 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1716 | padctl@7009f000 { |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1717 | status = "okay"; |
| 1718 | |
| 1719 | pads { |
| 1720 | usb2 { |
| 1721 | status = "okay"; |
| 1722 | |
| 1723 | lanes { |
| 1724 | usb2-0 { |
| 1725 | nvidia,function = "xusb"; |
| 1726 | status = "okay"; |
| 1727 | }; |
| 1728 | |
| 1729 | usb2-1 { |
| 1730 | nvidia,function = "xusb"; |
| 1731 | status = "okay"; |
| 1732 | }; |
| 1733 | |
| 1734 | usb2-2 { |
| 1735 | nvidia,function = "xusb"; |
| 1736 | status = "okay"; |
| 1737 | }; |
| 1738 | }; |
Thierry Reding | 62b8db0 | 2014-06-19 13:37:10 +0200 | [diff] [blame] | 1739 | }; |
| 1740 | |
| 1741 | pcie { |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1742 | status = "okay"; |
| 1743 | |
| 1744 | lanes { |
| 1745 | pcie-0 { |
| 1746 | nvidia,function = "usb3-ss"; |
| 1747 | status = "okay"; |
| 1748 | }; |
| 1749 | |
| 1750 | pcie-2 { |
| 1751 | nvidia,function = "pcie"; |
| 1752 | status = "okay"; |
| 1753 | }; |
| 1754 | |
| 1755 | pcie-4 { |
| 1756 | nvidia,function = "pcie"; |
| 1757 | status = "okay"; |
| 1758 | }; |
| 1759 | }; |
Thierry Reding | 62b8db0 | 2014-06-19 13:37:10 +0200 | [diff] [blame] | 1760 | }; |
| 1761 | |
| 1762 | sata { |
Thierry Reding | 87c6811 | 2015-11-11 18:22:27 +0100 | [diff] [blame] | 1763 | status = "okay"; |
| 1764 | |
| 1765 | lanes { |
| 1766 | sata-0 { |
| 1767 | nvidia,function = "sata"; |
| 1768 | status = "okay"; |
| 1769 | }; |
| 1770 | }; |
| 1771 | }; |
| 1772 | }; |
| 1773 | |
| 1774 | ports { |
| 1775 | /* Micro A/B */ |
| 1776 | usb2-0 { |
| 1777 | status = "okay"; |
| 1778 | mode = "otg"; |
| 1779 | }; |
| 1780 | |
| 1781 | /* Mini PCIe */ |
| 1782 | usb2-1 { |
| 1783 | status = "okay"; |
| 1784 | mode = "host"; |
| 1785 | }; |
| 1786 | |
| 1787 | /* USB3 */ |
| 1788 | usb2-2 { |
| 1789 | status = "okay"; |
| 1790 | mode = "host"; |
| 1791 | |
| 1792 | vbus-supply = <&vdd_usb3_vbus>; |
| 1793 | }; |
| 1794 | |
| 1795 | usb3-0 { |
| 1796 | nvidia,usb2-companion = <2>; |
| 1797 | status = "okay"; |
Thierry Reding | 62b8db0 | 2014-06-19 13:37:10 +0200 | [diff] [blame] | 1798 | }; |
| 1799 | }; |
| 1800 | }; |
| 1801 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1802 | /* SD card */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1803 | sdhci@700b0400 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1804 | status = "okay"; |
| 1805 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 1806 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
Stephen Warren | 215f21c | 2014-04-28 11:05:57 -0600 | [diff] [blame] | 1807 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1808 | bus-width = <4>; |
Stephen Warren | 9260764 | 2014-04-16 10:34:18 -0600 | [diff] [blame] | 1809 | vqmmc-supply = <&vddio_sdmmc3>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1810 | }; |
| 1811 | |
| 1812 | /* eMMC */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1813 | sdhci@700b0600 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1814 | status = "okay"; |
| 1815 | bus-width = <8>; |
Lucas Stach | 33f34f0 | 2014-06-03 14:48:46 +0200 | [diff] [blame] | 1816 | non-removable; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1817 | }; |
| 1818 | |
Tuomas Tynkkynen | 9be1e47 | 2015-05-13 17:58:45 +0300 | [diff] [blame] | 1819 | /* CPU DFLL clock */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1820 | clock@70110000 { |
Tuomas Tynkkynen | 9be1e47 | 2015-05-13 17:58:45 +0300 | [diff] [blame] | 1821 | status = "okay"; |
| 1822 | vdd-cpu-supply = <&vdd_cpu>; |
| 1823 | nvidia,i2c-fs-rate = <400000>; |
| 1824 | }; |
| 1825 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1826 | ahub@70300000 { |
| 1827 | i2s@70301100 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1828 | status = "okay"; |
| 1829 | }; |
| 1830 | }; |
| 1831 | |
| 1832 | /* mini-PCIe USB */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1833 | usb@7d004000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1834 | status = "okay"; |
| 1835 | }; |
| 1836 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1837 | usb-phy@7d004000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1838 | status = "okay"; |
| 1839 | }; |
| 1840 | |
| 1841 | /* USB A connector */ |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1842 | usb@7d008000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1843 | status = "okay"; |
| 1844 | }; |
| 1845 | |
Marcel Ziswiler | b5896f6 | 2016-06-30 00:21:37 +0200 | [diff] [blame] | 1846 | usb-phy@7d008000 { |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1847 | status = "okay"; |
| 1848 | vbus-supply = <&vdd_usb3_vbus>; |
| 1849 | }; |
| 1850 | |
| 1851 | clocks { |
| 1852 | compatible = "simple-bus"; |
| 1853 | #address-cells = <1>; |
| 1854 | #size-cells = <0>; |
| 1855 | |
| 1856 | clk32k_in: clock@0 { |
| 1857 | compatible = "fixed-clock"; |
| 1858 | reg = <0>; |
| 1859 | #clock-cells = <0>; |
| 1860 | clock-frequency = <32768>; |
| 1861 | }; |
| 1862 | }; |
| 1863 | |
Mikko Perttunen | ee9f106 | 2015-05-13 17:58:50 +0300 | [diff] [blame] | 1864 | cpus { |
| 1865 | cpu@0 { |
| 1866 | vdd-cpu-supply = <&vdd_cpu>; |
| 1867 | }; |
| 1868 | }; |
| 1869 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1870 | gpio-keys { |
| 1871 | compatible = "gpio-keys"; |
| 1872 | |
| 1873 | power { |
| 1874 | label = "Power"; |
| 1875 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 1876 | linux,code = <KEY_POWER>; |
| 1877 | debounce-interval = <10>; |
Sudeep Holla | d1c04d3 | 2016-02-08 21:55:43 +0000 | [diff] [blame] | 1878 | wakeup-source; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1879 | }; |
| 1880 | }; |
| 1881 | |
| 1882 | regulators { |
| 1883 | compatible = "simple-bus"; |
| 1884 | #address-cells = <1>; |
| 1885 | #size-cells = <0>; |
| 1886 | |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1887 | vdd_mux: regulator@0 { |
| 1888 | compatible = "regulator-fixed"; |
| 1889 | reg = <0>; |
| 1890 | regulator-name = "+VDD_MUX"; |
| 1891 | regulator-min-microvolt = <12000000>; |
| 1892 | regulator-max-microvolt = <12000000>; |
| 1893 | regulator-always-on; |
| 1894 | regulator-boot-on; |
| 1895 | }; |
| 1896 | |
| 1897 | vdd_5v0_sys: regulator@1 { |
| 1898 | compatible = "regulator-fixed"; |
| 1899 | reg = <1>; |
| 1900 | regulator-name = "+5V_SYS"; |
| 1901 | regulator-min-microvolt = <5000000>; |
| 1902 | regulator-max-microvolt = <5000000>; |
| 1903 | regulator-always-on; |
| 1904 | regulator-boot-on; |
| 1905 | vin-supply = <&vdd_mux>; |
| 1906 | }; |
| 1907 | |
| 1908 | vdd_3v3_sys: regulator@2 { |
| 1909 | compatible = "regulator-fixed"; |
| 1910 | reg = <2>; |
| 1911 | regulator-name = "+3.3V_SYS"; |
| 1912 | regulator-min-microvolt = <3300000>; |
| 1913 | regulator-max-microvolt = <3300000>; |
| 1914 | regulator-always-on; |
| 1915 | regulator-boot-on; |
| 1916 | vin-supply = <&vdd_mux>; |
| 1917 | }; |
| 1918 | |
| 1919 | vdd_3v3_run: regulator@3 { |
| 1920 | compatible = "regulator-fixed"; |
| 1921 | reg = <3>; |
| 1922 | regulator-name = "+3.3V_RUN"; |
| 1923 | regulator-min-microvolt = <3300000>; |
| 1924 | regulator-max-microvolt = <3300000>; |
| 1925 | regulator-always-on; |
| 1926 | regulator-boot-on; |
| 1927 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 1928 | enable-active-high; |
| 1929 | vin-supply = <&vdd_3v3_sys>; |
| 1930 | }; |
| 1931 | |
| 1932 | vdd_3v3_hdmi: regulator@4 { |
| 1933 | compatible = "regulator-fixed"; |
| 1934 | reg = <4>; |
| 1935 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
| 1936 | regulator-min-microvolt = <3300000>; |
| 1937 | regulator-max-microvolt = <3300000>; |
| 1938 | vin-supply = <&vdd_3v3_run>; |
| 1939 | }; |
| 1940 | |
| 1941 | vdd_usb1_vbus: regulator@7 { |
| 1942 | compatible = "regulator-fixed"; |
| 1943 | reg = <7>; |
| 1944 | regulator-name = "+USB0_VBUS_SW"; |
| 1945 | regulator-min-microvolt = <5000000>; |
| 1946 | regulator-max-microvolt = <5000000>; |
| 1947 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
| 1948 | enable-active-high; |
| 1949 | gpio-open-drain; |
| 1950 | vin-supply = <&vdd_5v0_sys>; |
| 1951 | }; |
| 1952 | |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1953 | vdd_usb3_vbus: regulator@8 { |
| 1954 | compatible = "regulator-fixed"; |
| 1955 | reg = <8>; |
| 1956 | regulator-name = "+5V_USB_HS"; |
| 1957 | regulator-min-microvolt = <5000000>; |
| 1958 | regulator-max-microvolt = <5000000>; |
| 1959 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; |
| 1960 | enable-active-high; |
| 1961 | gpio-open-drain; |
Stephen Warren | 22b3577 | 2014-03-24 18:04:43 -0600 | [diff] [blame] | 1962 | vin-supply = <&vdd_5v0_sys>; |
| 1963 | }; |
| 1964 | |
| 1965 | vdd_3v3_lp0: regulator@10 { |
| 1966 | compatible = "regulator-fixed"; |
| 1967 | reg = <10>; |
| 1968 | regulator-name = "+3.3V_LP0"; |
| 1969 | regulator-min-microvolt = <3300000>; |
| 1970 | regulator-max-microvolt = <3300000>; |
| 1971 | regulator-always-on; |
| 1972 | regulator-boot-on; |
| 1973 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
| 1974 | enable-active-high; |
| 1975 | vin-supply = <&vdd_3v3_sys>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 1976 | }; |
Thierry Reding | 6054dd3 | 2014-04-25 17:44:47 +0200 | [diff] [blame] | 1977 | |
| 1978 | vdd_hdmi_pll: regulator@11 { |
| 1979 | compatible = "regulator-fixed"; |
| 1980 | reg = <11>; |
| 1981 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; |
| 1982 | regulator-min-microvolt = <1050000>; |
| 1983 | regulator-max-microvolt = <1050000>; |
| 1984 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; |
| 1985 | vin-supply = <&vdd_1v05_run>; |
| 1986 | }; |
| 1987 | |
| 1988 | vdd_5v0_hdmi: regulator@12 { |
| 1989 | compatible = "regulator-fixed"; |
| 1990 | reg = <12>; |
| 1991 | regulator-name = "+5V_HDMI_CON"; |
| 1992 | regulator-min-microvolt = <5000000>; |
| 1993 | regulator-max-microvolt = <5000000>; |
| 1994 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 1995 | enable-active-high; |
| 1996 | vin-supply = <&vdd_5v0_sys>; |
| 1997 | }; |
Mikko Perttunen | 1b3ce99 | 2014-07-16 11:54:18 +0300 | [diff] [blame] | 1998 | |
| 1999 | /* Molex power connector */ |
| 2000 | vdd_5v0_sata: regulator@13 { |
| 2001 | compatible = "regulator-fixed"; |
| 2002 | reg = <13>; |
| 2003 | regulator-name = "+5V_SATA"; |
| 2004 | regulator-min-microvolt = <5000000>; |
| 2005 | regulator-max-microvolt = <5000000>; |
| 2006 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; |
| 2007 | enable-active-high; |
| 2008 | vin-supply = <&vdd_5v0_sys>; |
| 2009 | }; |
| 2010 | |
| 2011 | vdd_12v0_sata: regulator@14 { |
| 2012 | compatible = "regulator-fixed"; |
| 2013 | reg = <14>; |
| 2014 | regulator-name = "+12V_SATA"; |
| 2015 | regulator-min-microvolt = <12000000>; |
| 2016 | regulator-max-microvolt = <12000000>; |
| 2017 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; |
| 2018 | enable-active-high; |
| 2019 | vin-supply = <&vdd_mux>; |
| 2020 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 2021 | }; |
| 2022 | |
| 2023 | sound { |
| 2024 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", |
| 2025 | "nvidia,tegra-audio-rt5640"; |
| 2026 | nvidia,model = "NVIDIA Tegra Jetson TK1"; |
| 2027 | |
| 2028 | nvidia,audio-routing = |
| 2029 | "Headphones", "HPOR", |
| 2030 | "Headphones", "HPOL", |
| 2031 | "Mic Jack", "MICBIAS1", |
| 2032 | "IN2P", "Mic Jack"; |
| 2033 | |
| 2034 | nvidia,i2s-controller = <&tegra_i2s1>; |
Stephen Warren | 98de744 | 2014-04-25 10:12:42 -0600 | [diff] [blame] | 2035 | nvidia,audio-codec = <&rt5639>; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 2036 | |
| 2037 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; |
| 2038 | |
| 2039 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, |
| 2040 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
| 2041 | <&tegra_car TEGRA124_CLK_EXTERN1>; |
| 2042 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 2043 | }; |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2044 | |
| 2045 | thermal-zones { |
| 2046 | cpu { |
| 2047 | trips { |
Wei Ni | 40823f8 | 2016-05-11 18:20:19 +0800 | [diff] [blame^] | 2048 | cpu-shutdown-trip { |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2049 | temperature = <101000>; |
| 2050 | hysteresis = <0>; |
| 2051 | type = "critical"; |
| 2052 | }; |
| 2053 | }; |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2054 | }; |
| 2055 | |
| 2056 | mem { |
| 2057 | trips { |
Wei Ni | 40823f8 | 2016-05-11 18:20:19 +0800 | [diff] [blame^] | 2058 | mem-shutdown-trip { |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2059 | temperature = <101000>; |
| 2060 | hysteresis = <0>; |
| 2061 | type = "critical"; |
| 2062 | }; |
| 2063 | }; |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2064 | }; |
| 2065 | |
| 2066 | gpu { |
| 2067 | trips { |
Wei Ni | 40823f8 | 2016-05-11 18:20:19 +0800 | [diff] [blame^] | 2068 | gpu-shutdown-trip { |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2069 | temperature = <101000>; |
| 2070 | hysteresis = <0>; |
| 2071 | type = "critical"; |
| 2072 | }; |
| 2073 | }; |
Mikko Perttunen | ed7eac3 | 2014-09-26 12:43:12 +0300 | [diff] [blame] | 2074 | }; |
| 2075 | }; |
Stephen Warren | 15e524a | 2014-03-19 15:47:53 -0600 | [diff] [blame] | 2076 | }; |