blob: 9ebf4a234d9a907a68135239cb800cf88647848c [file] [log] [blame]
Thomas Gleixner77adf3f2020-09-08 14:34:48 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Andrew Vasquezfa90c542005-10-27 11:10:08 -07002/*
3 * QLogic Fibre Channel HBA Driver
Armen Baloyanbd21eaf2014-04-11 16:54:24 -04004 * Copyright (c) 2003-2014 QLogic Corporation
Andrew Vasquezfa90c542005-10-27 11:10:08 -07005 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07006#ifndef __QLA_DEF_H
7#define __QLA_DEF_H
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/completion.h>
Andrew Vasquezabbd8872005-07-06 10:30:05 -070022#include <linux/interrupt.h>
James.Smart@Emulex.Com19a7b4a2005-10-18 12:03:35 -040023#include <linux/workqueue.h>
Andrew Vasquez54333832005-11-09 15:49:04 -080024#include <linux/firmware.h>
Seokmann Ju14e660e2007-09-20 14:07:36 -070025#include <linux/aer.h>
Harihara Kadayam4d4df192008-04-03 13:13:26 -070026#include <linux/mutex.h>
Quinn Tran482c9dc2017-03-15 09:48:54 -070027#include <linux/btree.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -080033#include <scsi/scsi_transport_fc.h>
Giridhar Malavali9a069e12010-01-12 13:02:47 -080034#include <scsi/scsi_bsg_fc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Shyam Sundar62e9dd12020-06-30 03:22:28 -070036#include <uapi/scsi/fc/fc_els.h>
37
Bart Van Asschedf95f392019-08-08 20:01:58 -070038/* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
39typedef struct {
40 uint8_t domain;
41 uint8_t area;
42 uint8_t al_pa;
43} be_id_t;
44
45/* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
46typedef struct {
47 uint8_t al_pa;
48 uint8_t area;
49 uint8_t domain;
50} le_id_t;
51
Quinn Tran7ebb336e2021-06-23 22:25:56 -070052/*
53 * 24 bit port ID type definition.
54 */
55typedef union {
56 uint32_t b24 : 24;
57 struct {
58#ifdef __BIG_ENDIAN
59 uint8_t domain;
60 uint8_t area;
61 uint8_t al_pa;
62#elif defined(__LITTLE_ENDIAN)
63 uint8_t al_pa;
64 uint8_t area;
65 uint8_t domain;
66#else
67#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
68#endif
69 uint8_t rsvd_1;
70 } b;
71} port_id_t;
72#define INVALID_PORT_ID 0xFFFFFF
73
Giridhar Malavali6e980162010-03-19 17:03:58 -070074#include "qla_bsg.h"
Bart Van Assche15b7a682019-04-17 14:44:38 -070075#include "qla_dsd.h"
Giridhar Malavalia9083012010-04-12 17:59:55 -070076#include "qla_nx.h"
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -040077#include "qla_nx2.h"
Duane Grigsbye84067d2017-06-21 13:48:43 -070078#include "qla_nvme.h"
Harish Zunjarrao6a03b4c2010-05-04 15:01:24 -070079#define QLA2XXX_DRIVER_NAME "qla2xxx"
80#define QLA2XXX_APIDEV "ql2xapidev"
Paul Bollef24b6972013-02-08 01:57:55 -050081#define QLA2XXX_MANUFACTURER "QLogic Corporation"
Andrew Vasquezcb630672006-05-17 15:09:45 -070082
Linus Torvalds1da177e2005-04-16 15:20:36 -070083/*
84 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
85 * but that's fine as we don't look at the last 24 ones for
86 * ISP2100 HBAs.
87 */
88#define MAILBOX_REGISTER_COUNT_2100 8
Andrew Vasquez67ddda32012-02-09 11:14:08 -080089#define MAILBOX_REGISTER_COUNT_2200 24
Linus Torvalds1da177e2005-04-16 15:20:36 -070090#define MAILBOX_REGISTER_COUNT 32
91
92#define QLA2200A_RISC_ROM_VER 4
93#define FPM_2300 6
94#define FPM_2310 7
95
96#include "qla_settings.h"
97
Quinn Tran726b8542017-01-19 22:28:00 -080098#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
99
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700100/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 * Data bit definitions
102 */
103#define BIT_0 0x1
104#define BIT_1 0x2
105#define BIT_2 0x4
106#define BIT_3 0x8
107#define BIT_4 0x10
108#define BIT_5 0x20
109#define BIT_6 0x40
110#define BIT_7 0x80
111#define BIT_8 0x100
112#define BIT_9 0x200
113#define BIT_10 0x400
114#define BIT_11 0x800
115#define BIT_12 0x1000
116#define BIT_13 0x2000
117#define BIT_14 0x4000
118#define BIT_15 0x8000
119#define BIT_16 0x10000
120#define BIT_17 0x20000
121#define BIT_18 0x40000
122#define BIT_19 0x80000
123#define BIT_20 0x100000
124#define BIT_21 0x200000
125#define BIT_22 0x400000
126#define BIT_23 0x800000
127#define BIT_24 0x1000000
128#define BIT_25 0x2000000
129#define BIT_26 0x4000000
130#define BIT_27 0x8000000
131#define BIT_28 0x10000000
132#define BIT_29 0x20000000
133#define BIT_30 0x40000000
134#define BIT_31 0x80000000
135
136#define LSB(x) ((uint8_t)(x))
137#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
138
139#define LSW(x) ((uint16_t)(x))
140#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
141
142#define LSD(x) ((uint32_t)((uint64_t)(x)))
143#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
144
Bart Van Asschec25eb702020-02-19 20:34:40 -0800145static inline uint32_t make_handle(uint16_t x, uint16_t y)
146{
147 return ((uint32_t)x << 16) | y;
148}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149
150/*
151 * I/O register
152*/
153
Bart Van Assche04474d32020-05-18 14:17:08 -0700154static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700155{
156 return readb(addr);
157}
158
Bart Van Assche04474d32020-05-18 14:17:08 -0700159static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700160{
161 return readw(addr);
162}
163
Bart Van Assche04474d32020-05-18 14:17:08 -0700164static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700165{
166 return readl(addr);
167}
168
Bart Van Assche04474d32020-05-18 14:17:08 -0700169static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700170{
171 return readb_relaxed(addr);
172}
173
Bart Van Assche04474d32020-05-18 14:17:08 -0700174static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700175{
176 return readw_relaxed(addr);
177}
178
Bart Van Assche04474d32020-05-18 14:17:08 -0700179static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
Bart Van Assche37139da2020-05-18 14:17:07 -0700180{
181 return readl_relaxed(addr);
182}
183
Bart Van Assche04474d32020-05-18 14:17:08 -0700184static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
Bart Van Assche37139da2020-05-18 14:17:07 -0700185{
186 return writeb(data, addr);
187}
188
Bart Van Assche04474d32020-05-18 14:17:08 -0700189static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
Bart Van Assche37139da2020-05-18 14:17:07 -0700190{
191 return writew(data, addr);
192}
193
Bart Van Assche04474d32020-05-18 14:17:08 -0700194static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
Bart Van Assche37139da2020-05-18 14:17:07 -0700195{
196 return writel(data, addr);
197}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
199/*
Santosh Vernekar7d613ac2012-08-22 14:21:03 -0400200 * ISP83XX specific remote register addresses
201 */
202#define QLA83XX_LED_PORT0 0x00201320
203#define QLA83XX_LED_PORT1 0x00201328
204#define QLA83XX_IDC_DEV_STATE 0x22102384
205#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
206#define QLA83XX_IDC_MINOR_VERSION 0x22102398
207#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
208#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
209#define QLA83XX_IDC_CONTROL 0x22102390
210#define QLA83XX_IDC_AUDIT 0x22102394
211#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
212#define QLA83XX_DRIVER_LOCKID 0x22102104
213#define QLA83XX_DRIVER_LOCK 0x8111c028
214#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
215#define QLA83XX_FLASH_LOCKID 0x22102100
216#define QLA83XX_FLASH_LOCK 0x8111c010
217#define QLA83XX_FLASH_UNLOCK 0x8111c014
218#define QLA83XX_DEV_PARTINFO1 0x221023e0
219#define QLA83XX_DEV_PARTINFO2 0x221023e4
220#define QLA83XX_FW_HEARTBEAT 0x221020b0
221#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
222#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
223
224/* 83XX: Macros defining 8200 AEN Reason codes */
225#define IDC_DEVICE_STATE_CHANGE BIT_0
226#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
227#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
228#define IDC_HEARTBEAT_FAILURE BIT_3
229
230/* 83XX: Macros defining 8200 AEN Error-levels */
231#define ERR_LEVEL_NON_FATAL 0x1
232#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
233#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
234
235/* 83XX: Macros for IDC Version */
236#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
237#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
238
239/* 83XX: Macros for scheduling dpc tasks */
240#define QLA83XX_NIC_CORE_RESET 0x1
241#define QLA83XX_IDC_STATE_HANDLER 0x2
242#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
243
244/* 83XX: Macros for defining IDC-Control bits */
245#define QLA83XX_IDC_RESET_DISABLED BIT_0
246#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
247
248/* 83XX: Macros for different timeouts */
249#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
250#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
251#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
252
253/* 83XX: Macros for defining class in DEV-Partition Info register */
254#define QLA83XX_CLASS_TYPE_NONE 0x0
255#define QLA83XX_CLASS_TYPE_NIC 0x1
256#define QLA83XX_CLASS_TYPE_FCOE 0x2
257#define QLA83XX_CLASS_TYPE_ISCSI 0x3
258
259/* 83XX: Macros for IDC Lock-Recovery stages */
260#define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
261 * lock-recovery
262 */
263#define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
264
265/* 83XX: Macros for IDC Audit type */
266#define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
267 * dev-state change to NEED-RESET
268 * or NEED-QUIESCENT
269 */
270#define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
271 * reset-recovery completion is
272 * second
273 */
Himanshu Madhani2d5a4c32014-09-25 05:16:55 -0400274/* ISP2031: Values for laser on/off */
275#define PORT_0_2031 0x00201340
276#define PORT_1_2031 0x00201350
277#define LASER_ON_2031 0x01800100
278#define LASER_OFF_2031 0x01800180
Santosh Vernekar7d613ac2012-08-22 14:21:03 -0400279
280/*
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800281 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
282 * 133Mhz slot.
283 */
284#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
Bart Van Asschec1c71782019-08-08 20:01:24 -0700285#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800286
287/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 * Fibre Channel device definitions.
289 */
290#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
Chad Dupuis642ef982012-02-09 11:15:57 -0800291#define MAX_FIBRE_DEVICES_2100 512
292#define MAX_FIBRE_DEVICES_2400 2048
293#define MAX_FIBRE_DEVICES_LOOP 128
294#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
Chad Dupuis5f16b332012-08-22 14:21:00 -0400295#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
Andrew Vasquezcc4731f2005-07-06 10:32:37 -0700296#define MAX_FIBRE_LUNS 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297#define MAX_HOST_COUNT 16
298
299/*
300 * Host adapter default definitions.
301 */
302#define MAX_BUSES 1 /* We only have one bus today */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303#define MIN_LUNS 8
304#define MAX_LUNS MAX_FIBRE_LUNS
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700305#define MAX_CMDS_PER_LUN 255
306
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307/*
308 * Fibre Channel device definitions.
309 */
310#define SNS_LAST_LOOP_ID_2100 0xfe
311#define SNS_LAST_LOOP_ID_2300 0x7ff
312
313#define LAST_LOCAL_LOOP_ID 0x7d
314#define SNS_FL_PORT 0x7e
315#define FABRIC_CONTROLLER 0x7f
316#define SIMPLE_NAME_SERVER 0x80
317#define SNS_FIRST_LOOP_ID 0x81
318#define MANAGEMENT_SERVER 0xfe
319#define BROADCAST 0xff
320
Andrew Vasquez3d716442005-07-06 10:30:26 -0700321/*
322 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
323 * valid range of an N-PORT id is 0 through 0x7ef.
324 */
himanshu.madhani@cavium.com1429f042017-12-28 12:33:25 -0800325#define NPH_LAST_HANDLE 0x7ee
326#define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700327#define NPH_SNS 0x7fc /* FFFFFC */
328#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
329#define NPH_F_PORT 0x7fe /* FFFFFE */
330#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
331
Quinn Tranb98ae0d2017-06-02 09:12:00 -0700332#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
333
Andrew Vasquez3d716442005-07-06 10:30:26 -0700334#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
335#include "qla_fw.h"
Quinn Tran726b8542017-01-19 22:28:00 -0800336
337struct name_list_extended {
338 struct get_name_list_extended *l;
339 dma_addr_t ldma;
Hannes Reinecke1c6cacf2018-02-22 09:49:35 +0100340 struct list_head fcports;
Quinn Tran726b8542017-01-19 22:28:00 -0800341 u32 size;
Quinn Tran0aca7782018-09-04 14:19:16 -0700342 u8 sent;
Quinn Tran726b8542017-01-19 22:28:00 -0800343};
Quinn Tran84318a92021-06-23 22:25:58 -0700344
345struct els_reject {
346 struct fc_els_ls_rjt *c;
347 dma_addr_t cdma;
348 u16 size;
349};
350
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351/*
352 * Timeout timer counts in seconds
353 */
8482e1182005-04-17 15:04:54 -0500354#define PORT_RETRY_TIME 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355#define LOOP_DOWN_TIMEOUT 60
356#define LOOP_DOWN_TIME 255 /* 240 */
357#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
358
Quinn Trane7b42e32015-12-17 14:57:09 -0500359#define DEFAULT_OUTSTANDING_COMMANDS 4096
Chad Dupuis8d93f552013-01-30 03:34:37 -0500360#define MIN_OUTSTANDING_COMMANDS 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
362/* ISP request and response entry counts (37-65535) */
363#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
364#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
Andrew Vasquezd743de62009-03-24 09:08:15 -0700365#define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
Saurav Kashyapf2ea6532014-09-25 06:14:54 -0400366#define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
Quinn Trane7b42e32015-12-17 14:57:09 -0500367#define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
369#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -0700370#define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
Nicholas Bellinger2d70c102012-05-15 14:34:28 -0400371#define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400372#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
Quinn Tran99e1b682017-06-02 09:12:03 -0700373#define FW_DEF_EXCHANGES_CNT 2048
Quinn Trand1e36352017-12-28 12:33:12 -0800374#define FW_MAX_EXCHANGES_CNT (32 * 1024)
375#define REDUCE_EXCHANGES_CNT (8 * 1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
Quinn Tran7ebb336e2021-06-23 22:25:56 -0700377#define SET_DID_STATUS(stat_var, status) (stat_var = status << 16)
378
Anirban Chakraborty17d98632008-12-18 10:06:15 -0800379struct req_que;
Alexei Potashnika6ca8872015-07-14 16:00:44 -0400380struct qla_tgt_sess;
Anirban Chakraborty17d98632008-12-18 10:06:15 -0800381
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382/*
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700383 * SCSI Request Block
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 */
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800385struct srb_cmd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 uint32_t request_sense_length;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400388 uint32_t fw_sense_length;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 uint8_t *request_sense_ptr;
Bart Van Assche5ec9f902019-08-08 20:02:12 -0700390 struct ct6_dsd *ct6_ctx;
391 struct crc_context *crc_ctx;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800392};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
394/*
395 * SRB flag definitions
396 */
Arun Easibad75002010-05-04 15:01:30 -0700397#define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
398#define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
399#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
400#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
401#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
Quinn Tranf6145e82018-08-02 13:16:54 -0700402#define SRB_WAKEUP_ON_COMP BIT_6
Giridhar Malavali50b81272018-12-21 09:33:45 -0800403#define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
Quinn Trandd307062021-06-23 22:26:00 -0700404#define SRB_EDIF_CLEANUP_DELETE BIT_9
Arun Easibad75002010-05-04 15:01:30 -0700405
406/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
407#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
Quinn Tranf7a0ed472021-03-29 01:52:25 -0700408#define ISP_REG16_DISCONNECT 0xFFFF
Quinn Tran2d73ac62017-12-04 14:45:02 -0800409
Bart Van Asschedf95f392019-08-08 20:01:58 -0700410static inline le_id_t be_id_to_le(be_id_t id)
411{
412 le_id_t res;
413
414 res.domain = id.domain;
415 res.area = id.area;
416 res.al_pa = id.al_pa;
417
418 return res;
419}
420
421static inline be_id_t le_id_to_be(le_id_t id)
422{
423 be_id_t res;
424
425 res.domain = id.domain;
426 res.area = id.area;
427 res.al_pa = id.al_pa;
428
429 return res;
430}
431
432static inline port_id_t be_to_port_id(be_id_t id)
433{
434 port_id_t res;
435
436 res.b.domain = id.domain;
437 res.b.area = id.area;
438 res.b.al_pa = id.al_pa;
439 res.b.rsvd_1 = 0;
440
441 return res;
442}
443
444static inline be_id_t port_id_to_be_id(port_id_t port_id)
445{
446 be_id_t res;
447
448 res.domain = port_id.b.domain;
449 res.area = port_id.b.area;
450 res.al_pa = port_id.b.al_pa;
451
452 return res;
453}
454
Himanshu Madhani6eb54712015-12-17 14:57:00 -0500455struct els_logo_payload {
456 uint8_t opcode;
457 uint8_t rsvd[3];
458 uint8_t s_id[3];
459 uint8_t rsvd1[1];
460 uint8_t wwpn[WWN_SIZE];
461};
462
Duane Grigsbyedd05de2017-10-13 09:34:06 -0700463struct els_plogi_payload {
464 uint8_t opcode;
465 uint8_t rsvd[3];
Bart Van Assche1ee5ac32020-02-19 20:34:38 -0800466 __be32 data[112 / 4];
Duane Grigsbyedd05de2017-10-13 09:34:06 -0700467};
468
Quinn Tran726b8542017-01-19 22:28:00 -0800469struct ct_arg {
470 void *iocb;
471 u16 nport_handle;
472 dma_addr_t req_dma;
473 dma_addr_t rsp_dma;
474 u32 req_size;
475 u32 rsp_size;
Quinn Tranb5f3bc32018-07-02 13:01:58 -0700476 u32 req_allocated_size;
477 u32 rsp_allocated_size;
Quinn Tran726b8542017-01-19 22:28:00 -0800478 void *req;
479 void *rsp;
Quinn Tran2d73ac62017-12-04 14:45:02 -0800480 port_id_t id;
Quinn Tran726b8542017-01-19 22:28:00 -0800481};
482
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483/*
Andrew Vasquezac280b62009-08-20 11:06:05 -0700484 * SRB extensions.
485 */
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700486struct srb_iocb {
487 union {
488 struct {
489 uint16_t flags;
490#define SRB_LOGIN_RETRIED BIT_0
491#define SRB_LOGIN_COND_PLOGI BIT_1
492#define SRB_LOGIN_SKIP_PRLI BIT_2
Duane Grigsbya5d42f42017-06-21 13:48:41 -0700493#define SRB_LOGIN_NVME_PRLI BIT_3
Quinn Tran48acad02018-08-02 13:16:44 -0700494#define SRB_LOGIN_PRLI_ONLY BIT_4
Quinn Tran9efea842021-06-23 22:26:02 -0700495#define SRB_LOGIN_FCSP BIT_5
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700496 uint16_t data[2];
Quinn Tran726b8542017-01-19 22:28:00 -0800497 u32 iop[2];
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700498 } logio;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700499 struct {
Himanshu Madhani6eb54712015-12-17 14:57:00 -0500500#define ELS_DCMD_TIMEOUT 20
501#define ELS_DCMD_LOGO 0x5
502 uint32_t flags;
503 uint32_t els_cmd;
504 struct completion comp;
505 struct els_logo_payload *els_logo_pyld;
506 dma_addr_t els_logo_pyld_dma;
507 } els_logo;
Bart Van Asschec6e58162019-08-08 20:02:16 -0700508 struct els_plogi {
Duane Grigsbyedd05de2017-10-13 09:34:06 -0700509#define ELS_DCMD_PLOGI 0x3
510 uint32_t flags;
511 uint32_t els_cmd;
512 struct completion comp;
513 struct els_plogi_payload *els_plogi_pyld;
514 struct els_plogi_payload *els_resp_pyld;
Quinn Tran8777e432018-08-02 13:16:57 -0700515 u32 tx_size;
516 u32 rx_size;
Duane Grigsbyedd05de2017-10-13 09:34:06 -0700517 dma_addr_t els_plogi_pyld_dma;
518 dma_addr_t els_resp_pyld_dma;
Bart Van Assche21038b02020-05-18 14:17:11 -0700519 __le32 fw_status[3];
Duane Grigsbyedd05de2017-10-13 09:34:06 -0700520 __le16 comp_status;
521 __le16 len;
522 } els_plogi;
523 struct {
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700524 /*
525 * Values for flags field below are as
526 * defined in tsk_mgmt_entry struct
527 * for control_flags field in qla_fw.h.
528 */
Hannes Reinecke9cb78c12014-06-25 15:27:36 +0200529 uint64_t lun;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700530 uint32_t flags;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700531 uint32_t data;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400532 struct completion comp;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400533 __le16 comp_status;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700534 } tmf;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400535 struct {
536#define SRB_FXDISC_REQ_DMA_VALID BIT_0
537#define SRB_FXDISC_RESP_DMA_VALID BIT_1
538#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
539#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
540#define FXDISC_TIMEOUT 20
541 uint8_t flags;
542 uint32_t req_len;
543 uint32_t rsp_len;
544 void *req_addr;
545 void *rsp_addr;
546 dma_addr_t req_dma_handle;
547 dma_addr_t rsp_dma_handle;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400548 __le32 adapter_id;
549 __le32 adapter_id_hi;
550 __le16 req_func_type;
551 __le32 req_data;
552 __le32 req_data_extra;
553 __le32 result;
554 __le32 seq_number;
555 __le16 fw_flags;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400556 struct completion fxiocb_comp;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400557 __le32 reserved_0;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400558 uint8_t reserved_1;
559 } fxiocb;
560 struct {
561 uint32_t cmd_hndl;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400562 __le16 comp_status;
Darren Trappb027a5a2018-01-15 20:46:51 -0800563 __le16 req_que_no;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400564 struct completion comp;
565 } abt;
Quinn Tran726b8542017-01-19 22:28:00 -0800566 struct ct_arg ctarg;
Quinn Tran15f30a52017-03-15 09:48:52 -0700567#define MAX_IOCB_MB_REG 28
568#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
Quinn Tran726b8542017-01-19 22:28:00 -0800569 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -0700570 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
571 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
Quinn Tran726b8542017-01-19 22:28:00 -0800572 void *out, *in;
573 dma_addr_t out_dma, in_dma;
Quinn Tran15f30a52017-03-15 09:48:52 -0700574 struct completion comp;
575 int rc;
Quinn Tran726b8542017-01-19 22:28:00 -0800576 } mbx;
577 struct {
578 struct imm_ntfy_from_isp *ntfy;
579 } nack;
Duane Grigsby7401bc12017-06-21 13:48:42 -0700580 struct {
581 __le16 comp_status;
Bart Van Assche21038b02020-05-18 14:17:11 -0700582 __le16 rsp_pyld_len;
Duane Grigsby7401bc12017-06-21 13:48:42 -0700583 uint8_t aen_op;
584 void *desc;
585
586 /* These are only used with ls4 requests */
587 int cmd_len;
588 int rsp_len;
589 dma_addr_t cmd_dma;
590 dma_addr_t rsp_dma;
Duane Grigsbye84067d2017-06-21 13:48:43 -0700591 enum nvmefc_fcp_datadir dir;
Duane Grigsby7401bc12017-06-21 13:48:42 -0700592 uint32_t dl;
593 uint32_t timeout_sec;
Duane Grigsbycf19c452017-08-23 15:04:58 -0700594 struct list_head entry;
Duane Grigsby7401bc12017-06-21 13:48:42 -0700595 } nvme;
Quinn Tran28531922017-12-28 12:33:10 -0800596 struct {
597 u16 cmd;
598 u16 vp_index;
599 } ctrlvp;
Quinn Trandd307062021-06-23 22:26:00 -0700600 struct {
601 struct edif_sa_ctl *sa_ctl;
602 struct qla_sa_update_frame sa_frame;
603 } sa_update;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700604 } u;
Andrew Vasquez99b0bec2010-05-04 15:01:25 -0700605
Andrew Vasquezac280b62009-08-20 11:06:05 -0700606 struct timer_list timer;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800607 void (*timeout)(void *);
Andrew Vasquezac280b62009-08-20 11:06:05 -0700608};
609
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700610/* Values for srb_ctx type */
611#define SRB_LOGIN_CMD 1
612#define SRB_LOGOUT_CMD 2
613#define SRB_ELS_CMD_RPT 3
614#define SRB_ELS_CMD_HST 4
615#define SRB_CT_CMD 5
616#define SRB_ADISC_CMD 6
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700617#define SRB_TM_CMD 7
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800618#define SRB_SCSI_CMD 8
Saurav Kashyapa9b6f722012-08-22 14:21:01 -0400619#define SRB_BIDI_CMD 9
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400620#define SRB_FXIOCB_DCMD 10
621#define SRB_FXIOCB_BCMD 11
622#define SRB_ABT_CMD 12
Himanshu Madhani6eb54712015-12-17 14:57:00 -0500623#define SRB_ELS_DCMD 13
Quinn Tran726b8542017-01-19 22:28:00 -0800624#define SRB_MB_IOCB 14
625#define SRB_CT_PTHRU_CMD 15
626#define SRB_NACK_PLOGI 16
627#define SRB_NACK_PRLI 17
628#define SRB_NACK_LOGO 18
Duane Grigsby7401bc12017-06-21 13:48:42 -0700629#define SRB_NVME_CMD 19
Duane Grigsbye84067d2017-06-21 13:48:43 -0700630#define SRB_NVME_LS 20
Duane Grigsbya5d42f42017-06-21 13:48:41 -0700631#define SRB_PRLI_CMD 21
Quinn Tran28531922017-12-28 12:33:10 -0800632#define SRB_CTRL_VP 22
Quinn Tran11aea162017-12-28 12:33:20 -0800633#define SRB_PRLO_CMD 23
Quinn Tran84318a92021-06-23 22:25:58 -0700634#define SRB_SA_UPDATE 25
635#define SRB_ELS_CMD_HST_NOLOGIN 26
636#define SRB_SA_REPLACE 27
637
638struct qla_els_pt_arg {
639 u8 els_opcode;
640 u8 vp_idx;
641 __le16 nport_handle;
Quinn Tran6c9998c2021-10-26 04:54:07 -0700642 u16 control_flags, ox_id;
Quinn Tran84318a92021-06-23 22:25:58 -0700643 __le32 rx_xchg_address;
Quinn Tran6c9998c2021-10-26 04:54:07 -0700644 port_id_t did, sid;
Quinn Tran84318a92021-06-23 22:25:58 -0700645 u32 tx_len, tx_byte_count, rx_len, rx_byte_count;
646 dma_addr_t tx_addr, rx_addr;
647
648};
Andrew Vasquezac280b62009-08-20 11:06:05 -0700649
Quinn Tranc5419e22017-06-13 20:47:16 -0700650enum {
651 TYPE_SRB,
652 TYPE_TGT_CMD,
Quinn Tran6b0431d2018-09-04 14:19:13 -0700653 TYPE_TGT_TMCMD, /* task management */
Quinn Tranc5419e22017-06-13 20:47:16 -0700654};
655
Quinn Tran89c72f42020-09-03 21:51:26 -0700656struct iocb_resource {
657 u8 res_type;
658 u8 pad;
659 u16 iocb_cnt;
660};
661
Quinn Tran84318a92021-06-23 22:25:58 -0700662struct bsg_cmd {
663 struct bsg_job *bsg_job;
664 union {
665 struct qla_els_pt_arg els_arg;
666 } u;
667};
668
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800669typedef struct srb {
Quinn Tranc5419e22017-06-13 20:47:16 -0700670 /*
671 * Do not move cmd_type field, it needs to
672 * line up with qla_tgt_cmd->cmd_type
673 */
674 uint8_t cmd_type;
675 uint8_t pad[3];
Quinn Tran89c72f42020-09-03 21:51:26 -0700676 struct iocb_resource iores;
Quinn Tran4c2a2d02019-06-21 09:50:24 -0700677 struct kref cmd_kref; /* need to migrate ref_count over to this */
678 void *priv;
himanshu.madhani@cavium.com6fcd98f2017-07-21 09:32:23 -0700679 wait_queue_head_t nvme_ls_waitq;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800680 struct fc_port *fcport;
Joe Carnuccio25ff6af2017-01-19 22:28:04 -0800681 struct scsi_qla_host *vha;
Quinn Tran3a4b6cc2019-07-26 09:07:33 -0700682 unsigned int start_timer:1;
Quinn Tranf45bca82019-11-05 07:06:54 -0800683
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800684 uint32_t handle;
685 uint16_t flags;
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800686 uint16_t type;
Quinn Tran15f30a52017-03-15 09:48:52 -0700687 const char *name;
Andrew Vasquez57807902011-11-18 09:03:20 -0800688 int iocbs;
Michael Hernandezd7459522016-12-12 14:40:07 -0800689 struct qla_qpair *qpair;
Quinn Tran71c80b72019-11-05 07:06:51 -0800690 struct srb *cmd_sp;
Quinn Tran2d73ac62017-12-04 14:45:02 -0800691 struct list_head elem;
Quinn Tran726b8542017-01-19 22:28:00 -0800692 u32 gen1; /* scratch */
693 u32 gen2; /* scratch */
Quinn Tran28531922017-12-28 12:33:10 -0800694 int rc;
Quinn Trane374f9f2017-12-28 12:33:31 -0800695 int retry_count;
Bart Van Assche982cc4b2019-04-17 14:44:34 -0700696 struct completion *comp;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700697 union {
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800698 struct srb_iocb iocb_cmd;
Johannes Thumshirn75cc8cf2016-11-17 10:31:19 +0100699 struct bsg_job *bsg_job;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800700 struct srb_cmd scmd;
Quinn Tran84318a92021-06-23 22:25:58 -0700701 struct bsg_cmd bsg_cmd;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700702 } u;
Quinn Tran84318a92021-06-23 22:25:58 -0700703 struct {
704 bool remapped;
705 struct {
706 dma_addr_t dma;
707 void *buf;
708 uint len;
709 } req;
710 struct {
711 dma_addr_t dma;
712 void *buf;
713 uint len;
714 } rsp;
715 } remap;
Bart Van Assche6c18a432019-08-08 20:02:04 -0700716 /*
717 * Report completion status @res and call sp_put(@sp). @res is
718 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
719 * QLA_* status value.
720 */
721 void (*done)(struct srb *sp, int res);
722 /* Stop the timer and free @sp. Only used by the FCP code. */
723 void (*free)(struct srb *sp);
724 /*
725 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
726 * code.
727 */
Quinn Tran4c2a2d02019-06-21 09:50:24 -0700728 void (*put_fn)(struct kref *kref);
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800729} srb_t;
730
731#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800732
733#define GET_CMD_SENSE_LEN(sp) \
734 (sp->u.scmd.request_sense_length)
735#define SET_CMD_SENSE_LEN(sp, len) \
736 (sp->u.scmd.request_sense_length = len)
737#define GET_CMD_SENSE_PTR(sp) \
738 (sp->u.scmd.request_sense_ptr)
739#define SET_CMD_SENSE_PTR(sp, ptr) \
740 (sp->u.scmd.request_sense_ptr = ptr)
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400741#define GET_FW_SENSE_LEN(sp) \
742 (sp->u.scmd.fw_sense_length)
743#define SET_FW_SENSE_LEN(sp, len) \
744 (sp->u.scmd.fw_sense_length = len)
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800745
746struct msg_echo_lb {
747 dma_addr_t send_dma;
748 dma_addr_t rcv_dma;
749 uint16_t req_sg_cnt;
750 uint16_t rsp_sg_cnt;
751 uint16_t options;
752 uint32_t transfer_size;
Joe Carnuccio1b98b422013-03-28 08:21:26 -0400753 uint32_t iteration_count;
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800754};
755
Andrew Vasquezac280b62009-08-20 11:06:05 -0700756/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 * ISP I/O Register Set structure definitions.
758 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700759struct device_reg_2xxx {
Bart Van Assche21038b02020-05-18 14:17:11 -0700760 __le16 flash_address; /* Flash BIOS address */
761 __le16 flash_data; /* Flash BIOS data */
762 __le16 unused_1[1]; /* Gap */
763 __le16 ctrl_status; /* Control/Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700764#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
766#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
767
Bart Van Assche21038b02020-05-18 14:17:11 -0700768 __le16 ictrl; /* Interrupt control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
770#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
771
Bart Van Assche21038b02020-05-18 14:17:11 -0700772 __le16 istatus; /* Interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773#define ISR_RISC_INT BIT_3 /* RISC interrupt */
774
Bart Van Assche21038b02020-05-18 14:17:11 -0700775 __le16 semaphore; /* Semaphore */
776 __le16 nvram; /* NVRAM register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777#define NVR_DESELECT 0
778#define NVR_BUSY BIT_15
779#define NVR_WRT_ENABLE BIT_14 /* Write enable */
780#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
781#define NVR_DATA_IN BIT_3
782#define NVR_DATA_OUT BIT_2
783#define NVR_SELECT BIT_1
784#define NVR_CLOCK BIT_0
785
Ravi Anand45aeaf12006-05-17 15:08:49 -0700786#define NVR_WAIT_CNT 20000
787
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788 union {
789 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -0700790 __le16 mailbox0;
791 __le16 mailbox1;
792 __le16 mailbox2;
793 __le16 mailbox3;
794 __le16 mailbox4;
795 __le16 mailbox5;
796 __le16 mailbox6;
797 __le16 mailbox7;
798 __le16 unused_2[59]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 } __attribute__((packed)) isp2100;
800 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700801 /* Request Queue */
Bart Van Assche21038b02020-05-18 14:17:11 -0700802 __le16 req_q_in; /* In-Pointer */
803 __le16 req_q_out; /* Out-Pointer */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700804 /* Response Queue */
Bart Van Assche21038b02020-05-18 14:17:11 -0700805 __le16 rsp_q_in; /* In-Pointer */
806 __le16 rsp_q_out; /* Out-Pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
808 /* RISC to Host Status */
Bart Van Assche21038b02020-05-18 14:17:11 -0700809 __le32 host_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810#define HSR_RISC_INT BIT_15 /* RISC interrupt */
811#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
812
813 /* Host to Host Semaphore */
Bart Van Assche21038b02020-05-18 14:17:11 -0700814 __le16 host_semaphore;
815 __le16 unused_3[17]; /* Gap */
816 __le16 mailbox0;
817 __le16 mailbox1;
818 __le16 mailbox2;
819 __le16 mailbox3;
820 __le16 mailbox4;
821 __le16 mailbox5;
822 __le16 mailbox6;
823 __le16 mailbox7;
824 __le16 mailbox8;
825 __le16 mailbox9;
826 __le16 mailbox10;
827 __le16 mailbox11;
828 __le16 mailbox12;
829 __le16 mailbox13;
830 __le16 mailbox14;
831 __le16 mailbox15;
832 __le16 mailbox16;
833 __le16 mailbox17;
834 __le16 mailbox18;
835 __le16 mailbox19;
836 __le16 mailbox20;
837 __le16 mailbox21;
838 __le16 mailbox22;
839 __le16 mailbox23;
840 __le16 mailbox24;
841 __le16 mailbox25;
842 __le16 mailbox26;
843 __le16 mailbox27;
844 __le16 mailbox28;
845 __le16 mailbox29;
846 __le16 mailbox30;
847 __le16 mailbox31;
848 __le16 fb_cmd;
849 __le16 unused_4[10]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 } __attribute__((packed)) isp2300;
851 } u;
852
Bart Van Assche21038b02020-05-18 14:17:11 -0700853 __le16 fpm_diag_config;
854 __le16 unused_5[0x4]; /* Gap */
855 __le16 risc_hw;
856 __le16 unused_5_1; /* Gap */
857 __le16 pcr; /* Processor Control Register. */
858 __le16 unused_6[0x5]; /* Gap */
859 __le16 mctr; /* Memory Configuration and Timing. */
860 __le16 unused_7[0x3]; /* Gap */
861 __le16 fb_cmd_2100; /* Unused on 23XX */
862 __le16 unused_8[0x3]; /* Gap */
863 __le16 hccr; /* Host command & control register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
865#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
866 /* HCCR commands */
867#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
868#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
869#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
870#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
871#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
872#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
873#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
874#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
875
Bart Van Assche21038b02020-05-18 14:17:11 -0700876 __le16 unused_9[5]; /* Gap */
877 __le16 gpiod; /* GPIO Data register. */
878 __le16 gpioe; /* GPIO Enable register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879#define GPIO_LED_MASK 0x00C0
880#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
881#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
882#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
883#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800884#define GPIO_LED_ALL_OFF 0x0000
885#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
886#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887
888 union {
889 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -0700890 __le16 unused_10[8]; /* Gap */
891 __le16 mailbox8;
892 __le16 mailbox9;
893 __le16 mailbox10;
894 __le16 mailbox11;
895 __le16 mailbox12;
896 __le16 mailbox13;
897 __le16 mailbox14;
898 __le16 mailbox15;
899 __le16 mailbox16;
900 __le16 mailbox17;
901 __le16 mailbox18;
902 __le16 mailbox19;
903 __le16 mailbox20;
904 __le16 mailbox21;
905 __le16 mailbox22;
906 __le16 mailbox23; /* Also probe reg. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 } __attribute__((packed)) isp2200;
908 } u_end;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700909};
910
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800911struct device_reg_25xxmq {
Bart Van Assche21038b02020-05-18 14:17:11 -0700912 __le32 req_q_in;
913 __le32 req_q_out;
914 __le32 rsp_q_in;
915 __le32 rsp_q_out;
916 __le32 atio_q_in;
917 __le32 atio_q_out;
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800918};
919
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400920
921struct device_reg_fx00 {
Bart Van Assche21038b02020-05-18 14:17:11 -0700922 __le32 mailbox0; /* 00 */
923 __le32 mailbox1; /* 04 */
924 __le32 mailbox2; /* 08 */
925 __le32 mailbox3; /* 0C */
926 __le32 mailbox4; /* 10 */
927 __le32 mailbox5; /* 14 */
928 __le32 mailbox6; /* 18 */
929 __le32 mailbox7; /* 1C */
930 __le32 mailbox8; /* 20 */
931 __le32 mailbox9; /* 24 */
932 __le32 mailbox10; /* 28 */
933 __le32 mailbox11;
934 __le32 mailbox12;
935 __le32 mailbox13;
936 __le32 mailbox14;
937 __le32 mailbox15;
938 __le32 mailbox16;
939 __le32 mailbox17;
940 __le32 mailbox18;
941 __le32 mailbox19;
942 __le32 mailbox20;
943 __le32 mailbox21;
944 __le32 mailbox22;
945 __le32 mailbox23;
946 __le32 mailbox24;
947 __le32 mailbox25;
948 __le32 mailbox26;
949 __le32 mailbox27;
950 __le32 mailbox28;
951 __le32 mailbox29;
952 __le32 mailbox30;
953 __le32 mailbox31;
954 __le32 aenmailbox0;
955 __le32 aenmailbox1;
956 __le32 aenmailbox2;
957 __le32 aenmailbox3;
958 __le32 aenmailbox4;
959 __le32 aenmailbox5;
960 __le32 aenmailbox6;
961 __le32 aenmailbox7;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400962 /* Request Queue. */
Bart Van Assche21038b02020-05-18 14:17:11 -0700963 __le32 req_q_in; /* A0 - Request Queue In-Pointer */
964 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400965 /* Response Queue. */
Bart Van Assche21038b02020-05-18 14:17:11 -0700966 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
967 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400968 /* Init values shadowed on FW Up Event */
Bart Van Assche21038b02020-05-18 14:17:11 -0700969 __le32 initval0; /* B0 */
970 __le32 initval1; /* B4 */
971 __le32 initval2; /* B8 */
972 __le32 initval3; /* BC */
973 __le32 initval4; /* C0 */
974 __le32 initval5; /* C4 */
975 __le32 initval6; /* C8 */
976 __le32 initval7; /* CC */
977 __le32 fwheartbeat; /* D0 */
978 __le32 pseudoaen; /* D4 */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400979};
980
981
982
Andrew Morton9a168bd2005-07-26 14:11:28 -0700983typedef union {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700984 struct device_reg_2xxx isp;
985 struct device_reg_24xx isp24;
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800986 struct device_reg_25xxmq isp25mq;
Giridhar Malavalia9083012010-04-12 17:59:55 -0700987 struct device_reg_82xx isp82;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400988 struct device_reg_fx00 ispfx00;
Chad Dupuisf73cb692014-02-26 04:15:06 -0500989} __iomem device_reg_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
991#define ISP_REQ_Q_IN(ha, reg) \
992 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
993 &(reg)->u.isp2100.mailbox4 : \
994 &(reg)->u.isp2300.req_q_in)
995#define ISP_REQ_Q_OUT(ha, reg) \
996 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
997 &(reg)->u.isp2100.mailbox4 : \
998 &(reg)->u.isp2300.req_q_out)
999#define ISP_RSP_Q_IN(ha, reg) \
1000 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1001 &(reg)->u.isp2100.mailbox5 : \
1002 &(reg)->u.isp2300.rsp_q_in)
1003#define ISP_RSP_Q_OUT(ha, reg) \
1004 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1005 &(reg)->u.isp2100.mailbox5 : \
1006 &(reg)->u.isp2300.rsp_q_out)
1007
Arun Easiaa230bc2013-01-30 03:34:39 -05001008#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
1009#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
1010
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011#define MAILBOX_REG(ha, reg, num) \
1012 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1013 (num < 8 ? \
1014 &(reg)->u.isp2100.mailbox0 + (num) : \
1015 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
1016 &(reg)->u.isp2300.mailbox0 + (num))
1017#define RD_MAILBOX_REG(ha, reg, num) \
Bart Van Assche04474d32020-05-18 14:17:08 -07001018 rd_reg_word(MAILBOX_REG(ha, reg, num))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019#define WRT_MAILBOX_REG(ha, reg, num, data) \
Bart Van Assche04474d32020-05-18 14:17:08 -07001020 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021
1022#define FB_CMD_REG(ha, reg) \
1023 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1024 &(reg)->fb_cmd_2100 : \
1025 &(reg)->u.isp2300.fb_cmd)
1026#define RD_FB_CMD_REG(ha, reg) \
Bart Van Assche04474d32020-05-18 14:17:08 -07001027 rd_reg_word(FB_CMD_REG(ha, reg))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028#define WRT_FB_CMD_REG(ha, reg, data) \
Bart Van Assche04474d32020-05-18 14:17:08 -07001029 wrt_reg_word(FB_CMD_REG(ha, reg), data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030
1031typedef struct {
1032 uint32_t out_mb; /* outbound from driver */
1033 uint32_t in_mb; /* Incoming from RISC */
1034 uint16_t mb[MAILBOX_REGISTER_COUNT];
1035 long buf_size;
1036 void *bufp;
1037 uint32_t tov;
1038 uint8_t flags;
1039#define MBX_DMA_IN BIT_0
1040#define MBX_DMA_OUT BIT_1
1041#define IOCTL_CMD BIT_2
1042} mbx_cmd_t;
1043
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04001044struct mbx_cmd_32 {
1045 uint32_t out_mb; /* outbound from driver */
1046 uint32_t in_mb; /* Incoming from RISC */
1047 uint32_t mb[MAILBOX_REGISTER_COUNT];
1048 long buf_size;
1049 void *bufp;
1050 uint32_t tov;
1051 uint8_t flags;
1052#define MBX_DMA_IN BIT_0
1053#define MBX_DMA_OUT BIT_1
1054#define IOCTL_CMD BIT_2
1055};
1056
1057
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058#define MBX_TOV_SECONDS 30
1059
1060/*
1061 * ISP product identification definitions in mailboxes after reset.
1062 */
1063#define PROD_ID_1 0x4953
1064#define PROD_ID_2 0x0000
1065#define PROD_ID_2a 0x5020
1066#define PROD_ID_3 0x2020
1067
1068/*
1069 * ISP mailbox Self-Test status codes
1070 */
1071#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
1072#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
1073#define MBS_BUSY 4 /* Busy. */
1074
1075/*
1076 * ISP mailbox command complete status codes
1077 */
1078#define MBS_COMMAND_COMPLETE 0x4000
1079#define MBS_INVALID_COMMAND 0x4001
1080#define MBS_HOST_INTERFACE_ERROR 0x4002
1081#define MBS_TEST_FAILED 0x4003
1082#define MBS_COMMAND_ERROR 0x4005
1083#define MBS_COMMAND_PARAMETER_ERROR 0x4006
1084#define MBS_PORT_ID_USED 0x4007
1085#define MBS_LOOP_ID_USED 0x4008
1086#define MBS_ALL_IDS_IN_USE 0x4009
1087#define MBS_NOT_LOGGED_IN 0x400A
Andrew Vasquez3d716442005-07-06 10:30:26 -07001088#define MBS_LINK_DOWN_ERROR 0x400B
1089#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090
Bart Van Assche72436192019-08-08 20:02:14 -07001091static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1092{
1093 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1094}
1095
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096/*
1097 * ISP mailbox asynchronous event status codes
1098 */
1099#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
1100#define MBA_RESET 0x8001 /* Reset Detected. */
1101#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
1102#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
1103#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
1104#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
1105#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
1106 /* occurred. */
1107#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
1108#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
1109#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
1110#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
1111#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1112#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1113#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1114#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
Shyam Sundar9f2475f2020-06-30 03:22:29 -07001115#define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1117#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1118#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1119#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1120#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1121#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1122#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1123#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1124 /* used. */
Andrew Vasquez45ebeb52006-08-01 13:48:14 -07001125#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1127#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1128#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1129#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1130#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1131#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1132#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1133#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1134#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1135#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1136#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1137#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1138#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04001139#define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1140#define MBA_FW_STARTING 0x8051 /* Firmware starting */
1141#define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1142#define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1143#define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
Joe Carnuccioa29b3dd2016-07-06 11:14:19 -04001144#define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
Joe Carnucciob5a340d2014-09-25 05:16:48 -04001145#define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
Sawan Chandak92d44082017-08-23 15:05:16 -07001146#define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
Andrew Vasquezb0f18ee2020-02-26 14:40:13 -08001147#define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04001148#define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1149#define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1150 Notification */
1151#define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
Armen Baloyanb6511d92013-08-27 01:37:31 -04001152#define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
Armen Baloyan0f8cdff2014-02-26 04:14:57 -05001153#define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04001154/* 83XX FCoE specific */
1155#define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1156
Arun Easifafbda92012-08-22 14:21:16 -04001157/* Interrupt type codes */
1158#define INTR_ROM_MB_SUCCESS 0x1
1159#define INTR_ROM_MB_FAILED 0x2
1160#define INTR_MB_SUCCESS 0x10
1161#define INTR_MB_FAILED 0x11
1162#define INTR_ASYNC_EVENT 0x12
1163#define INTR_RSP_QUE_UPDATE 0x13
1164#define INTR_RSP_QUE_UPDATE_83XX 0x14
1165#define INTR_ATIO_QUE_UPDATE 0x1C
1166#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
Himanshu Madhanic9558862017-10-13 09:34:04 -07001167#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
Arun Easifafbda92012-08-22 14:21:16 -04001168
Giridhar Malavali9a069e12010-01-12 13:02:47 -08001169/* ISP mailbox loopback echo diagnostic error code */
1170#define MBS_LB_RESET 0x17
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171/*
1172 * Firmware options 1, 2, 3.
1173 */
1174#define FO1_AE_ON_LIPF8 BIT_0
1175#define FO1_AE_ALL_LIP_RESET BIT_1
1176#define FO1_CTIO_RETRY BIT_3
1177#define FO1_DISABLE_LIP_F7_SW BIT_4
1178#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
Andrew Vasquez3d716442005-07-06 10:30:26 -07001179#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1181#define FO1_SET_EMPHASIS_SWING BIT_8
1182#define FO1_AE_AUTO_BYPASS BIT_9
1183#define FO1_ENABLE_PURE_IOCB BIT_10
1184#define FO1_AE_PLOGI_RJT BIT_11
1185#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1186#define FO1_AE_QUEUE_FULL BIT_13
1187
1188#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1189#define FO2_REV_LOOPBACK BIT_1
1190
1191#define FO3_ENABLE_EMERG_IOCB BIT_0
1192#define FO3_AE_RND_ERROR BIT_1
1193
Andrew Vasquez3d716442005-07-06 10:30:26 -07001194/* 24XX additional firmware options */
1195#define ADD_FO_COUNT 3
1196#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1197#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1198
1199#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1200
1201#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1202
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203/*
1204 * ISP mailbox commands
1205 */
1206#define MBC_LOAD_RAM 1 /* Load RAM. */
1207#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1209#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1210#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1211#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1212#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1213#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
Michael Hernandez3f006ac2019-03-12 11:08:22 -07001214#define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1216#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1217#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1218#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1219#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
Andrew Vasquezf6ef3b12005-08-26 19:10:20 -07001220#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1222#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1223#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1224#define MBC_RESET 0x18 /* Reset. */
1225#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
Duane Grigsbydeeae7a2017-07-21 09:32:25 -07001226#define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1228#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1229#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1230#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
Himanshu Madhanib0d6cab2015-12-17 14:56:56 -05001231#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
Joe Carnuccio07553b12020-02-12 13:44:12 -08001233#define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1235#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1236#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1237#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1238#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1239#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1240#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1241#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08001242#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1244#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
Andrew Vasquezaf11f642012-02-09 11:15:43 -08001245#define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1247#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
Joe Carnuccio90687a12013-02-08 01:57:59 -05001248#define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1249#define MBC_DATA_RATE 0x5d /* Data Rate */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1251#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1252 /* Initialization Procedure */
1253#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1254#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1255#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1256#define MBC_TARGET_RESET 0x66 /* Target Reset. */
1257#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1258#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1259#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1260#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1261#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1262#define MBC_LIP_RESET 0x6c /* LIP reset. */
1263#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1264 /* commandd. */
1265#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1266#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1267#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1268#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1269#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1270#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1271#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1272#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1273#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1274#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1275#define MBC_LUN_RESET 0x7E /* Send LUN reset */
1276
Andrew Vasquez3d716442005-07-06 10:30:26 -07001277/*
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04001278 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1279 * should be defined with MBC_MR_*
1280 */
1281#define MBC_MR_DRV_SHUTDOWN 0x6A
1282
1283/*
Andrew Vasquez3d716442005-07-06 10:30:26 -07001284 * ISP24xx mailbox commands
1285 */
Joe Carnucciodb64e932013-10-30 03:38:18 -04001286#define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1287#define MBC_READ_SERDES 0x4 /* Read serdes word. */
Chad Dupuisf73cb692014-02-26 04:15:06 -05001288#define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001289#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1290#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001291#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001292#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07001293#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001294#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
Joe Carnuccioad0ecd62009-03-24 09:08:12 -07001295#define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
Andrew Vasquez88729e52006-06-23 16:10:50 -07001296#define MBC_READ_SFP 0x31 /* Read SFP Data. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001297#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
Joe Carnucciob5a340d2014-09-25 05:16:48 -04001298#define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001299#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1300#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1301#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1302#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1303#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1304#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
Joe Carnuccio61e1b262013-02-08 01:57:48 -05001305#define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001306#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
Chad Dupuis8fcd6b82012-08-22 14:21:06 -04001307#define MBC_PORT_RESET 0x120 /* Port Reset */
Sarang Radke23f2ebd2010-05-28 15:08:21 -07001308#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1309#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001310
Madhuranath Iyengarb1d469892010-09-03 15:20:54 -07001311/*
1312 * ISP81xx mailbox commands
1313 */
1314#define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1315
Joe Carnuccioe8887c52014-04-11 16:54:17 -04001316/*
1317 * ISP8044 mailbox commands
1318 */
1319#define MBC_SET_GET_ETH_SERDES_REG 0x150
1320#define HCS_WRITE_SERDES 0x3
1321#define HCS_READ_SERDES 0x4
1322
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323/* Firmware return data sizes */
1324#define FCAL_MAP_SIZE 128
1325
1326/* Mailbox bit definitions for out_mb and in_mb */
1327#define MBX_31 BIT_31
1328#define MBX_30 BIT_30
1329#define MBX_29 BIT_29
1330#define MBX_28 BIT_28
1331#define MBX_27 BIT_27
1332#define MBX_26 BIT_26
1333#define MBX_25 BIT_25
1334#define MBX_24 BIT_24
1335#define MBX_23 BIT_23
1336#define MBX_22 BIT_22
1337#define MBX_21 BIT_21
1338#define MBX_20 BIT_20
1339#define MBX_19 BIT_19
1340#define MBX_18 BIT_18
1341#define MBX_17 BIT_17
1342#define MBX_16 BIT_16
1343#define MBX_15 BIT_15
1344#define MBX_14 BIT_14
1345#define MBX_13 BIT_13
1346#define MBX_12 BIT_12
1347#define MBX_11 BIT_11
1348#define MBX_10 BIT_10
1349#define MBX_9 BIT_9
1350#define MBX_8 BIT_8
1351#define MBX_7 BIT_7
1352#define MBX_6 BIT_6
1353#define MBX_5 BIT_5
1354#define MBX_4 BIT_4
1355#define MBX_3 BIT_3
1356#define MBX_2 BIT_2
1357#define MBX_1 BIT_1
1358#define MBX_0 BIT_0
1359
Joe Carnuccio818c7f82020-02-12 13:44:17 -08001360#define RNID_TYPE_ELS_CMD 0x5
Duane Grigsbya5d42f42017-06-21 13:48:41 -07001361#define RNID_TYPE_PORT_LOGIN 0x7
Joe Carnuccio818c7f82020-02-12 13:44:17 -08001362#define RNID_BUFFER_CREDITS 0x8
Joe Carnuccioc46e65c2013-08-27 01:37:35 -04001363#define RNID_TYPE_SET_VERSION 0x9
Joe Carnucciofe52f6e2013-02-08 01:58:03 -05001364#define RNID_TYPE_ASIC_TEMP 0xC
Joe Carnuccio3a117112013-02-08 01:58:00 -05001365
Joe Carnucciod83a80e2020-02-12 13:44:18 -08001366#define ELS_CMD_MAP_SIZE 32
Joe Carnucciod83a80e2020-02-12 13:44:18 -08001367
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368/*
1369 * Firmware state codes from get firmware state mailbox command
1370 */
1371#define FSTATE_CONFIG_WAIT 0
1372#define FSTATE_WAIT_AL_PA 1
1373#define FSTATE_WAIT_LOGIN 2
1374#define FSTATE_READY 3
1375#define FSTATE_LOSS_OF_SYNC 4
1376#define FSTATE_ERROR 5
1377#define FSTATE_REINIT 6
1378#define FSTATE_NON_PART 7
1379
1380#define FSTATE_CONFIG_CORRECT 0
1381#define FSTATE_P2P_RCV_LIP 1
1382#define FSTATE_P2P_CHOOSE_LOOP 2
1383#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1384#define FSTATE_FATAL_ERROR 4
1385#define FSTATE_LOOP_BACK_CONN 5
1386
Sawan Chandak4243c112016-01-27 12:03:31 -05001387#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1388#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1389#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
Joe Carnuccioecc89f22019-03-12 11:08:13 -07001390#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
Joe Carnuccio5fa87742019-03-12 11:08:21 -07001391#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1392#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1393#define QLA27XX_DEFAULT_IMAGE 0
Sawan Chandak4243c112016-01-27 12:03:31 -05001394#define QLA27XX_PRIMARY_IMAGE 1
1395#define QLA27XX_SECONDARY_IMAGE 2
1396
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397/*
1398 * Port Database structure definition
1399 * Little endian except where noted.
1400 */
1401#define PORT_DATABASE_SIZE 128 /* bytes */
1402typedef struct {
1403 uint8_t options;
1404 uint8_t control;
1405 uint8_t master_state;
1406 uint8_t slave_state;
1407 uint8_t reserved[2];
1408 uint8_t hard_address;
1409 uint8_t reserved_1;
1410 uint8_t port_id[4];
1411 uint8_t node_name[WWN_SIZE];
1412 uint8_t port_name[WWN_SIZE];
Bart Van Assche21038b02020-05-18 14:17:11 -07001413 __le16 execution_throttle;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414 uint16_t execution_count;
1415 uint8_t reset_count;
1416 uint8_t reserved_2;
1417 uint16_t resource_allocation;
1418 uint16_t current_allocation;
1419 uint16_t queue_head;
1420 uint16_t queue_tail;
1421 uint16_t transmit_execution_list_next;
1422 uint16_t transmit_execution_list_previous;
1423 uint16_t common_features;
1424 uint16_t total_concurrent_sequences;
1425 uint16_t RO_by_information_category;
1426 uint8_t recipient;
1427 uint8_t initiator;
1428 uint16_t receive_data_size;
1429 uint16_t concurrent_sequences;
1430 uint16_t open_sequences_per_exchange;
1431 uint16_t lun_abort_flags;
1432 uint16_t lun_stop_flags;
1433 uint16_t stop_queue_head;
1434 uint16_t stop_queue_tail;
1435 uint16_t port_retry_timer;
1436 uint16_t next_sequence_id;
1437 uint16_t frame_count;
1438 uint16_t PRLI_payload_length;
1439 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1440 /* Bits 15-0 of word 0 */
1441 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1442 /* Bits 15-0 of word 3 */
1443 uint16_t loop_id;
1444 uint16_t extended_lun_info_list_pointer;
1445 uint16_t extended_lun_stop_list_pointer;
1446} port_database_t;
1447
1448/*
1449 * Port database slave/master states
1450 */
1451#define PD_STATE_DISCOVERY 0
1452#define PD_STATE_WAIT_DISCOVERY_ACK 1
1453#define PD_STATE_PORT_LOGIN 2
1454#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1455#define PD_STATE_PROCESS_LOGIN 4
1456#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1457#define PD_STATE_PORT_LOGGED_IN 6
1458#define PD_STATE_PORT_UNAVAILABLE 7
1459#define PD_STATE_PROCESS_LOGOUT 8
1460#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1461#define PD_STATE_PORT_LOGOUT 10
1462#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1463
1464
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -07001465#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1466#define QLA_ZIO_DISABLED 0
1467#define QLA_ZIO_DEFAULT_TIMER 2
1468
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469/*
1470 * ISP Initialization Control Block.
1471 * Little endian except where noted.
1472 */
1473#define ICB_VERSION 1
1474typedef struct {
1475 uint8_t version;
1476 uint8_t reserved_1;
1477
1478 /*
1479 * LSB BIT 0 = Enable Hard Loop Id
1480 * LSB BIT 1 = Enable Fairness
1481 * LSB BIT 2 = Enable Full-Duplex
1482 * LSB BIT 3 = Enable Fast Posting
1483 * LSB BIT 4 = Enable Target Mode
1484 * LSB BIT 5 = Disable Initiator Mode
1485 * LSB BIT 6 = Enable ADISC
1486 * LSB BIT 7 = Enable Target Inquiry Data
1487 *
1488 * MSB BIT 0 = Enable PDBC Notify
1489 * MSB BIT 1 = Non Participating LIP
1490 * MSB BIT 2 = Descending Loop ID Search
1491 * MSB BIT 3 = Acquire Loop ID in LIPA
1492 * MSB BIT 4 = Stop PortQ on Full Status
1493 * MSB BIT 5 = Full Login after LIP
1494 * MSB BIT 6 = Node Name Option
1495 * MSB BIT 7 = Ext IFWCB enable bit
1496 */
1497 uint8_t firmware_options[2];
1498
Bart Van Assche21038b02020-05-18 14:17:11 -07001499 __le16 frame_payload_size;
1500 __le16 max_iocb_allocation;
1501 __le16 execution_throttle;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502 uint8_t retry_count;
1503 uint8_t retry_delay; /* unused */
1504 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1505 uint16_t hard_address;
1506 uint8_t inquiry_data;
1507 uint8_t login_timeout;
1508 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1509
Bart Van Assche21038b02020-05-18 14:17:11 -07001510 __le16 request_q_outpointer;
1511 __le16 response_q_inpointer;
1512 __le16 request_q_length;
1513 __le16 response_q_length;
1514 __le64 request_q_address __packed;
1515 __le64 response_q_address __packed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516
Bart Van Assche21038b02020-05-18 14:17:11 -07001517 __le16 lun_enables;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 uint8_t command_resource_count;
1519 uint8_t immediate_notify_resource_count;
Bart Van Assche21038b02020-05-18 14:17:11 -07001520 __le16 timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 uint8_t reserved_2[2];
1522
1523 /*
1524 * LSB BIT 0 = Timer Operation mode bit 0
1525 * LSB BIT 1 = Timer Operation mode bit 1
1526 * LSB BIT 2 = Timer Operation mode bit 2
1527 * LSB BIT 3 = Timer Operation mode bit 3
1528 * LSB BIT 4 = Init Config Mode bit 0
1529 * LSB BIT 5 = Init Config Mode bit 1
1530 * LSB BIT 6 = Init Config Mode bit 2
1531 * LSB BIT 7 = Enable Non part on LIHA failure
1532 *
1533 * MSB BIT 0 = Enable class 2
1534 * MSB BIT 1 = Enable ACK0
1535 * MSB BIT 2 =
1536 * MSB BIT 3 =
1537 * MSB BIT 4 = FC Tape Enable
1538 * MSB BIT 5 = Enable FC Confirm
1539 * MSB BIT 6 = Enable command queuing in target mode
1540 * MSB BIT 7 = No Logo On Link Down
1541 */
1542 uint8_t add_firmware_options[2];
1543
1544 uint8_t response_accumulation_timer;
1545 uint8_t interrupt_delay_timer;
1546
1547 /*
1548 * LSB BIT 0 = Enable Read xfr_rdy
1549 * LSB BIT 1 = Soft ID only
1550 * LSB BIT 2 =
1551 * LSB BIT 3 =
1552 * LSB BIT 4 = FCP RSP Payload [0]
1553 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1554 * LSB BIT 6 = Enable Out-of-Order frame handling
1555 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1556 *
1557 * MSB BIT 0 = Sbus enable - 2300
1558 * MSB BIT 1 =
1559 * MSB BIT 2 =
1560 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -07001561 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 * MSB BIT 5 = enable 50 ohm termination
1563 * MSB BIT 6 = Data Rate (2300 only)
1564 * MSB BIT 7 = Data Rate (2300 only)
1565 */
1566 uint8_t special_options[2];
1567
1568 uint8_t reserved_3[26];
1569} init_cb_t;
1570
Shyam Sundar9f2475f2020-06-30 03:22:29 -07001571/* Special Features Control Block */
1572struct init_sf_cb {
1573 uint8_t format;
1574 uint8_t reserved0;
1575 /*
1576 * BIT 15-14 = Reserved
1577 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
1578 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
1579 * BIT 11-0 = Reserved
1580 */
Bart Van Assche37ce4f32021-03-20 16:23:55 -07001581 __le16 flags;
Shyam Sundar9f2475f2020-06-30 03:22:29 -07001582 uint8_t reserved1[32];
1583 uint16_t discard_OHRB_timeout_value;
1584 uint16_t remote_write_opt_queue_num;
1585 uint8_t reserved2[40];
1586 uint8_t scm_related_parameter[16];
1587 uint8_t reserved3[32];
1588};
1589
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590/*
1591 * Get Link Status mailbox command return buffer.
1592 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001593#define GLSO_SEND_RPS BIT_0
1594#define GLSO_USE_DID BIT_3
1595
Andrew Vasquez43ef0582008-01-17 09:02:08 -08001596struct link_statistics {
Joe Carnuccio974c0862020-02-12 13:44:16 -08001597 __le32 link_fail_cnt;
1598 __le32 loss_sync_cnt;
1599 __le32 loss_sig_cnt;
1600 __le32 prim_seq_err_cnt;
1601 __le32 inval_xmit_word_cnt;
1602 __le32 inval_crc_cnt;
1603 __le32 lip_cnt;
1604 __le32 link_up_cnt;
1605 __le32 link_down_loop_init_tmo;
1606 __le32 link_down_los;
1607 __le32 link_down_loss_rcv_clk;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001608 uint32_t reserved0[5];
Joe Carnuccio974c0862020-02-12 13:44:16 -08001609 __le32 port_cfg_chg;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001610 uint32_t reserved1[11];
Joe Carnuccio974c0862020-02-12 13:44:16 -08001611 __le32 rsp_q_full;
1612 __le32 atio_q_full;
1613 __le32 drop_ae;
1614 __le32 els_proto_err;
1615 __le32 reserved2;
1616 __le32 tx_frames;
1617 __le32 rx_frames;
1618 __le32 discarded_frames;
1619 __le32 dropped_frames;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001620 uint32_t reserved3;
Joe Carnuccio974c0862020-02-12 13:44:16 -08001621 __le32 nos_rcvd;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001622 uint32_t reserved4[4];
Joe Carnuccio974c0862020-02-12 13:44:16 -08001623 __le32 tx_prjt;
1624 __le32 rcv_exfail;
1625 __le32 rcv_abts;
1626 __le32 seq_frm_miss;
1627 __le32 corr_err;
1628 __le32 mb_rqst;
1629 __le32 nport_full;
1630 __le32 eofa;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001631 uint32_t reserved5;
Joe Carnuccio974c0862020-02-12 13:44:16 -08001632 __le64 fpm_recv_word_cnt;
1633 __le64 fpm_disc_word_cnt;
1634 __le64 fpm_xmit_word_cnt;
Harish Zunjarrao243de672016-01-27 12:03:33 -05001635 uint32_t reserved6[70];
Andrew Vasquez43ef0582008-01-17 09:02:08 -08001636};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637
1638/*
1639 * NVRAM Command values.
1640 */
1641#define NV_START_BIT BIT_2
1642#define NV_WRITE_OP (BIT_26+BIT_24)
1643#define NV_READ_OP (BIT_26+BIT_25)
1644#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1645#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1646#define NV_DELAY_COUNT 10
1647
1648/*
1649 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1650 */
1651typedef struct {
1652 /*
1653 * NVRAM header
1654 */
1655 uint8_t id[4];
1656 uint8_t nvram_version;
1657 uint8_t reserved_0;
1658
1659 /*
1660 * NVRAM RISC parameter block
1661 */
1662 uint8_t parameter_block_version;
1663 uint8_t reserved_1;
1664
1665 /*
1666 * LSB BIT 0 = Enable Hard Loop Id
1667 * LSB BIT 1 = Enable Fairness
1668 * LSB BIT 2 = Enable Full-Duplex
1669 * LSB BIT 3 = Enable Fast Posting
1670 * LSB BIT 4 = Enable Target Mode
1671 * LSB BIT 5 = Disable Initiator Mode
1672 * LSB BIT 6 = Enable ADISC
1673 * LSB BIT 7 = Enable Target Inquiry Data
1674 *
1675 * MSB BIT 0 = Enable PDBC Notify
1676 * MSB BIT 1 = Non Participating LIP
1677 * MSB BIT 2 = Descending Loop ID Search
1678 * MSB BIT 3 = Acquire Loop ID in LIPA
1679 * MSB BIT 4 = Stop PortQ on Full Status
1680 * MSB BIT 5 = Full Login after LIP
1681 * MSB BIT 6 = Node Name Option
1682 * MSB BIT 7 = Ext IFWCB enable bit
1683 */
1684 uint8_t firmware_options[2];
1685
René Rebe2a87d482020-08-27 22:27:29 +02001686 __le16 frame_payload_size;
Bart Van Assche21038b02020-05-18 14:17:11 -07001687 __le16 max_iocb_allocation;
1688 __le16 execution_throttle;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 uint8_t retry_count;
1690 uint8_t retry_delay; /* unused */
1691 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1692 uint16_t hard_address;
1693 uint8_t inquiry_data;
1694 uint8_t login_timeout;
1695 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1696
1697 /*
1698 * LSB BIT 0 = Timer Operation mode bit 0
1699 * LSB BIT 1 = Timer Operation mode bit 1
1700 * LSB BIT 2 = Timer Operation mode bit 2
1701 * LSB BIT 3 = Timer Operation mode bit 3
1702 * LSB BIT 4 = Init Config Mode bit 0
1703 * LSB BIT 5 = Init Config Mode bit 1
1704 * LSB BIT 6 = Init Config Mode bit 2
1705 * LSB BIT 7 = Enable Non part on LIHA failure
1706 *
1707 * MSB BIT 0 = Enable class 2
1708 * MSB BIT 1 = Enable ACK0
1709 * MSB BIT 2 =
1710 * MSB BIT 3 =
1711 * MSB BIT 4 = FC Tape Enable
1712 * MSB BIT 5 = Enable FC Confirm
1713 * MSB BIT 6 = Enable command queuing in target mode
1714 * MSB BIT 7 = No Logo On Link Down
1715 */
1716 uint8_t add_firmware_options[2];
1717
1718 uint8_t response_accumulation_timer;
1719 uint8_t interrupt_delay_timer;
1720
1721 /*
1722 * LSB BIT 0 = Enable Read xfr_rdy
1723 * LSB BIT 1 = Soft ID only
1724 * LSB BIT 2 =
1725 * LSB BIT 3 =
1726 * LSB BIT 4 = FCP RSP Payload [0]
1727 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1728 * LSB BIT 6 = Enable Out-of-Order frame handling
1729 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1730 *
1731 * MSB BIT 0 = Sbus enable - 2300
1732 * MSB BIT 1 =
1733 * MSB BIT 2 =
1734 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -07001735 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -07001736 * MSB BIT 5 = enable 50 ohm termination
1737 * MSB BIT 6 = Data Rate (2300 only)
1738 * MSB BIT 7 = Data Rate (2300 only)
1739 */
1740 uint8_t special_options[2];
1741
1742 /* Reserved for expanded RISC parameter block */
1743 uint8_t reserved_2[22];
1744
1745 /*
1746 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1747 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1748 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1749 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1750 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1751 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1752 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1753 * LSB BIT 7 = Rx Sensitivity 1G bit 3
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001754 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1756 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1757 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1758 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1759 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1760 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1761 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1762 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1763 *
1764 * LSB BIT 0 = Output Swing 1G bit 0
1765 * LSB BIT 1 = Output Swing 1G bit 1
1766 * LSB BIT 2 = Output Swing 1G bit 2
1767 * LSB BIT 3 = Output Emphasis 1G bit 0
1768 * LSB BIT 4 = Output Emphasis 1G bit 1
1769 * LSB BIT 5 = Output Swing 2G bit 0
1770 * LSB BIT 6 = Output Swing 2G bit 1
1771 * LSB BIT 7 = Output Swing 2G bit 2
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001772 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773 * MSB BIT 0 = Output Emphasis 2G bit 0
1774 * MSB BIT 1 = Output Emphasis 2G bit 1
1775 * MSB BIT 2 = Output Enable
1776 * MSB BIT 3 =
1777 * MSB BIT 4 =
1778 * MSB BIT 5 =
1779 * MSB BIT 6 =
1780 * MSB BIT 7 =
1781 */
1782 uint8_t seriallink_options[4];
1783
1784 /*
1785 * NVRAM host parameter block
1786 *
1787 * LSB BIT 0 = Enable spinup delay
1788 * LSB BIT 1 = Disable BIOS
1789 * LSB BIT 2 = Enable Memory Map BIOS
1790 * LSB BIT 3 = Enable Selectable Boot
1791 * LSB BIT 4 = Disable RISC code load
1792 * LSB BIT 5 = Set cache line size 1
1793 * LSB BIT 6 = PCI Parity Disable
1794 * LSB BIT 7 = Enable extended logging
1795 *
1796 * MSB BIT 0 = Enable 64bit addressing
1797 * MSB BIT 1 = Enable lip reset
1798 * MSB BIT 2 = Enable lip full login
1799 * MSB BIT 3 = Enable target reset
1800 * MSB BIT 4 = Enable database storage
1801 * MSB BIT 5 = Enable cache flush read
1802 * MSB BIT 6 = Enable database load
1803 * MSB BIT 7 = Enable alternate WWN
1804 */
1805 uint8_t host_p[2];
1806
1807 uint8_t boot_node_name[WWN_SIZE];
1808 uint8_t boot_lun_number;
1809 uint8_t reset_delay;
1810 uint8_t port_down_retry_count;
1811 uint8_t boot_id_number;
Bart Van Assche21038b02020-05-18 14:17:11 -07001812 __le16 max_luns_per_target;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001813 uint8_t fcode_boot_port_name[WWN_SIZE];
1814 uint8_t alternate_port_name[WWN_SIZE];
1815 uint8_t alternate_node_name[WWN_SIZE];
1816
1817 /*
1818 * BIT 0 = Selective Login
1819 * BIT 1 = Alt-Boot Enable
1820 * BIT 2 =
1821 * BIT 3 = Boot Order List
1822 * BIT 4 =
1823 * BIT 5 = Selective LUN
1824 * BIT 6 =
1825 * BIT 7 = unused
1826 */
1827 uint8_t efi_parameters;
1828
1829 uint8_t link_down_timeout;
1830
Andrew Vasquezcca53352005-08-26 19:08:30 -07001831 uint8_t adapter_id[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832
1833 uint8_t alt1_boot_node_name[WWN_SIZE];
1834 uint16_t alt1_boot_lun_number;
1835 uint8_t alt2_boot_node_name[WWN_SIZE];
1836 uint16_t alt2_boot_lun_number;
1837 uint8_t alt3_boot_node_name[WWN_SIZE];
1838 uint16_t alt3_boot_lun_number;
1839 uint8_t alt4_boot_node_name[WWN_SIZE];
1840 uint16_t alt4_boot_lun_number;
1841 uint8_t alt5_boot_node_name[WWN_SIZE];
1842 uint16_t alt5_boot_lun_number;
1843 uint8_t alt6_boot_node_name[WWN_SIZE];
1844 uint16_t alt6_boot_lun_number;
1845 uint8_t alt7_boot_node_name[WWN_SIZE];
1846 uint16_t alt7_boot_lun_number;
1847
1848 uint8_t reserved_3[2];
1849
1850 /* Offset 200-215 : Model Number */
1851 uint8_t model_number[16];
1852
1853 /* OEM related items */
1854 uint8_t oem_specific[16];
1855
1856 /*
1857 * NVRAM Adapter Features offset 232-239
1858 *
1859 * LSB BIT 0 = External GBIC
1860 * LSB BIT 1 = Risc RAM parity
1861 * LSB BIT 2 = Buffer Plus Module
1862 * LSB BIT 3 = Multi Chip Adapter
1863 * LSB BIT 4 = Internal connector
1864 * LSB BIT 5 =
1865 * LSB BIT 6 =
1866 * LSB BIT 7 =
1867 *
1868 * MSB BIT 0 =
1869 * MSB BIT 1 =
1870 * MSB BIT 2 =
1871 * MSB BIT 3 =
1872 * MSB BIT 4 =
1873 * MSB BIT 5 =
1874 * MSB BIT 6 =
1875 * MSB BIT 7 =
1876 */
1877 uint8_t adapter_features[2];
1878
1879 uint8_t reserved_4[16];
1880
1881 /* Subsystem vendor ID for ISP2200 */
1882 uint16_t subsystem_vendor_id_2200;
1883
1884 /* Subsystem device ID for ISP2200 */
1885 uint16_t subsystem_device_id_2200;
1886
1887 uint8_t reserved_5;
1888 uint8_t checksum;
1889} nvram_t;
1890
1891/*
1892 * ISP queue - response queue entry definition.
1893 */
1894typedef struct {
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04001895 uint8_t entry_type; /* Entry type. */
1896 uint8_t entry_count; /* Entry count. */
1897 uint8_t sys_define; /* System defined. */
1898 uint8_t entry_status; /* Entry Status. */
1899 uint32_t handle; /* System defined handle */
1900 uint8_t data[52];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 uint32_t signature;
1902#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1903} response_t;
1904
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04001905/*
1906 * ISP queue - ATIO queue entry definition.
1907 */
1908struct atio {
1909 uint8_t entry_type; /* Entry type. */
1910 uint8_t entry_count; /* Entry count. */
Quinn Tran5f355092016-12-23 18:06:11 -08001911 __le16 attr_n_length;
1912 uint8_t data[56];
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04001913 uint32_t signature;
1914#define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1915};
1916
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917typedef union {
Bart Van Assche21038b02020-05-18 14:17:11 -07001918 __le16 extended;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919 struct {
1920 uint8_t reserved;
1921 uint8_t standard;
1922 } id;
1923} target_id_t;
1924
1925#define SET_TARGET_ID(ha, to, from) \
1926do { \
1927 if (HAS_EXTENDED_IDS(ha)) \
1928 to.extended = cpu_to_le16(from); \
1929 else \
1930 to.id.standard = (uint8_t)from; \
1931} while (0)
1932
1933/*
1934 * ISP queue - command entry structure definition.
1935 */
1936#define COMMAND_TYPE 0x11 /* Command entry */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937typedef struct {
1938 uint8_t entry_type; /* Entry type. */
1939 uint8_t entry_count; /* Entry count. */
1940 uint8_t sys_define; /* System defined. */
1941 uint8_t entry_status; /* Entry Status. */
1942 uint32_t handle; /* System handle. */
1943 target_id_t target; /* SCSI ID */
Bart Van Assche21038b02020-05-18 14:17:11 -07001944 __le16 lun; /* SCSI LUN */
1945 __le16 control_flags; /* Control flags. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946#define CF_WRITE BIT_6
1947#define CF_READ BIT_5
1948#define CF_SIMPLE_TAG BIT_3
1949#define CF_ORDERED_TAG BIT_2
1950#define CF_HEAD_TAG BIT_1
1951 uint16_t reserved_1;
Bart Van Assche21038b02020-05-18 14:17:11 -07001952 __le16 timeout; /* Command timeout. */
1953 __le16 dseg_count; /* Data segment count. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
Bart Van Assche21038b02020-05-18 14:17:11 -07001955 __le32 byte_count; /* Total byte count. */
Bart Van Assche15b7a682019-04-17 14:44:38 -07001956 union {
1957 struct dsd32 dsd32[3];
1958 struct dsd64 dsd64[2];
1959 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960} cmd_entry_t;
1961
1962/*
1963 * ISP queue - 64-Bit addressing, command entry structure definition.
1964 */
1965#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1966typedef struct {
1967 uint8_t entry_type; /* Entry type. */
1968 uint8_t entry_count; /* Entry count. */
1969 uint8_t sys_define; /* System defined. */
1970 uint8_t entry_status; /* Entry Status. */
1971 uint32_t handle; /* System handle. */
1972 target_id_t target; /* SCSI ID */
Bart Van Assche21038b02020-05-18 14:17:11 -07001973 __le16 lun; /* SCSI LUN */
1974 __le16 control_flags; /* Control flags. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975 uint16_t reserved_1;
Bart Van Assche21038b02020-05-18 14:17:11 -07001976 __le16 timeout; /* Command timeout. */
1977 __le16 dseg_count; /* Data segment count. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001978 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1979 uint32_t byte_count; /* Total byte count. */
Bart Van Assche15b7a682019-04-17 14:44:38 -07001980 struct dsd64 dsd[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981} cmd_a64_entry_t, request_t;
1982
1983/*
1984 * ISP queue - continuation entry structure definition.
1985 */
1986#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1987typedef struct {
1988 uint8_t entry_type; /* Entry type. */
1989 uint8_t entry_count; /* Entry count. */
1990 uint8_t sys_define; /* System defined. */
1991 uint8_t entry_status; /* Entry Status. */
1992 uint32_t reserved;
Bart Van Assche15b7a682019-04-17 14:44:38 -07001993 struct dsd32 dsd[7];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001994} cont_entry_t;
1995
1996/*
1997 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1998 */
1999#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
2000typedef struct {
2001 uint8_t entry_type; /* Entry type. */
2002 uint8_t entry_count; /* Entry count. */
2003 uint8_t sys_define; /* System defined. */
2004 uint8_t entry_status; /* Entry Status. */
Bart Van Assche15b7a682019-04-17 14:44:38 -07002005 struct dsd64 dsd[5];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002006} cont_a64_entry_t;
2007
Arun Easibad75002010-05-04 15:01:30 -07002008#define PO_MODE_DIF_INSERT 0
Arun Easi9e522cd2012-08-22 14:21:31 -04002009#define PO_MODE_DIF_REMOVE 1
2010#define PO_MODE_DIF_PASS 2
2011#define PO_MODE_DIF_REPLACE 3
2012#define PO_MODE_DIF_TCP_CKSUM 6
Arun Easibad75002010-05-04 15:01:30 -07002013#define PO_ENABLE_INCR_GUARD_SEED BIT_3
Arun Easibad75002010-05-04 15:01:30 -07002014#define PO_DISABLE_GUARD_CHECK BIT_4
Quinn Tranf83adb62014-04-11 16:54:43 -04002015#define PO_DISABLE_INCR_REF_TAG BIT_5
2016#define PO_DIS_HEADER_MODE BIT_7
2017#define PO_ENABLE_DIF_BUNDLING BIT_8
2018#define PO_DIS_FRAME_MODE BIT_9
2019#define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
2020#define PO_DIS_VALD_APP_REF_ESC BIT_11
2021
2022#define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
2023#define PO_DIS_REF_TAG_REPL BIT_13
2024#define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
2025#define PO_DIS_REF_TAG_VALD BIT_15
2026
Arun Easibad75002010-05-04 15:01:30 -07002027/*
2028 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
2029 */
2030struct crc_context {
2031 uint32_t handle; /* System handle. */
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04002032 __le32 ref_tag;
2033 __le16 app_tag;
Arun Easibad75002010-05-04 15:01:30 -07002034 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
2035 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04002036 __le16 guard_seed; /* Initial Guard Seed */
2037 __le16 prot_opts; /* Requested Data Protection Mode */
2038 __le16 blk_size; /* Data size in bytes */
Bart Van Assche21038b02020-05-18 14:17:11 -07002039 __le16 runt_blk_guard; /* Guard value for runt block (tape
Arun Easibad75002010-05-04 15:01:30 -07002040 * only) */
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04002041 __le32 byte_count; /* Total byte count/ total data
Arun Easibad75002010-05-04 15:01:30 -07002042 * transfer count */
2043 union {
2044 struct {
2045 uint32_t reserved_1;
2046 uint16_t reserved_2;
2047 uint16_t reserved_3;
2048 uint32_t reserved_4;
Bart Van Assche9e75b5e2019-08-08 20:01:33 -07002049 struct dsd64 data_dsd[1];
Arun Easibad75002010-05-04 15:01:30 -07002050 uint32_t reserved_5[2];
2051 uint32_t reserved_6;
2052 } nobundling;
2053 struct {
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04002054 __le32 dif_byte_count; /* Total DIF byte
Arun Easibad75002010-05-04 15:01:30 -07002055 * count */
2056 uint16_t reserved_1;
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04002057 __le16 dseg_count; /* Data segment count */
Arun Easibad75002010-05-04 15:01:30 -07002058 uint32_t reserved_2;
Bart Van Assche9e75b5e2019-08-08 20:01:33 -07002059 struct dsd64 data_dsd[1];
Bart Van Assche15b7a682019-04-17 14:44:38 -07002060 struct dsd64 dif_dsd;
Arun Easibad75002010-05-04 15:01:30 -07002061 } bundling;
2062 } u;
2063
2064 struct fcp_cmnd fcp_cmnd;
2065 dma_addr_t crc_ctx_dma;
2066 /* List of DMA context transfers */
2067 struct list_head dsd_list;
2068
Giridhar Malavali50b81272018-12-21 09:33:45 -08002069 /* List of DIF Bundling context DMA address */
2070 struct list_head ldif_dsd_list;
2071 u8 no_ldif_dsd;
2072
2073 struct list_head ldif_dma_hndl_list;
2074 u32 dif_bundl_len;
2075 u8 no_dif_bundl;
Arun Easibad75002010-05-04 15:01:30 -07002076 /* This structure should not exceed 512 bytes */
2077};
2078
2079#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2080#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2081
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082/*
2083 * ISP queue - status entry structure definition.
2084 */
2085#define STATUS_TYPE 0x03 /* Status entry. */
2086typedef struct {
2087 uint8_t entry_type; /* Entry type. */
2088 uint8_t entry_count; /* Entry count. */
2089 uint8_t sys_define; /* System defined. */
2090 uint8_t entry_status; /* Entry Status. */
2091 uint32_t handle; /* System handle. */
Bart Van Assche21038b02020-05-18 14:17:11 -07002092 __le16 scsi_status; /* SCSI status. */
2093 __le16 comp_status; /* Completion status. */
2094 __le16 state_flags; /* State flags. */
2095 __le16 status_flags; /* Status flags. */
2096 __le16 rsp_info_len; /* Response Info Length. */
2097 __le16 req_sense_length; /* Request sense data length. */
2098 __le32 residual_length; /* Residual transfer length. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099 uint8_t rsp_info[8]; /* FCP response information. */
2100 uint8_t req_sense_data[32]; /* Request sense data. */
2101} sts_entry_t;
2102
2103/*
2104 * Status entry entry status
2105 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002106#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002107#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2108#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
2109#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
2110#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
2111#define RF_BUSY BIT_1 /* Busy */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002112#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2113 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2114#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2115 RF_INV_E_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116
2117/*
2118 * Status entry SCSI status bit definitions.
2119 */
2120#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
2121#define SS_RESIDUAL_UNDER BIT_11
2122#define SS_RESIDUAL_OVER BIT_10
2123#define SS_SENSE_LEN_VALID BIT_9
2124#define SS_RESPONSE_INFO_LEN_VALID BIT_8
Quinn Trandf2e32c2017-01-19 22:27:53 -08002125#define SS_SCSI_STATUS_BYTE 0xff
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126
2127#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2128#define SS_BUSY_CONDITION BIT_3
2129#define SS_CONDITION_MET BIT_2
2130#define SS_CHECK_CONDITION BIT_1
2131
2132/*
2133 * Status entry completion status
2134 */
2135#define CS_COMPLETE 0x0 /* No errors */
2136#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2137#define CS_DMA 0x2 /* A DMA direction error. */
2138#define CS_TRANSPORT 0x3 /* Transport error. */
2139#define CS_RESET 0x4 /* SCSI bus reset occurred */
2140#define CS_ABORTED 0x5 /* System aborted command. */
2141#define CS_TIMEOUT 0x6 /* Timeout error. */
2142#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
Arun Easibad75002010-05-04 15:01:30 -07002143#define CS_DIF_ERROR 0xC /* DIF error detected */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002144
2145#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2146#define CS_QUEUE_FULL 0x1C /* Queue Full. */
2147#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2148 /* (selection timeout) */
2149#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2150#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2151#define CS_PORT_BUSY 0x2B /* Port Busy */
2152#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
Chad Dupuisf934c9d2014-04-11 16:54:31 -04002153#define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2154 failure */
Bikash Hazarikaa0465852021-01-11 01:31:31 -08002155#define CS_REJECT_RECEIVED 0x4E /* Reject received */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2157#define CS_UNKNOWN 0x81 /* Driver defined */
2158#define CS_RETRY 0x82 /* Driver defined */
2159#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2160
Saurav Kashyapa9b6f722012-08-22 14:21:01 -04002161#define CS_BIDIR_RD_OVERRUN 0x700
2162#define CS_BIDIR_RD_WR_OVERRUN 0x707
2163#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2164#define CS_BIDIR_RD_UNDERRUN 0x1500
2165#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2166#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2167#define CS_BIDIR_DMA 0x200
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168/*
2169 * Status entry status flags
2170 */
2171#define SF_ABTS_TERMINATED BIT_10
2172#define SF_LOGOUT_SENT BIT_13
2173
2174/*
2175 * ISP queue - status continuation entry structure definition.
2176 */
2177#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2178typedef struct {
2179 uint8_t entry_type; /* Entry type. */
2180 uint8_t entry_count; /* Entry count. */
2181 uint8_t sys_define; /* System defined. */
2182 uint8_t entry_status; /* Entry Status. */
2183 uint8_t data[60]; /* data */
2184} sts_cont_entry_t;
2185
2186/*
2187 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2188 * structure definition.
2189 */
2190#define STATUS_TYPE_21 0x21 /* Status entry. */
2191typedef struct {
2192 uint8_t entry_type; /* Entry type. */
2193 uint8_t entry_count; /* Entry count. */
2194 uint8_t handle_count; /* Handle count. */
2195 uint8_t entry_status; /* Entry Status. */
2196 uint32_t handle[15]; /* System handles. */
2197} sts21_entry_t;
2198
2199/*
2200 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2201 * structure definition.
2202 */
2203#define STATUS_TYPE_22 0x22 /* Status entry. */
2204typedef struct {
2205 uint8_t entry_type; /* Entry type. */
2206 uint8_t entry_count; /* Entry count. */
2207 uint8_t handle_count; /* Handle count. */
2208 uint8_t entry_status; /* Entry Status. */
2209 uint16_t handle[30]; /* System handles. */
2210} sts22_entry_t;
2211
2212/*
2213 * ISP queue - marker entry structure definition.
2214 */
2215#define MARKER_TYPE 0x04 /* Marker entry. */
2216typedef struct {
2217 uint8_t entry_type; /* Entry type. */
2218 uint8_t entry_count; /* Entry count. */
2219 uint8_t handle_count; /* Handle count. */
2220 uint8_t entry_status; /* Entry Status. */
2221 uint32_t sys_define_2; /* System defined. */
2222 target_id_t target; /* SCSI ID */
2223 uint8_t modifier; /* Modifier (7-0). */
2224#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2225#define MK_SYNC_ID 1 /* Synchronize ID */
2226#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2227#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2228 /* clear port changed, */
2229 /* use sequence number. */
2230 uint8_t reserved_1;
Bart Van Assche21038b02020-05-18 14:17:11 -07002231 __le16 sequence_number; /* Sequence number of event */
2232 __le16 lun; /* SCSI LUN */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233 uint8_t reserved_2[48];
2234} mrk_entry_t;
2235
2236/*
2237 * ISP queue - Management Server entry structure definition.
2238 */
2239#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2240typedef struct {
2241 uint8_t entry_type; /* Entry type. */
2242 uint8_t entry_count; /* Entry count. */
2243 uint8_t handle_count; /* Handle count. */
2244 uint8_t entry_status; /* Entry Status. */
2245 uint32_t handle1; /* System handle. */
2246 target_id_t loop_id;
Bart Van Assche21038b02020-05-18 14:17:11 -07002247 __le16 status;
2248 __le16 control_flags; /* Control flags. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002249 uint16_t reserved2;
Bart Van Assche21038b02020-05-18 14:17:11 -07002250 __le16 timeout;
2251 __le16 cmd_dsd_count;
2252 __le16 total_dsd_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002253 uint8_t type;
2254 uint8_t r_ctl;
Bart Van Assche21038b02020-05-18 14:17:11 -07002255 __le16 rx_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002256 uint16_t reserved3;
2257 uint32_t handle2;
Bart Van Assche21038b02020-05-18 14:17:11 -07002258 __le32 rsp_bytecount;
2259 __le32 req_bytecount;
Bart Van Assche15b7a682019-04-17 14:44:38 -07002260 struct dsd64 req_dsd;
2261 struct dsd64 rsp_dsd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002262} ms_iocb_entry_t;
2263
Shyam Sundar9f2475f2020-06-30 03:22:29 -07002264#define SCM_EDC_ACC_RECEIVED BIT_6
2265#define SCM_RDF_ACC_RECEIVED BIT_7
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266
2267/*
2268 * ISP queue - Mailbox Command entry structure definition.
2269 */
2270#define MBX_IOCB_TYPE 0x39
2271struct mbx_entry {
2272 uint8_t entry_type;
2273 uint8_t entry_count;
2274 uint8_t sys_define1;
2275 /* Use sys_define1 for source type */
2276#define SOURCE_SCSI 0x00
2277#define SOURCE_IP 0x01
2278#define SOURCE_VI 0x02
2279#define SOURCE_SCTP 0x03
2280#define SOURCE_MP 0x04
2281#define SOURCE_MPIOCTL 0x05
2282#define SOURCE_ASYNC_IOCB 0x07
2283
2284 uint8_t entry_status;
2285
2286 uint32_t handle;
2287 target_id_t loop_id;
2288
Bart Van Assche21038b02020-05-18 14:17:11 -07002289 __le16 status;
2290 __le16 state_flags;
2291 __le16 status_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292
2293 uint32_t sys_define2[2];
2294
Bart Van Assche21038b02020-05-18 14:17:11 -07002295 __le16 mb0;
2296 __le16 mb1;
2297 __le16 mb2;
2298 __le16 mb3;
2299 __le16 mb6;
2300 __le16 mb7;
2301 __le16 mb9;
2302 __le16 mb10;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002303 uint32_t reserved_2[2];
2304 uint8_t node_name[WWN_SIZE];
2305 uint8_t port_name[WWN_SIZE];
2306};
2307
Quinn Tran5d964832017-01-19 22:27:59 -08002308#ifndef IMMED_NOTIFY_TYPE
2309#define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2310/*
2311 * ISP queue - immediate notify entry structure definition.
2312 * This is sent by the ISP to the Target driver.
2313 * This IOCB would have report of events sent by the
2314 * initiator, that needs to be handled by the target
2315 * driver immediately.
2316 */
2317struct imm_ntfy_from_isp {
2318 uint8_t entry_type; /* Entry type. */
2319 uint8_t entry_count; /* Entry count. */
2320 uint8_t sys_define; /* System defined. */
2321 uint8_t entry_status; /* Entry Status. */
2322 union {
2323 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07002324 __le32 sys_define_2; /* System defined. */
Quinn Tran5d964832017-01-19 22:27:59 -08002325 target_id_t target;
Bart Van Assche21038b02020-05-18 14:17:11 -07002326 __le16 lun;
Quinn Tran5d964832017-01-19 22:27:59 -08002327 uint8_t target_id;
2328 uint8_t reserved_1;
Bart Van Assche21038b02020-05-18 14:17:11 -07002329 __le16 status_modifier;
2330 __le16 status;
2331 __le16 task_flags;
2332 __le16 seq_id;
2333 __le16 srr_rx_id;
2334 __le32 srr_rel_offs;
2335 __le16 srr_ui;
Quinn Tran5d964832017-01-19 22:27:59 -08002336#define SRR_IU_DATA_IN 0x1
2337#define SRR_IU_DATA_OUT 0x5
2338#define SRR_IU_STATUS 0x7
Bart Van Assche21038b02020-05-18 14:17:11 -07002339 __le16 srr_ox_id;
Quinn Tran5d964832017-01-19 22:27:59 -08002340 uint8_t reserved_2[28];
2341 } isp2x;
2342 struct {
2343 uint32_t reserved;
Bart Van Assche21038b02020-05-18 14:17:11 -07002344 __le16 nport_handle;
Quinn Tran5d964832017-01-19 22:27:59 -08002345 uint16_t reserved_2;
Bart Van Assche21038b02020-05-18 14:17:11 -07002346 __le16 flags;
Quinn Tran9efea842021-06-23 22:26:02 -07002347#define NOTIFY24XX_FLAGS_FCSP BIT_5
Quinn Tran5d964832017-01-19 22:27:59 -08002348#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2349#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
Bart Van Assche21038b02020-05-18 14:17:11 -07002350 __le16 srr_rx_id;
2351 __le16 status;
Quinn Tran5d964832017-01-19 22:27:59 -08002352 uint8_t status_subcode;
2353 uint8_t fw_handle;
Bart Van Assche21038b02020-05-18 14:17:11 -07002354 __le32 exchange_address;
2355 __le32 srr_rel_offs;
2356 __le16 srr_ui;
2357 __le16 srr_ox_id;
Quinn Tran5d964832017-01-19 22:27:59 -08002358 union {
2359 struct {
2360 uint8_t node_name[8];
2361 } plogi; /* PLOGI/ADISC/PDISC */
2362 struct {
2363 /* PRLI word 3 bit 0-15 */
Bart Van Assche21038b02020-05-18 14:17:11 -07002364 __le16 wd3_lo;
Quinn Tran5d964832017-01-19 22:27:59 -08002365 uint8_t resv0[6];
2366 } prli;
2367 struct {
2368 uint8_t port_id[3];
2369 uint8_t resv1;
Bart Van Assche21038b02020-05-18 14:17:11 -07002370 __le16 nport_handle;
Quinn Tran5d964832017-01-19 22:27:59 -08002371 uint16_t resv2;
2372 } req_els;
2373 } u;
2374 uint8_t port_name[8];
2375 uint8_t resv3[3];
2376 uint8_t vp_index;
2377 uint32_t reserved_5;
2378 uint8_t port_id[3];
2379 uint8_t reserved_6;
2380 } isp24;
2381 } u;
2382 uint16_t reserved_7;
Bart Van Assche21038b02020-05-18 14:17:11 -07002383 __le16 ox_id;
Quinn Tran5d964832017-01-19 22:27:59 -08002384} __packed;
2385#endif
2386
Linus Torvalds1da177e2005-04-16 15:20:36 -07002387/*
2388 * ISP request and response queue entry sizes
2389 */
2390#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2391#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2392
2393
Linus Torvalds1da177e2005-04-16 15:20:36 -07002394
2395/*
2396 * Switch info gathering structure.
2397 */
2398typedef struct {
2399 port_id_t d_id;
2400 uint8_t node_name[WWN_SIZE];
2401 uint8_t port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002402 uint8_t fabric_port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002403 uint16_t fp_speed;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002404 uint8_t fc4_type;
Michael Hernandez84ed3622019-09-12 11:09:12 -07002405 uint8_t fc4_features;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406} sw_info_t;
2407
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002408/* FCP-4 types */
2409#define FC4_TYPE_FCP_SCSI 0x08
Quinn Tran33b28352018-03-20 23:09:40 -07002410#define FC4_TYPE_NVME 0x28
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002411#define FC4_TYPE_OTHER 0x0
2412#define FC4_TYPE_UNKNOWN 0xff
2413
Quinn Tran726b8542017-01-19 22:28:00 -08002414/* mailbox command 4G & above */
2415struct mbx_24xx_entry {
2416 uint8_t entry_type;
2417 uint8_t entry_count;
2418 uint8_t sys_define1;
2419 uint8_t entry_status;
2420 uint32_t handle;
2421 uint16_t mb[28];
2422};
2423
2424#define IOCB_SIZE 64
2425
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427 * Fibre channel port type.
2428 */
Quinn Tran5d964832017-01-19 22:27:59 -08002429typedef enum {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002430 FCT_UNKNOWN,
Quinn Tran01c97f22021-08-09 21:37:13 -07002431 FCT_BROADCAST = 0x01,
2432 FCT_INITIATOR = 0x02,
2433 FCT_TARGET = 0x04,
Hannes Reineckea6a6d052019-04-10 16:16:19 +02002434 FCT_NVME_INITIATOR = 0x10,
2435 FCT_NVME_TARGET = 0x20,
2436 FCT_NVME_DISCOVERY = 0x40,
2437 FCT_NVME = 0xf0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002438} fc_port_type_t;
2439
Quinn Tran726b8542017-01-19 22:28:00 -08002440enum qla_sess_deletion {
2441 QLA_SESS_DELETION_NONE = 0,
2442 QLA_SESS_DELETION_IN_PROGRESS,
2443 QLA_SESS_DELETED,
2444};
2445
Quinn Tran5d964832017-01-19 22:27:59 -08002446enum qlt_plogi_link_t {
2447 QLT_PLOGI_LINK_SAME_WWN,
2448 QLT_PLOGI_LINK_CONFLICT,
2449 QLT_PLOGI_LINK_MAX
2450};
2451
2452struct qlt_plogi_ack_t {
2453 struct list_head list;
2454 struct imm_ntfy_from_isp iocb;
2455 port_id_t id;
2456 int ref_count;
Quinn Tran726b8542017-01-19 22:28:00 -08002457 void *fcport;
2458};
2459
2460struct ct_sns_desc {
2461 struct ct_sns_pkt *ct_sns;
2462 dma_addr_t ct_sns_dma;
2463};
2464
2465enum discovery_state {
2466 DSC_DELETED,
Quinn Trana4239942017-12-28 12:33:26 -08002467 DSC_GNN_ID,
Quinn Tran726b8542017-01-19 22:28:00 -08002468 DSC_GNL,
2469 DSC_LOGIN_PEND,
2470 DSC_LOGIN_FAILED,
2471 DSC_GPDB,
Quinn Tran726b8542017-01-19 22:28:00 -08002472 DSC_UPD_FCPORT,
2473 DSC_LOGIN_COMPLETE,
Quinn Tranf13515a2017-12-28 12:33:15 -08002474 DSC_ADISC,
Quinn Tran726b8542017-01-19 22:28:00 -08002475 DSC_DELETE_PEND,
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002476 DSC_LOGIN_AUTH_PEND,
Quinn Tran726b8542017-01-19 22:28:00 -08002477};
2478
2479enum login_state { /* FW control Target side */
2480 DSC_LS_LLIOCB_SENT = 2,
2481 DSC_LS_PLOGI_PEND,
2482 DSC_LS_PLOGI_COMP,
2483 DSC_LS_PRLI_PEND,
2484 DSC_LS_PRLI_COMP,
2485 DSC_LS_PORT_UNAVAIL,
2486 DSC_LS_PRLO_PEND = 9,
2487 DSC_LS_LOGO_PEND,
2488};
2489
Quinn Tran41dc5292017-01-19 22:28:03 -08002490enum rscn_addr_format {
2491 RSCN_PORT_ADDR,
2492 RSCN_AREA_ADDR,
2493 RSCN_DOM_ADDR,
2494 RSCN_FAB_ADDR,
2495};
2496
Linus Torvalds1da177e2005-04-16 15:20:36 -07002497/*
2498 * Fibre channel port structure.
2499 */
2500typedef struct fc_port {
2501 struct list_head list;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002502 struct scsi_qla_host *vha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002503
Quinn Tran5d964832017-01-19 22:27:59 -08002504 unsigned int conf_compl_supported:1;
2505 unsigned int deleted:2;
Quinn Tran1ae634e2017-12-28 12:33:44 -08002506 unsigned int free_pending:1;
Quinn Tran5d964832017-01-19 22:27:59 -08002507 unsigned int local:1;
2508 unsigned int logout_on_delete:1;
Quinn Tran726b8542017-01-19 22:28:00 -08002509 unsigned int logo_ack_needed:1;
Quinn Tran5d964832017-01-19 22:27:59 -08002510 unsigned int keep_nport_handle:1;
2511 unsigned int send_els_logo:1;
Quinn Tran726b8542017-01-19 22:28:00 -08002512 unsigned int login_pause:1;
2513 unsigned int login_succ:1;
Duane Grigsbyc0c462c2017-10-13 09:34:05 -07002514 unsigned int query:1;
Quinn Trana4239942017-12-28 12:33:26 -08002515 unsigned int id_changed:1;
Quinn Trancb873ba2018-08-31 11:24:29 -07002516 unsigned int scan_needed:1;
Quinn Tran7f2a3982019-09-12 11:09:09 -07002517 unsigned int n2n_flag:1;
Quinn Tran86196a82019-11-25 19:56:51 +03002518 unsigned int explicit_logout:1;
Quinn Tran8aaac2d2019-12-17 14:06:11 -08002519 unsigned int prli_pend_timer:1;
Quinn Tranf8844452021-08-16 22:13:12 -07002520 unsigned int do_prli_nvme:1;
2521
Quinn Tran49db4d42020-09-03 21:51:22 -07002522 uint8_t nvme_flag;
2523
2524 uint8_t node_name[WWN_SIZE];
2525 uint8_t port_name[WWN_SIZE];
2526 port_id_t d_id;
2527 uint16_t loop_id;
2528 uint16_t old_loop_id;
Quinn Tran5d964832017-01-19 22:27:59 -08002529
himanshu.madhani@cavium.com5621b0d2017-07-21 09:32:26 -07002530 struct completion nvme_del_done;
Duane Grigsbya5d42f42017-06-21 13:48:41 -07002531 uint32_t nvme_prli_service_param;
Saurav Kashyapcf3c54f2020-09-03 21:51:27 -07002532#define NVME_PRLI_SP_PI_CTRL BIT_9
2533#define NVME_PRLI_SP_SLER BIT_8
Duane Grigsbya5d42f42017-06-21 13:48:41 -07002534#define NVME_PRLI_SP_CONF BIT_7
2535#define NVME_PRLI_SP_INITIATOR BIT_5
2536#define NVME_PRLI_SP_TARGET BIT_4
2537#define NVME_PRLI_SP_DISCOVERY BIT_3
Darren Trapp03aaa892019-02-15 14:37:13 -08002538#define NVME_PRLI_SP_FIRST_BURST BIT_0
Quinn Tran49db4d42020-09-03 21:51:22 -07002539
Darren Trapp03aaa892019-02-15 14:37:13 -08002540 uint32_t nvme_first_burst_size;
Duane Grigsbya5d42f42017-06-21 13:48:41 -07002541#define NVME_FLAG_REGISTERED 4
Darren Trapp9dd96862018-03-20 23:09:32 -07002542#define NVME_FLAG_DELETING 2
Darren Trapp870fe242018-03-20 23:09:35 -07002543#define NVME_FLAG_RESETTING 1
Duane Grigsbya5d42f42017-06-21 13:48:41 -07002544
Quinn Tran726b8542017-01-19 22:28:00 -08002545 struct fc_port *conflict;
Quinn Tran5d964832017-01-19 22:27:59 -08002546 unsigned char logout_completed;
2547 int generation;
2548
2549 struct se_session *se_sess;
Mike Christie605e7402020-11-01 12:59:31 -06002550 struct list_head sess_cmd_list;
2551 spinlock_t sess_cmd_lock;
Quinn Tran5d964832017-01-19 22:27:59 -08002552 struct kref sess_kref;
2553 struct qla_tgt *tgt;
2554 unsigned long expires;
2555 struct list_head del_list_entry;
2556 struct work_struct free_work;
Quinn Trancd4ed6b2018-08-31 11:24:31 -07002557 struct work_struct reg_work;
2558 uint64_t jiffies_at_registration;
Quinn Tran8aaac2d2019-12-17 14:06:11 -08002559 unsigned long prli_expired;
Quinn Tran5d964832017-01-19 22:27:59 -08002560 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2561
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002562 uint16_t tgt_id;
2563 uint16_t old_tgt_id;
Quinn Trancd4ed6b2018-08-31 11:24:31 -07002564 uint16_t sec_since_registration;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002565
Sarang Radke09ff7012010-03-19 17:03:59 -07002566 uint8_t fcp_prio;
2567
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002568 uint8_t fabric_port_name[WWN_SIZE];
2569 uint16_t fp_speed;
2570
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571 fc_port_type_t port_type;
2572
2573 atomic_t state;
2574 uint32_t flags;
2575
Linus Torvalds1da177e2005-04-16 15:20:36 -07002576 int login_retry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08002578 struct fc_rport *rport, *drport;
Andrew Vasquezad3e0ed2005-08-26 19:08:10 -07002579 u32 supported_classes;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07002580
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002581 uint8_t fc4_type;
Michael Hernandez84ed3622019-09-12 11:09:12 -07002582 uint8_t fc4_features;
Arun Easib3b02e62012-02-09 11:15:39 -08002583 uint8_t scan_state;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002584
2585 unsigned long last_queue_full;
2586 unsigned long last_ramp_up;
2587
2588 uint16_t port_id;
Chad Dupuise05fe292014-09-25 05:16:59 -04002589
Duane Grigsbya5d42f42017-06-21 13:48:41 -07002590 struct nvme_fc_remote_port *nvme_remote_port;
2591
Chad Dupuise05fe292014-09-25 05:16:59 -04002592 unsigned long retry_delay_timestamp;
Alexei Potashnika6ca8872015-07-14 16:00:44 -04002593 struct qla_tgt_sess *tgt_session;
Quinn Tran726b8542017-01-19 22:28:00 -08002594 struct ct_sns_desc ct_desc;
2595 enum discovery_state disc_state;
Shyam Sundar27258a52019-12-17 14:06:06 -08002596 atomic_t shadow_disc_state;
Quinn Trancd4ed6b2018-08-31 11:24:31 -07002597 enum discovery_state next_disc_state;
Quinn Tran726b8542017-01-19 22:28:00 -08002598 enum login_state fw_login_state;
Quinn Tran8777e432018-08-02 13:16:57 -07002599 unsigned long dm_login_expire;
Quinn Tran5b334692017-03-15 09:48:48 -07002600 unsigned long plogi_nack_done_deadline;
2601
Quinn Tran726b8542017-01-19 22:28:00 -08002602 u32 login_gen, last_login_gen;
2603 u32 rscn_gen, last_rscn_gen;
2604 u32 chip_reset;
2605 struct list_head gnl_entry;
2606 struct work_struct del_work;
2607 u8 iocb[IOCB_SIZE];
Duane Grigsbyc0c462c2017-10-13 09:34:05 -07002608 u8 current_login_state;
2609 u8 last_login_state;
Quinn Tran8777e432018-08-02 13:16:57 -07002610 u16 n2n_link_reset_cnt;
2611 u16 n2n_chip_reset;
Arun Easi1e98fb02020-09-03 21:51:17 -07002612
2613 struct dentry *dfs_rport_dir;
Saurav Kashyapdbf1f532021-01-11 01:31:28 -08002614
2615 u64 tgt_short_link_down_cnt;
2616 u64 tgt_link_down_time;
2617 u64 dev_loss_tmo;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002618 /*
2619 * EDIF parameters for encryption.
2620 */
2621 struct {
2622 uint32_t enable:1; /* device is edif enabled/req'd */
2623 uint32_t app_stop:2;
2624 uint32_t app_started:1;
Quinn Trandd307062021-06-23 22:26:00 -07002625 uint32_t aes_gmac:1;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002626 uint32_t app_sess_online:1;
Quinn Trandd307062021-06-23 22:26:00 -07002627 uint32_t tx_sa_set:1;
2628 uint32_t rx_sa_set:1;
2629 uint32_t tx_sa_pending:1;
2630 uint32_t rx_sa_pending:1;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002631 uint32_t tx_rekey_cnt;
2632 uint32_t rx_rekey_cnt;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002633 uint64_t tx_bytes;
2634 uint64_t rx_bytes;
Quinn Tran7878f222021-06-23 22:25:57 -07002635 uint8_t auth_state;
Quinn Tran4de067e2021-08-16 22:13:08 -07002636 uint16_t authok:1;
Quinn Tran7878f222021-06-23 22:25:57 -07002637 uint16_t rekey_cnt;
Quinn Trandd307062021-06-23 22:26:00 -07002638 struct list_head edif_indx_list;
2639 spinlock_t indx_list_lock;
2640
2641 struct list_head tx_sa_list;
2642 struct list_head rx_sa_list;
2643 spinlock_t sa_list_lock;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002644 } edif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002645} fc_port_t;
2646
Martin Wilcka10c8802019-11-07 22:48:57 +00002647enum {
2648 FC4_PRIORITY_NVME = 1,
2649 FC4_PRIORITY_FCP = 2,
2650};
Michael Hernandez84ed3622019-09-12 11:09:12 -07002651
Quinn Tran726b8542017-01-19 22:28:00 -08002652#define QLA_FCPORT_SCAN 1
2653#define QLA_FCPORT_FOUND 2
2654
2655struct event_arg {
Quinn Tran726b8542017-01-19 22:28:00 -08002656 fc_port_t *fcport;
2657 srb_t *sp;
2658 port_id_t id;
2659 u16 data[2], rc;
2660 u8 port_name[WWN_SIZE];
2661 u32 iop[2];
2662};
2663
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002664#include "qla_mr.h"
2665
Linus Torvalds1da177e2005-04-16 15:20:36 -07002666/*
2667 * Fibre channel port/lun states.
2668 */
2669#define FCS_UNCONFIGURED 1
2670#define FCS_DEVICE_DEAD 2
2671#define FCS_DEVICE_LOST 3
2672#define FCS_ONLINE 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07002673
Bart Van Asschec4dc7cd2019-04-11 14:53:20 -07002674extern const char *const port_state_str[5];
Chad Dupuisec426e12011-03-30 11:46:32 -07002675
Shyam Sundar27258a52019-12-17 14:06:06 -08002676static const char * const port_dstate_str[] = {
2677 "DELETED",
2678 "GNN_ID",
2679 "GNL",
2680 "LOGIN_PEND",
2681 "LOGIN_FAILED",
2682 "GPDB",
2683 "UPD_FCPORT",
2684 "LOGIN_COMPLETE",
2685 "ADISC",
Quinn Tran9efea842021-06-23 22:26:02 -07002686 "DELETE_PEND",
2687 "LOGIN_AUTH_PEND",
Shyam Sundar27258a52019-12-17 14:06:06 -08002688};
2689
Linus Torvalds1da177e2005-04-16 15:20:36 -07002690/*
2691 * FC port flags.
2692 */
2693#define FCF_FABRIC_DEVICE BIT_0
2694#define FCF_LOGIN_NEEDED BIT_1
Andrew Vasquezf08b7252010-01-12 12:59:48 -08002695#define FCF_FCP2_DEVICE BIT_2
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07002696#define FCF_ASYNC_SENT BIT_3
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002697#define FCF_CONF_COMP_SUPPORTED BIT_4
Quinn Tran6d6749272017-12-28 12:33:41 -08002698#define FCF_ASYNC_ACTIVE BIT_5
Quinn Tran7ebb336e2021-06-23 22:25:56 -07002699#define FCF_FCSP_DEVICE BIT_6
Quinn Trandd307062021-06-23 22:26:00 -07002700#define FCF_EDIF_DELETE BIT_7
Linus Torvalds1da177e2005-04-16 15:20:36 -07002701
2702/* No loop ID flag. */
2703#define FC_NO_LOOP_ID 0x1000
2704
2705/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002706 * FC-CT interface
2707 *
2708 * NOTE: All structures are big-endian in form.
2709 */
2710
2711#define CT_REJECT_RESPONSE 0x8001
2712#define CT_ACCEPT_RESPONSE 0x8002
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002713#define CT_REASON_INVALID_COMMAND_CODE 0x01
2714#define CT_REASON_CANNOT_PERFORM 0x09
2715#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2716#define CT_EXPL_ALREADY_REGISTERED 0x10
2717#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2718#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2719#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2720#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2721#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2722#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2723#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2724#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2725#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2726#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2727#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
Linus Torvalds1da177e2005-04-16 15:20:36 -07002728
2729#define NS_N_PORT_TYPE 0x01
2730#define NS_NL_PORT_TYPE 0x02
2731#define NS_NX_PORT_TYPE 0x7F
2732
2733#define GA_NXT_CMD 0x100
2734#define GA_NXT_REQ_SIZE (16 + 4)
2735#define GA_NXT_RSP_SIZE (16 + 620)
2736
Quinn Trana4239942017-12-28 12:33:26 -08002737#define GPN_FT_CMD 0x172
2738#define GPN_FT_REQ_SIZE (16 + 4)
2739#define GNN_FT_CMD 0x173
2740#define GNN_FT_REQ_SIZE (16 + 4)
2741
Linus Torvalds1da177e2005-04-16 15:20:36 -07002742#define GID_PT_CMD 0x1A1
2743#define GID_PT_REQ_SIZE (16 + 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002744
2745#define GPN_ID_CMD 0x112
2746#define GPN_ID_REQ_SIZE (16 + 4)
2747#define GPN_ID_RSP_SIZE (16 + 8)
2748
2749#define GNN_ID_CMD 0x113
2750#define GNN_ID_REQ_SIZE (16 + 4)
2751#define GNN_ID_RSP_SIZE (16 + 8)
2752
2753#define GFT_ID_CMD 0x117
2754#define GFT_ID_REQ_SIZE (16 + 4)
2755#define GFT_ID_RSP_SIZE (16 + 32)
2756
Quinn Tran726b8542017-01-19 22:28:00 -08002757#define GID_PN_CMD 0x121
2758#define GID_PN_REQ_SIZE (16 + 8)
2759#define GID_PN_RSP_SIZE (16 + 4)
2760
Linus Torvalds1da177e2005-04-16 15:20:36 -07002761#define RFT_ID_CMD 0x217
2762#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2763#define RFT_ID_RSP_SIZE 16
2764
2765#define RFF_ID_CMD 0x21F
2766#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2767#define RFF_ID_RSP_SIZE 16
2768
2769#define RNN_ID_CMD 0x213
2770#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2771#define RNN_ID_RSP_SIZE 16
2772
2773#define RSNN_NN_CMD 0x239
2774#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2775#define RSNN_NN_RSP_SIZE 16
2776
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002777#define GFPN_ID_CMD 0x11C
2778#define GFPN_ID_REQ_SIZE (16 + 4)
2779#define GFPN_ID_RSP_SIZE (16 + 8)
2780
2781#define GPSC_CMD 0x127
2782#define GPSC_REQ_SIZE (16 + 8)
2783#define GPSC_RSP_SIZE (16 + 2 + 2)
2784
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002785#define GFF_ID_CMD 0x011F
2786#define GFF_ID_REQ_SIZE (16 + 4)
2787#define GFF_ID_RSP_SIZE (16 + 128)
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002788
Andrew Vasquezcca53352005-08-26 19:08:30 -07002789/*
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002790 * FDMI HBA attribute types.
Andrew Vasquezcca53352005-08-26 19:08:30 -07002791 */
Arun Easi137316b2021-08-09 21:37:11 -07002792#define FDMI1_HBA_ATTR_COUNT 10
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002793#define FDMI2_HBA_ATTR_COUNT 17
2794
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002795#define FDMI_HBA_NODE_NAME 0x1
2796#define FDMI_HBA_MANUFACTURER 0x2
2797#define FDMI_HBA_SERIAL_NUMBER 0x3
2798#define FDMI_HBA_MODEL 0x4
2799#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2800#define FDMI_HBA_HARDWARE_VERSION 0x6
2801#define FDMI_HBA_DRIVER_VERSION 0x7
2802#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2803#define FDMI_HBA_FIRMWARE_VERSION 0x9
Andrew Vasquezcca53352005-08-26 19:08:30 -07002804#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2805#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002806
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002807#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002808#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002809#define FDMI_HBA_NUM_PORTS 0xe
2810#define FDMI_HBA_FABRIC_NAME 0xf
2811#define FDMI_HBA_BOOT_BIOS_NAME 0x10
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002812#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
Andrew Vasquezcca53352005-08-26 19:08:30 -07002813
2814struct ct_fdmi_hba_attr {
Bart Van Assche21038b02020-05-18 14:17:11 -07002815 __be16 type;
2816 __be16 len;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002817 union {
2818 uint8_t node_name[WWN_SIZE];
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002819 uint8_t manufacturer[64];
2820 uint8_t serial_num[32];
Himanshu Madhanidd83cb22015-04-09 14:59:55 -04002821 uint8_t model[16+1];
Andrew Vasquezcca53352005-08-26 19:08:30 -07002822 uint8_t model_desc[80];
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002823 uint8_t hw_version[32];
Andrew Vasquezcca53352005-08-26 19:08:30 -07002824 uint8_t driver_version[32];
2825 uint8_t orom_version[16];
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002826 uint8_t fw_version[32];
Andrew Vasquezcca53352005-08-26 19:08:30 -07002827 uint8_t os_version[128];
Bart Van Assche21038b02020-05-18 14:17:11 -07002828 __be32 max_ct_len;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002829
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002830 uint8_t sym_name[256];
Bart Van Assche21038b02020-05-18 14:17:11 -07002831 __be32 vendor_specific_info;
2832 __be32 num_ports;
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002833 uint8_t fabric_name[WWN_SIZE];
2834 uint8_t bios_name[32];
Colin Ian King577419f2016-12-29 22:20:38 +00002835 uint8_t vendor_identifier[8];
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002836 } a;
2837};
2838
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002839struct ct_fdmi1_hba_attributes {
Bart Van Assche21038b02020-05-18 14:17:11 -07002840 __be32 count;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002841 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2842};
2843
2844struct ct_fdmi2_hba_attributes {
Bart Van Assche21038b02020-05-18 14:17:11 -07002845 __be32 count;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002846 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002847};
2848
Andrew Vasquezcca53352005-08-26 19:08:30 -07002849/*
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002850 * FDMI Port attribute types.
Andrew Vasquezcca53352005-08-26 19:08:30 -07002851 */
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002852#define FDMI1_PORT_ATTR_COUNT 6
2853#define FDMI2_PORT_ATTR_COUNT 16
2854#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2855
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002856#define FDMI_PORT_FC4_TYPES 0x1
2857#define FDMI_PORT_SUPPORT_SPEED 0x2
2858#define FDMI_PORT_CURRENT_SPEED 0x3
2859#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2860#define FDMI_PORT_OS_DEVICE_NAME 0x5
2861#define FDMI_PORT_HOST_NAME 0x6
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002862
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002863#define FDMI_PORT_NODE_NAME 0x7
2864#define FDMI_PORT_NAME 0x8
2865#define FDMI_PORT_SYM_NAME 0x9
2866#define FDMI_PORT_TYPE 0xa
2867#define FDMI_PORT_SUPP_COS 0xb
2868#define FDMI_PORT_FABRIC_NAME 0xc
2869#define FDMI_PORT_FC4_TYPE 0xd
2870#define FDMI_PORT_STATE 0x101
2871#define FDMI_PORT_COUNT 0x102
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002872#define FDMI_PORT_IDENTIFIER 0x103
2873
2874#define FDMI_SMARTSAN_SERVICE 0xF100
2875#define FDMI_SMARTSAN_GUID 0xF101
2876#define FDMI_SMARTSAN_VERSION 0xF102
2877#define FDMI_SMARTSAN_PROD_NAME 0xF103
2878#define FDMI_SMARTSAN_PORT_INFO 0xF104
2879#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2880#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
Andrew Vasquezcca53352005-08-26 19:08:30 -07002881
Andrew Vasquez58815692007-07-19 15:05:58 -07002882#define FDMI_PORT_SPEED_1GB 0x1
2883#define FDMI_PORT_SPEED_2GB 0x2
2884#define FDMI_PORT_SPEED_10GB 0x4
2885#define FDMI_PORT_SPEED_4GB 0x8
2886#define FDMI_PORT_SPEED_8GB 0x10
2887#define FDMI_PORT_SPEED_16GB 0x20
Chad Dupuisf73cb692014-02-26 04:15:06 -05002888#define FDMI_PORT_SPEED_32GB 0x40
Joe Carnuccioecc89f22019-03-12 11:08:13 -07002889#define FDMI_PORT_SPEED_64GB 0x80
Andrew Vasquez58815692007-07-19 15:05:58 -07002890#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2891
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04002892#define FC_CLASS_2 0x04
2893#define FC_CLASS_3 0x08
2894#define FC_CLASS_2_3 0x0C
2895
Andrew Vasquezcca53352005-08-26 19:08:30 -07002896struct ct_fdmi_port_attr {
Bart Van Assche21038b02020-05-18 14:17:11 -07002897 __be16 type;
2898 __be16 len;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002899 union {
2900 uint8_t fc4_types[32];
Bart Van Assche21038b02020-05-18 14:17:11 -07002901 __be32 sup_speed;
2902 __be32 cur_speed;
2903 __be32 max_frame_size;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002904 uint8_t os_dev_name[32];
Himanshu Madhanidd83cb22015-04-09 14:59:55 -04002905 uint8_t host_name[256];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002906
2907 uint8_t node_name[WWN_SIZE];
2908 uint8_t port_name[WWN_SIZE];
2909 uint8_t port_sym_name[128];
Bart Van Assche21038b02020-05-18 14:17:11 -07002910 __be32 port_type;
2911 __be32 port_supported_cos;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002912 uint8_t fabric_name[WWN_SIZE];
2913 uint8_t port_fc4_type[32];
Bart Van Assche21038b02020-05-18 14:17:11 -07002914 __be32 port_state;
2915 __be32 num_ports;
2916 __be32 port_id;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002917
2918 uint8_t smartsan_service[24];
2919 uint8_t smartsan_guid[16];
2920 uint8_t smartsan_version[24];
2921 uint8_t smartsan_prod_name[16];
Bart Van Assche21038b02020-05-18 14:17:11 -07002922 __be32 smartsan_port_info;
2923 __be32 smartsan_qos_support;
2924 __be32 smartsan_security_support;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002925 } a;
2926};
2927
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002928struct ct_fdmi1_port_attributes {
Bart Van Assche21038b02020-05-18 14:17:11 -07002929 __be32 count;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002930 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
Andrew Vasquezcca53352005-08-26 19:08:30 -07002931};
2932
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002933struct ct_fdmi2_port_attributes {
Bart Van Assche21038b02020-05-18 14:17:11 -07002934 __be32 count;
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002935 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2936};
2937
2938#define FDMI_ATTR_TYPELEN(obj) \
2939 (sizeof((obj)->type) + sizeof((obj)->len))
2940
2941#define FDMI_ATTR_ALIGNMENT(len) \
2942 (4 - ((len) & 3))
2943
2944/* FDMI register call options */
2945#define CALLOPT_FDMI1 0
2946#define CALLOPT_FDMI2 1
2947#define CALLOPT_FDMI2_SMARTSAN 2
2948
Andrew Vasquezcca53352005-08-26 19:08:30 -07002949/* FDMI definitions. */
2950#define GRHL_CMD 0x100
2951#define GHAT_CMD 0x101
2952#define GRPL_CMD 0x102
2953#define GPAT_CMD 0x110
2954
2955#define RHBA_CMD 0x200
2956#define RHBA_RSP_SIZE 16
2957
2958#define RHAT_CMD 0x201
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002959
Andrew Vasquezcca53352005-08-26 19:08:30 -07002960#define RPRT_CMD 0x210
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002961#define RPRT_RSP_SIZE 24
Andrew Vasquezcca53352005-08-26 19:08:30 -07002962
2963#define RPA_CMD 0x211
2964#define RPA_RSP_SIZE 16
Joe Carnuccio52bfb082020-02-12 13:44:20 -08002965#define SMARTSAN_RPA_RSP_SIZE 24
Andrew Vasquezcca53352005-08-26 19:08:30 -07002966
2967#define DHBA_CMD 0x300
2968#define DHBA_REQ_SIZE (16 + 8)
2969#define DHBA_RSP_SIZE 16
2970
2971#define DHAT_CMD 0x301
2972#define DPRT_CMD 0x310
2973#define DPA_CMD 0x311
2974
Linus Torvalds1da177e2005-04-16 15:20:36 -07002975/* CT command header -- request/response common fields */
2976struct ct_cmd_hdr {
2977 uint8_t revision;
2978 uint8_t in_id[3];
2979 uint8_t gs_type;
2980 uint8_t gs_subtype;
2981 uint8_t options;
2982 uint8_t reserved;
2983};
2984
2985/* CT command request */
2986struct ct_sns_req {
2987 struct ct_cmd_hdr header;
Bart Van Assche21038b02020-05-18 14:17:11 -07002988 __be16 command;
2989 __be16 max_rsp_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990 uint8_t fragment_id;
2991 uint8_t reserved[3];
2992
2993 union {
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002994 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002995 struct {
2996 uint8_t reserved;
Bart Van Asschedf95f392019-08-08 20:01:58 -07002997 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002998 } port_id;
2999
3000 struct {
Quinn Trana4239942017-12-28 12:33:26 -08003001 uint8_t reserved;
3002 uint8_t domain;
3003 uint8_t area;
3004 uint8_t port_type;
3005 } gpn_ft;
3006
3007 struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003008 uint8_t port_type;
3009 uint8_t domain;
3010 uint8_t area;
3011 uint8_t reserved;
3012 } gid_pt;
3013
3014 struct {
3015 uint8_t reserved;
Bart Van Asschedf95f392019-08-08 20:01:58 -07003016 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003017 uint8_t fc4_types[32];
3018 } rft_id;
3019
3020 struct {
3021 uint8_t reserved;
Bart Van Asschedf95f392019-08-08 20:01:58 -07003022 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003023 uint16_t reserved2;
3024 uint8_t fc4_feature;
3025 uint8_t fc4_type;
3026 } rff_id;
3027
3028 struct {
3029 uint8_t reserved;
Bart Van Asschedf95f392019-08-08 20:01:58 -07003030 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003031 uint8_t node_name[8];
3032 } rnn_id;
3033
3034 struct {
3035 uint8_t node_name[8];
3036 uint8_t name_len;
3037 uint8_t sym_node_name[255];
3038 } rsnn_nn;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003039
3040 struct {
Colin Ian King577419f2016-12-29 22:20:38 +00003041 uint8_t hba_identifier[8];
Andrew Vasquezcca53352005-08-26 19:08:30 -07003042 } ghat;
3043
3044 struct {
3045 uint8_t hba_identifier[8];
Bart Van Assche21038b02020-05-18 14:17:11 -07003046 __be32 entry_count;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003047 uint8_t port_name[8];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003048 struct ct_fdmi2_hba_attributes attrs;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003049 } rhba;
3050
3051 struct {
3052 uint8_t hba_identifier[8];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003053 struct ct_fdmi1_hba_attributes attrs;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003054 } rhat;
3055
3056 struct {
3057 uint8_t port_name[8];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003058 struct ct_fdmi2_port_attributes attrs;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003059 } rpa;
3060
3061 struct {
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003062 uint8_t hba_identifier[8];
Andrew Vasquezcca53352005-08-26 19:08:30 -07003063 uint8_t port_name[8];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003064 struct ct_fdmi2_port_attributes attrs;
3065 } rprt;
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04003066
3067 struct {
3068 uint8_t port_name[8];
Andrew Vasquezcca53352005-08-26 19:08:30 -07003069 } dhba;
3070
3071 struct {
3072 uint8_t port_name[8];
3073 } dhat;
3074
3075 struct {
3076 uint8_t port_name[8];
3077 } dprt;
3078
3079 struct {
3080 uint8_t port_name[8];
3081 } dpa;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07003082
3083 struct {
3084 uint8_t port_name[8];
3085 } gpsc;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05003086
3087 struct {
3088 uint8_t reserved;
Duane Grigsbya5d42f42017-06-21 13:48:41 -07003089 uint8_t port_id[3];
Chad Dupuise8c72ba2010-07-23 15:28:25 +05003090 } gff_id;
Quinn Tran726b8542017-01-19 22:28:00 -08003091
3092 struct {
3093 uint8_t port_name[8];
3094 } gid_pn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003095 } req;
3096};
3097
3098/* CT command response header */
3099struct ct_rsp_hdr {
3100 struct ct_cmd_hdr header;
Bart Van Assche21038b02020-05-18 14:17:11 -07003101 __be16 response;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003102 uint16_t residual;
3103 uint8_t fragment_id;
3104 uint8_t reason_code;
3105 uint8_t explanation_code;
3106 uint8_t vendor_unique;
3107};
3108
3109struct ct_sns_gid_pt_data {
3110 uint8_t control_byte;
Bart Van Asschedf95f392019-08-08 20:01:58 -07003111 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003112};
3113
Quinn Trana4239942017-12-28 12:33:26 -08003114/* It's the same for both GPN_FT and GNN_FT */
3115struct ct_sns_gpnft_rsp {
3116 struct {
3117 struct ct_cmd_hdr header;
3118 uint16_t response;
3119 uint16_t residual;
3120 uint8_t fragment_id;
3121 uint8_t reason_code;
3122 uint8_t explanation_code;
3123 uint8_t vendor_unique;
3124 };
3125 /* Assume the largest number of targets for the union */
3126 struct ct_sns_gpn_ft_data {
3127 u8 control_byte;
3128 u8 port_id[3];
3129 u32 reserved;
3130 u8 port_name[8];
3131 } entries[1];
3132};
3133
3134/* CT command response */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003135struct ct_sns_rsp {
3136 struct ct_rsp_hdr header;
3137
3138 union {
3139 struct {
3140 uint8_t port_type;
Bart Van Asschedf95f392019-08-08 20:01:58 -07003141 be_id_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003142 uint8_t port_name[8];
3143 uint8_t sym_port_name_len;
3144 uint8_t sym_port_name[255];
3145 uint8_t node_name[8];
3146 uint8_t sym_node_name_len;
3147 uint8_t sym_node_name[255];
3148 uint8_t init_proc_assoc[8];
3149 uint8_t node_ip_addr[16];
3150 uint8_t class_of_service[4];
3151 uint8_t fc4_types[32];
3152 uint8_t ip_address[16];
3153 uint8_t fabric_port_name[8];
3154 uint8_t reserved;
3155 uint8_t hard_address[3];
3156 } ga_nxt;
3157
3158 struct {
Chad Dupuis642ef982012-02-09 11:15:57 -08003159 /* Assume the largest number of targets for the union */
3160 struct ct_sns_gid_pt_data
3161 entries[MAX_FIBRE_DEVICES_MAX];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003162 } gid_pt;
3163
3164 struct {
3165 uint8_t port_name[8];
3166 } gpn_id;
3167
3168 struct {
3169 uint8_t node_name[8];
3170 } gnn_id;
3171
3172 struct {
3173 uint8_t fc4_types[32];
3174 } gft_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003175
3176 struct {
3177 uint32_t entry_count;
3178 uint8_t port_name[8];
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003179 struct ct_fdmi1_hba_attributes attrs;
Andrew Vasquezcca53352005-08-26 19:08:30 -07003180 } ghat;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07003181
3182 struct {
3183 uint8_t port_name[8];
3184 } gfpn_id;
3185
3186 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003187 __be16 speeds;
3188 __be16 speed;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07003189 } gpsc;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05003190
3191#define GFF_FCP_SCSI_OFFSET 7
Duane Grigsbyd3bae932017-06-21 13:48:44 -07003192#define GFF_NVME_OFFSET 23 /* type = 28h */
Chad Dupuise8c72ba2010-07-23 15:28:25 +05003193 struct {
3194 uint8_t fc4_features[128];
3195 } gff_id;
Quinn Tran726b8542017-01-19 22:28:00 -08003196 struct {
3197 uint8_t reserved;
3198 uint8_t port_id[3];
3199 } gid_pn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003200 } rsp;
3201};
3202
3203struct ct_sns_pkt {
3204 union {
3205 struct ct_sns_req req;
3206 struct ct_sns_rsp rsp;
3207 } p;
3208};
3209
Quinn Trana4239942017-12-28 12:33:26 -08003210struct ct_sns_gpnft_pkt {
3211 union {
3212 struct ct_sns_req req;
3213 struct ct_sns_gpnft_rsp rsp;
3214 } p;
3215};
3216
Quinn Tranf352eeb2017-12-28 12:33:35 -08003217enum scan_flags_t {
3218 SF_SCANNING = BIT_0,
3219 SF_QUEUED = BIT_1,
3220};
3221
Quinn Tran33b28352018-03-20 23:09:40 -07003222enum fc4type_t {
3223 FS_FC4TYPE_FCP = BIT_0,
3224 FS_FC4TYPE_NVME = BIT_1,
Quinn Tran7f2a3982019-09-12 11:09:09 -07003225 FS_FCP_IS_N2N = BIT_7,
Quinn Tran33b28352018-03-20 23:09:40 -07003226};
3227
Quinn Trana4239942017-12-28 12:33:26 -08003228struct fab_scan_rp {
3229 port_id_t id;
Quinn Tran33b28352018-03-20 23:09:40 -07003230 enum fc4type_t fc4type;
Quinn Trana4239942017-12-28 12:33:26 -08003231 u8 port_name[8];
3232 u8 node_name[8];
3233};
3234
3235struct fab_scan {
3236 struct fab_scan_rp *l;
3237 u32 size;
Quinn Tran6944dcc2017-12-28 12:33:39 -08003238 u16 scan_retry;
3239#define MAX_SCAN_RETRIES 5
Quinn Tranf352eeb2017-12-28 12:33:35 -08003240 enum scan_flags_t scan_flags;
3241 struct delayed_work scan_work;
Quinn Trana4239942017-12-28 12:33:26 -08003242};
3243
Linus Torvalds1da177e2005-04-16 15:20:36 -07003244/*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003245 * SNS command structures -- for 2200 compatibility.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003246 */
3247#define RFT_ID_SNS_SCMD_LEN 22
3248#define RFT_ID_SNS_CMD_SIZE 60
3249#define RFT_ID_SNS_DATA_SIZE 16
3250
3251#define RNN_ID_SNS_SCMD_LEN 10
3252#define RNN_ID_SNS_CMD_SIZE 36
3253#define RNN_ID_SNS_DATA_SIZE 16
3254
3255#define GA_NXT_SNS_SCMD_LEN 6
3256#define GA_NXT_SNS_CMD_SIZE 28
3257#define GA_NXT_SNS_DATA_SIZE (620 + 16)
3258
3259#define GID_PT_SNS_SCMD_LEN 6
3260#define GID_PT_SNS_CMD_SIZE 28
Chad Dupuis642ef982012-02-09 11:15:57 -08003261/*
3262 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3263 * adapters.
3264 */
3265#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003266
3267#define GPN_ID_SNS_SCMD_LEN 6
3268#define GPN_ID_SNS_CMD_SIZE 28
3269#define GPN_ID_SNS_DATA_SIZE (8 + 16)
3270
3271#define GNN_ID_SNS_SCMD_LEN 6
3272#define GNN_ID_SNS_CMD_SIZE 28
3273#define GNN_ID_SNS_DATA_SIZE (8 + 16)
3274
3275struct sns_cmd_pkt {
3276 union {
3277 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003278 __le16 buffer_length;
3279 __le16 reserved_1;
3280 __le64 buffer_address __packed;
3281 __le16 subcommand_length;
3282 __le16 reserved_2;
3283 __le16 subcommand;
3284 __le16 size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003285 uint32_t reserved_3;
3286 uint8_t param[36];
3287 } cmd;
3288
3289 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3290 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3291 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3292 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3293 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3294 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3295 } p;
3296};
3297
Andrew Vasquez54333832005-11-09 15:49:04 -08003298struct fw_blob {
3299 char *name;
3300 uint32_t segs[4];
3301 const struct firmware *fw;
3302};
3303
Linus Torvalds1da177e2005-04-16 15:20:36 -07003304/* Return data from MBC_GET_ID_LIST call. */
3305struct gid_list_info {
3306 uint8_t al_pa;
3307 uint8_t area;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07003308 uint8_t domain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003309 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
Bart Van Assche21038b02020-05-18 14:17:11 -07003310 __le16 loop_id; /* ISP23XX -- 6 bytes. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07003311 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003312};
Linus Torvalds1da177e2005-04-16 15:20:36 -07003313
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003314/* NPIV */
3315typedef struct vport_info {
3316 uint8_t port_name[WWN_SIZE];
3317 uint8_t node_name[WWN_SIZE];
3318 int vp_id;
3319 uint16_t loop_id;
3320 unsigned long host_no;
3321 uint8_t port_id[3];
3322 int loop_state;
3323} vport_info_t;
3324
3325typedef struct vport_params {
3326 uint8_t port_name[WWN_SIZE];
3327 uint8_t node_name[WWN_SIZE];
3328 uint32_t options;
3329#define VP_OPTS_RETRY_ENABLE BIT_0
3330#define VP_OPTS_VP_DISABLE BIT_1
3331} vport_params_t;
3332
3333/* NPIV - return codes of VP create and modify */
3334#define VP_RET_CODE_OK 0
3335#define VP_RET_CODE_FATAL 1
3336#define VP_RET_CODE_WRONG_ID 2
3337#define VP_RET_CODE_WWPN 3
3338#define VP_RET_CODE_RESOURCES 4
3339#define VP_RET_CODE_NO_MEM 5
3340#define VP_RET_CODE_NOT_FOUND 6
3341
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003342struct qla_hw_data;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07003343struct rsp_que;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003344/*
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003345 * ISP operations
3346 */
3347struct isp_operations {
3348
3349 int (*pci_config) (struct scsi_qla_host *);
Michael Hernandez3f006ac2019-03-12 11:08:22 -07003350 int (*reset_chip)(struct scsi_qla_host *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003351 int (*chip_diag) (struct scsi_qla_host *);
3352 void (*config_rings) (struct scsi_qla_host *);
Michael Hernandez3f006ac2019-03-12 11:08:22 -07003353 int (*reset_adapter)(struct scsi_qla_host *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003354 int (*nvram_config) (struct scsi_qla_host *);
3355 void (*update_fw_options) (struct scsi_qla_host *);
3356 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3357
Bart Van Asschedc6d6d32019-08-08 20:01:55 -07003358 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
Himanshu Madhanidf57cab2014-09-25 05:16:46 -04003359 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003360
David Howells7d12e782006-10-05 14:55:46 +01003361 irq_handler_t intr_handler;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003362 void (*enable_intrs) (struct qla_hw_data *);
3363 void (*disable_intrs) (struct qla_hw_data *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003364
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07003365 int (*abort_command) (srb_t *);
Hannes Reinecke9cb78c12014-06-25 15:27:36 +02003366 int (*target_reset) (struct fc_port *, uint64_t, int);
3367 int (*lun_reset) (struct fc_port *, uint64_t, int);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003368 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3369 uint8_t, uint8_t, uint16_t *, uint8_t);
Andrew Vasquez1c7c6352005-07-06 10:30:57 -07003370 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3371 uint8_t, uint8_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003372
3373 uint16_t (*calc_req_entries) (uint16_t);
3374 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
Quinn Tran726b8542017-01-19 22:28:00 -08003375 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3376 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
Andrew Vasquezcca53352005-08-26 19:08:30 -07003377 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003378
Joe Carnuccio36953102019-03-12 11:08:18 -07003379 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003380 uint32_t, uint32_t);
Joe Carnuccio36953102019-03-12 11:08:18 -07003381 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003382 uint32_t);
3383
Bart Van Assche8ae17872020-05-18 14:17:00 -07003384 void (*fw_dump)(struct scsi_qla_host *vha);
Arun Easicbb01c22020-03-31 03:40:13 -07003385 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08003386
Ahmed S. Darwish8ac246b2020-11-26 14:29:42 +01003387 /* Context: task, might sleep */
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08003388 int (*beacon_on) (struct scsi_qla_host *);
3389 int (*beacon_off) (struct scsi_qla_host *);
Ahmed S. Darwish8ac246b2020-11-26 14:29:42 +01003390
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08003391 void (*beacon_blink) (struct scsi_qla_host *);
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003392
Joe Carnuccio36953102019-03-12 11:08:18 -07003393 void *(*read_optrom)(struct scsi_qla_host *, void *,
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003394 uint32_t, uint32_t);
Joe Carnuccio36953102019-03-12 11:08:18 -07003395 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003396 uint32_t);
Andrew Vasquez30c47662007-01-29 10:22:21 -08003397
3398 int (*get_flash_version) (struct scsi_qla_host *, void *);
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003399 int (*start_scsi) (srb_t *);
Michael Hernandezd7459522016-12-12 14:40:07 -08003400 int (*start_scsi_mq) (srb_t *);
Ahmed S. Darwish8ac246b2020-11-26 14:29:42 +01003401
3402 /* Context: task, might sleep */
Giridhar Malavalia9083012010-04-12 17:59:55 -07003403 int (*abort_isp) (struct scsi_qla_host *);
Ahmed S. Darwish8ac246b2020-11-26 14:29:42 +01003404
Bart Van Assche845bbb02019-04-11 14:53:18 -07003405 int (*iospace_config)(struct qla_hw_data *);
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003406 int (*initialize_adapter)(struct scsi_qla_host *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003407};
3408
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003409/* MSI-X Support *************************************************************/
3410
3411#define QLA_MSIX_CHIP_REV_24XX 3
3412#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3413#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3414
Christoph Hellwig17e5fc52017-01-11 17:55:45 +01003415#define QLA_BASE_VECTORS 2 /* default + RSP */
Michael Hernandezd7459522016-12-12 14:40:07 -08003416#define QLA_MSIX_RSP_Q 0x01
Quinn Tran093df732016-12-12 14:40:09 -08003417#define QLA_ATIO_VECTOR 0x02
3418#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
Andrew Vasquez7b2a7392020-02-26 14:40:11 -08003419#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003420
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003421#define QLA_MIDX_DEFAULT 0
3422#define QLA_MIDX_RSP_Q 1
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003423#define QLA_PCI_MSIX_CONTROL 0xa2
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08003424#define QLA_83XX_PCI_MSIX_CONTROL 0x92
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003425
3426struct scsi_qla_host;
3427
Quinn Trancdb898c2015-12-17 14:57:05 -05003428
3429#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3430
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003431struct qla_msix_entry {
3432 int have_irq;
Michael Hernandezd7459522016-12-12 14:40:07 -08003433 int in_use;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003434 uint32_t vector;
3435 uint16_t entry;
Michael Hernandezd7459522016-12-12 14:40:07 -08003436 char name[30];
Michael Hernandez4fa18342016-12-12 14:40:06 -08003437 void *handle;
Quinn Trancdb898c2015-12-17 14:57:05 -05003438 int cpuid;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003439};
3440
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003441#define WATCH_INTERVAL 1 /* number of seconds */
3442
Andrew Vasquez0971de72008-04-03 13:13:18 -07003443/* Work events. */
3444enum qla_work_type {
3445 QLA_EVT_AEN,
Andrew Vasquez8a659572009-02-08 20:50:12 -08003446 QLA_EVT_IDC_ACK,
Andrew Vasquezac280b62009-08-20 11:06:05 -07003447 QLA_EVT_ASYNC_LOGIN,
Andrew Vasquezac280b62009-08-20 11:06:05 -07003448 QLA_EVT_ASYNC_LOGOUT,
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07003449 QLA_EVT_ASYNC_ADISC,
Andrew Vasquez3420d362009-10-13 15:16:45 -07003450 QLA_EVT_UEVENT,
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003451 QLA_EVT_AENFX,
Quinn Tran726b8542017-01-19 22:28:00 -08003452 QLA_EVT_GPNID,
Quinn Trane374f9f2017-12-28 12:33:31 -08003453 QLA_EVT_UNMAP,
Quinn Tran726b8542017-01-19 22:28:00 -08003454 QLA_EVT_NEW_SESS,
3455 QLA_EVT_GPDB,
Duane Grigsbya5d42f42017-06-21 13:48:41 -07003456 QLA_EVT_PRLI,
Quinn Tran726b8542017-01-19 22:28:00 -08003457 QLA_EVT_GPSC,
Quinn Tran726b8542017-01-19 22:28:00 -08003458 QLA_EVT_GNL,
3459 QLA_EVT_NACK,
Quinn Tran9b3e0f42017-12-28 12:33:16 -08003460 QLA_EVT_RELOGIN,
Quinn Tran11aea162017-12-28 12:33:20 -08003461 QLA_EVT_ASYNC_PRLO,
3462 QLA_EVT_ASYNC_PRLO_DONE,
Quinn Trana4239942017-12-28 12:33:26 -08003463 QLA_EVT_GPNFT,
3464 QLA_EVT_GPNFT_DONE,
3465 QLA_EVT_GNNFT_DONE,
3466 QLA_EVT_GNNID,
3467 QLA_EVT_GFPNID,
Quinn Trane374f9f2017-12-28 12:33:31 -08003468 QLA_EVT_SP_RETRY,
Quinn Trancc28e0a2018-05-01 09:01:48 -07003469 QLA_EVT_IIDMA,
Quinn Tran8777e432018-08-02 13:16:57 -07003470 QLA_EVT_ELS_PLOGI,
Quinn Trandd307062021-06-23 22:26:00 -07003471 QLA_EVT_SA_REPLACE,
Andrew Vasquez0971de72008-04-03 13:13:18 -07003472};
3473
3474
3475struct qla_work_evt {
3476 struct list_head list;
3477 enum qla_work_type type;
3478 u32 flags;
3479#define QLA_EVT_FLAG_FREE 0x1
3480
3481 union {
3482 struct {
3483 enum fc_host_event_code code;
3484 u32 data;
3485 } aen;
Andrew Vasquez8a659572009-02-08 20:50:12 -08003486 struct {
3487#define QLA_IDC_ACK_REGS 7
3488 uint16_t mb[QLA_IDC_ACK_REGS];
3489 } idc_ack;
Andrew Vasquezac280b62009-08-20 11:06:05 -07003490 struct {
3491 struct fc_port *fcport;
3492#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3493 u16 data[2];
3494 } logio;
Andrew Vasquez3420d362009-10-13 15:16:45 -07003495 struct {
3496 u32 code;
3497#define QLA_UEVENT_CODE_FW_DUMP 0
3498 } uevent;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003499 struct {
3500 uint32_t evtcode;
3501 uint32_t mbx[8];
3502 uint32_t count;
3503 } aenfx;
3504 struct {
3505 srb_t *sp;
3506 } iosb;
Quinn Tran726b8542017-01-19 22:28:00 -08003507 struct {
3508 port_id_t id;
3509 } gpnid;
3510 struct {
3511 port_id_t id;
3512 u8 port_name[8];
Quinn Trana4239942017-12-28 12:33:26 -08003513 u8 node_name[8];
Quinn Tran726b8542017-01-19 22:28:00 -08003514 void *pla;
Quinn Trana4239942017-12-28 12:33:26 -08003515 u8 fc4_type;
Quinn Tran726b8542017-01-19 22:28:00 -08003516 } new_sess;
3517 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3518 fc_port_t *fcport;
3519 u8 opt;
3520 } fcport;
3521 struct {
3522 fc_port_t *fcport;
3523 u8 iocb[IOCB_SIZE];
3524 int type;
3525 } nack;
Quinn Trana4239942017-12-28 12:33:26 -08003526 struct {
3527 u8 fc4_type;
Quinn Tran33b28352018-03-20 23:09:40 -07003528 srb_t *sp;
Quinn Trana4239942017-12-28 12:33:26 -08003529 } gpnft;
Quinn Trandd307062021-06-23 22:26:00 -07003530 struct {
3531 struct edif_sa_ctl *sa_ctl;
3532 fc_port_t *fcport;
3533 uint16_t nport_handle;
3534 } sa_update;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003535 } u;
Andrew Vasquez0971de72008-04-03 13:13:18 -07003536};
3537
Harihara Kadayam4d4df192008-04-03 13:13:26 -07003538struct qla_chip_state_84xx {
3539 struct list_head list;
3540 struct kref kref;
3541
3542 void *bus;
3543 spinlock_t access_lock;
3544 struct mutex fw_update_mutex;
3545 uint32_t fw_update;
3546 uint32_t op_fw_version;
3547 uint32_t op_fw_size;
3548 uint32_t op_fw_seq_size;
3549 uint32_t diag_fw_version;
3550 uint32_t gold_fw_version;
3551};
3552
Anil Gurumurthy54b99932017-03-15 09:48:50 -07003553struct qla_dif_statistics {
3554 uint64_t dif_input_bytes;
3555 uint64_t dif_output_bytes;
3556 uint64_t dif_input_requests;
3557 uint64_t dif_output_requests;
3558 uint32_t dif_guard_err;
3559 uint32_t dif_ref_tag_err;
3560 uint32_t dif_app_tag_err;
3561};
3562
Harish Zunjarraoe5f5f6f2008-07-10 16:55:49 -07003563struct qla_statistics {
3564 uint32_t total_isp_aborts;
Harish Zunjarrao49fd4622008-09-11 21:22:47 -07003565 uint64_t input_bytes;
3566 uint64_t output_bytes;
Joe Carnucciofabbb8d2013-08-27 01:37:40 -04003567 uint64_t input_requests;
3568 uint64_t output_requests;
3569 uint32_t control_requests;
3570
3571 uint64_t jiffies_at_last_reset;
Quinn Tran33e79972014-09-25 06:14:55 -04003572 uint32_t stat_max_pend_cmds;
3573 uint32_t stat_max_qfull_cmds_alloc;
3574 uint32_t stat_max_qfull_cmds_dropped;
Anil Gurumurthy54b99932017-03-15 09:48:50 -07003575
3576 struct qla_dif_statistics qla_dif_stats;
Harish Zunjarraoe5f5f6f2008-07-10 16:55:49 -07003577};
3578
Saurav Kashyapa9b6f722012-08-22 14:21:01 -04003579struct bidi_statistics {
3580 unsigned long long io_count;
3581 unsigned long long transfer_bytes;
3582};
3583
Quinn Tranbe251522017-03-15 09:48:49 -07003584struct qla_tc_param {
3585 struct scsi_qla_host *vha;
3586 uint32_t blk_sz;
3587 uint32_t bufflen;
3588 struct scatterlist *sg;
3589 struct scatterlist *prot_sg;
3590 struct crc_context *ctx;
3591 uint8_t *ctx_dsd_alloced;
3592};
3593
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003594/* Multi queue support */
3595#define MBC_INITIALIZE_MULTIQ 0x1f
3596#define QLA_QUE_PAGE 0X1000
3597#define QLA_MQ_SIZE 32
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003598#define QLA_MAX_QUEUES 256
3599#define ISP_QUE_REG(ha, id) \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07003600 ((ha->mqenable || IS_QLA83XX(ha) || \
3601 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
Andrew Vasquezda9b1d52013-08-27 01:37:30 -04003602 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3603 ((void __iomem *)ha->iobase))
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003604#define QLA_REQ_QUE_ID(tag) \
3605 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3606#define QLA_DEFAULT_QUE_QOS 5
3607#define QLA_PRECONFIG_VPORTS 32
3608#define QLA_MAX_VPORTS_QLA24XX 128
3609#define QLA_MAX_VPORTS_QLA25XX 256
Quinn Tran82de8022017-06-13 20:47:17 -07003610
Quinn Tran60a9ead2017-06-13 20:47:28 -07003611struct qla_tgt_counters {
3612 uint64_t qla_core_sbt_cmd;
3613 uint64_t core_qla_que_buf;
3614 uint64_t qla_core_ret_ctio;
3615 uint64_t core_qla_snd_status;
3616 uint64_t qla_core_ret_sta_ctio;
3617 uint64_t core_qla_free_cmd;
3618 uint64_t num_q_full_sent;
3619 uint64_t num_alloc_iocb_failed;
3620 uint64_t num_term_xchg_sent;
3621};
3622
Quinn Tran49db4d42020-09-03 21:51:22 -07003623struct qla_counters {
3624 uint64_t input_bytes;
3625 uint64_t input_requests;
3626 uint64_t output_bytes;
3627 uint64_t output_requests;
3628
3629};
3630
Quinn Tran82de8022017-06-13 20:47:17 -07003631struct qla_qpair;
3632
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003633/* Response queue data structure */
3634struct rsp_que {
3635 dma_addr_t dma;
3636 response_t *ring;
3637 response_t *ring_ptr;
Bart Van Assche21038b02020-05-18 14:17:11 -07003638 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */
3639 __le32 __iomem *rsp_q_out;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003640 uint16_t ring_index;
3641 uint16_t out_ptr;
Joe Carnuccio7c6300e2014-04-11 16:54:37 -04003642 uint16_t *in_ptr; /* queue shadow in index */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003643 uint16_t length;
3644 uint16_t options;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003645 uint16_t rid;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003646 uint16_t id;
3647 uint16_t vp_idx;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003648 struct qla_hw_data *hw;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003649 struct qla_msix_entry *msix;
3650 struct req_que *req;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07003651 srb_t *status_srb; /* status continuation entry */
Quinn Tran82de8022017-06-13 20:47:17 -07003652 struct qla_qpair *qpair;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003653
3654 dma_addr_t dma_fx00;
3655 response_t *ring_fx00;
3656 uint16_t length_fx00;
3657 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003658};
3659
3660/* Request queue data structure */
3661struct req_que {
3662 dma_addr_t dma;
3663 request_t *ring;
3664 request_t *ring_ptr;
Bart Van Assche21038b02020-05-18 14:17:11 -07003665 __le32 __iomem *req_q_in; /* FWI2-capable only. */
3666 __le32 __iomem *req_q_out;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003667 uint16_t ring_index;
3668 uint16_t in_ptr;
Joe Carnuccio7c6300e2014-04-11 16:54:37 -04003669 uint16_t *out_ptr; /* queue shadow out index */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003670 uint16_t cnt;
3671 uint16_t length;
3672 uint16_t options;
3673 uint16_t rid;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003674 uint16_t id;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003675 uint16_t qos;
3676 uint16_t vp_idx;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003677 struct rsp_que *rsp;
Chad Dupuis8d93f552013-01-30 03:34:37 -05003678 srb_t **outstanding_cmds;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003679 uint32_t current_outstanding_cmd;
Chad Dupuis8d93f552013-01-30 03:34:37 -05003680 uint16_t num_outstanding_cmds;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003681 int max_q_depth;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003682
3683 dma_addr_t dma_fx00;
3684 request_t *ring_fx00;
3685 uint16_t length_fx00;
3686 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003687};
3688
Quinn Tran89c72f42020-09-03 21:51:26 -07003689struct qla_fw_resources {
3690 u16 iocbs_total;
3691 u16 iocbs_limit;
3692 u16 iocbs_qp_limit;
3693 u16 iocbs_used;
3694};
3695
3696#define QLA_IOCB_PCT_LIMIT 95
3697
Michael Hernandezd7459522016-12-12 14:40:07 -08003698/*Queue pair data structure */
3699struct qla_qpair {
3700 spinlock_t qp_lock;
3701 atomic_t ref_count;
Quinn Trane326d222017-06-13 20:47:18 -07003702 uint32_t lun_cnt;
Quinn Tran82de8022017-06-13 20:47:17 -07003703 /*
3704 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3705 * legacy code. For other Qpair(s), it will point at qp_lock.
3706 */
3707 spinlock_t *qp_lock_ptr;
3708 struct scsi_qla_host *vha;
Quinn Tran7c3f8fd2017-06-13 20:47:22 -07003709 u32 chip_reset;
Quinn Tran82de8022017-06-13 20:47:17 -07003710
Michael Hernandezd7459522016-12-12 14:40:07 -08003711 /* distill these fields down to 'online=0/1'
3712 * ha->flags.eeh_busy
3713 * ha->flags.pci_channel_io_perm_failure
3714 * base_vha->loop_state
3715 */
3716 uint32_t online:1;
3717 /* move vha->flags.difdix_supported here */
3718 uint32_t difdix_supported:1;
3719 uint32_t delete_in_progress:1;
Quinn Tran4b60c822017-06-13 20:47:21 -07003720 uint32_t fw_started:1;
Quinn Tran7c3f8fd2017-06-13 20:47:22 -07003721 uint32_t enable_class_2:1;
3722 uint32_t enable_explicit_conf:1;
Quinn Tranaf7bb382017-06-13 20:47:23 -07003723 uint32_t use_shadow_reg:1;
Quinn Tran49db4d42020-09-03 21:51:22 -07003724 uint32_t rcv_intr:1;
Michael Hernandezd7459522016-12-12 14:40:07 -08003725
3726 uint16_t id; /* qp number used with FW */
Michael Hernandezd7459522016-12-12 14:40:07 -08003727 uint16_t vp_idx; /* vport ID */
Michael Hernandezd7459522016-12-12 14:40:07 -08003728 mempool_t *srb_mempool;
3729
Quinn Tran8abfa9e2017-06-13 20:47:24 -07003730 struct pci_dev *pdev;
3731 void (*reqq_start_iocbs)(struct qla_qpair *);
3732
Michael Hernandezd7459522016-12-12 14:40:07 -08003733 /* to do: New driver: move queues to here instead of pointers */
3734 struct req_que *req;
3735 struct rsp_que *rsp;
3736 struct atio_que *atio;
3737 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3738 struct qla_hw_data *hw;
3739 struct work_struct q_work;
Quinn Tran49db4d42020-09-03 21:51:22 -07003740 struct qla_counters counters;
3741
Michael Hernandezd7459522016-12-12 14:40:07 -08003742 struct list_head qp_list_elem; /* vha->qp_list */
Quinn Trane326d222017-06-13 20:47:18 -07003743 struct list_head hints_list;
Quinn Tran49db4d42020-09-03 21:51:22 -07003744
Quinn Tran06910942018-09-04 14:19:12 -07003745 uint16_t retry_term_cnt;
Bart Van Assche21038b02020-05-18 14:17:11 -07003746 __le32 retry_term_exchg_addr;
Quinn Tran06910942018-09-04 14:19:12 -07003747 uint64_t retry_term_jiff;
Quinn Tran60a9ead2017-06-13 20:47:28 -07003748 struct qla_tgt_counters tgt_counters;
Quinn Tran49db4d42020-09-03 21:51:22 -07003749 uint16_t cpuid;
Quinn Tran89c72f42020-09-03 21:51:26 -07003750 struct qla_fw_resources fwres ____cacheline_aligned;
Quinn Trand94d8152021-06-18 22:24:27 -07003751 u32 cmd_cnt;
3752 u32 cmd_completion_cnt;
Manish Rangankar3a4e1f32021-09-08 09:46:20 -07003753 u32 prev_completion_cnt;
Michael Hernandezd7459522016-12-12 14:40:07 -08003754};
3755
Giridhar Malavali9a069e12010-01-12 13:02:47 -08003756/* Place holder for FW buffer parameters */
3757struct qlfc_fw {
3758 void *fw_buf;
3759 dma_addr_t fw_dma;
3760 uint32_t len;
3761};
3762
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003763struct rdp_req_payload {
3764 uint32_t els_request;
3765 uint32_t desc_list_len;
3766
3767 /* NPIV descriptor */
3768 struct {
3769 uint32_t desc_tag;
3770 uint32_t desc_len;
3771 uint8_t reserved;
3772 uint8_t nport_id[3];
3773 } npiv_desc;
3774};
3775
3776struct rdp_rsp_payload {
3777 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003778 __be32 cmd;
3779 __be32 len;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003780 } hdr;
3781
3782 /* LS Request Info descriptor */
3783 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003784 __be32 desc_tag;
3785 __be32 desc_len;
3786 __be32 req_payload_word_0;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003787 } ls_req_info_desc;
3788
3789 /* LS Request Info descriptor */
3790 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003791 __be32 desc_tag;
3792 __be32 desc_len;
3793 __be32 req_payload_word_0;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003794 } ls_req_info_desc2;
3795
3796 /* SFP diagnostic param descriptor */
3797 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003798 __be32 desc_tag;
3799 __be32 desc_len;
3800 __be16 temperature;
3801 __be16 vcc;
3802 __be16 tx_bias;
3803 __be16 tx_power;
3804 __be16 rx_power;
3805 __be16 sfp_flags;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003806 } sfp_diag_desc;
3807
3808 /* Port Speed Descriptor */
3809 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003810 __be32 desc_tag;
3811 __be32 desc_len;
3812 __be16 speed_capab;
3813 __be16 operating_speed;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003814 } port_speed_desc;
3815
3816 /* Link Error Status Descriptor */
3817 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003818 __be32 desc_tag;
3819 __be32 desc_len;
3820 __be32 link_fail_cnt;
3821 __be32 loss_sync_cnt;
3822 __be32 loss_sig_cnt;
3823 __be32 prim_seq_err_cnt;
3824 __be32 inval_xmit_word_cnt;
3825 __be32 inval_crc_cnt;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003826 uint8_t pn_port_phy_type;
3827 uint8_t reserved[3];
3828 } ls_err_desc;
3829
3830 /* Port name description with diag param */
3831 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003832 __be32 desc_tag;
3833 __be32 desc_len;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003834 uint8_t WWNN[WWN_SIZE];
3835 uint8_t WWPN[WWN_SIZE];
3836 } port_name_diag_desc;
3837
3838 /* Port Name desc for Direct attached Fx_Port or Nx_Port */
3839 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003840 __be32 desc_tag;
3841 __be32 desc_len;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003842 uint8_t WWNN[WWN_SIZE];
3843 uint8_t WWPN[WWN_SIZE];
3844 } port_name_direct_desc;
3845
3846 /* Buffer Credit descriptor */
3847 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003848 __be32 desc_tag;
3849 __be32 desc_len;
3850 __be32 fcport_b2b;
3851 __be32 attached_fcport_b2b;
3852 __be32 fcport_rtt;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003853 } buffer_credit_desc;
3854
3855 /* Optical Element Data Descriptor */
3856 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003857 __be32 desc_tag;
3858 __be32 desc_len;
3859 __be16 high_alarm;
3860 __be16 low_alarm;
3861 __be16 high_warn;
3862 __be16 low_warn;
3863 __be32 element_flags;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003864 } optical_elmt_desc[5];
3865
3866 /* Optical Product Data Descriptor */
3867 struct {
Bart Van Assche21038b02020-05-18 14:17:11 -07003868 __be32 desc_tag;
3869 __be32 desc_len;
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003870 uint8_t vendor_name[16];
3871 uint8_t part_number[16];
3872 uint8_t serial_number[16];
3873 uint8_t revision[4];
3874 uint8_t date[8];
3875 } optical_prod_desc;
3876};
3877
3878#define RDP_DESC_LEN(obj) \
3879 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3880
3881#define RDP_PORT_SPEED_1GB BIT_15
3882#define RDP_PORT_SPEED_2GB BIT_14
3883#define RDP_PORT_SPEED_4GB BIT_13
3884#define RDP_PORT_SPEED_10GB BIT_12
3885#define RDP_PORT_SPEED_8GB BIT_11
3886#define RDP_PORT_SPEED_16GB BIT_10
3887#define RDP_PORT_SPEED_32GB BIT_9
Joe Carnuccio52bfb082020-02-12 13:44:20 -08003888#define RDP_PORT_SPEED_64GB BIT_8
Joe Carnucciod83a80e2020-02-12 13:44:18 -08003889#define RDP_PORT_SPEED_UNKNOWN BIT_0
3890
Saurav Kashyap0e8cd712014-01-14 20:40:38 -08003891struct scsi_qlt_host {
3892 void *target_lport_ptr;
3893 struct mutex tgt_mutex;
3894 struct mutex tgt_host_action_mutex;
3895 struct qla_tgt *qla_tgt;
3896};
3897
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003898struct qlt_hw_data {
3899 /* Protected by hw lock */
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003900 uint32_t node_name_set:1;
3901
3902 dma_addr_t atio_dma; /* Physical address. */
3903 struct atio *atio_ring; /* Base virtual address */
3904 struct atio *atio_ring_ptr; /* Current address. */
3905 uint16_t atio_ring_index; /* Current index. */
3906 uint16_t atio_q_length;
Bart Van Assche21038b02020-05-18 14:17:11 -07003907 __le32 __iomem *atio_q_in;
3908 __le32 __iomem *atio_q_out;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003909
Bart Van Assche634b9772021-03-20 16:23:54 -07003910 const struct qla_tgt_func_tmpl *tgt_ops;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003911 struct qla_tgt_vp_map *tgt_vp_map;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003912
3913 int saved_set;
Bart Van Assche21038b02020-05-18 14:17:11 -07003914 __le16 saved_exchange_count;
3915 __le32 saved_firmware_options_1;
3916 __le32 saved_firmware_options_2;
3917 __le32 saved_firmware_options_3;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003918 uint8_t saved_firmware_options[2];
3919 uint8_t saved_add_firmware_options[2];
3920
3921 uint8_t tgt_node_name[WWN_SIZE];
Quinn Tran33e79972014-09-25 06:14:55 -04003922
Quinn Tran36c78452016-02-04 11:45:18 -05003923 struct dentry *dfs_tgt_sess;
Himanshu Madhanic4234372017-03-15 09:48:53 -07003924 struct dentry *dfs_tgt_port_database;
Quinn Tran09620eeb2017-06-13 20:47:20 -07003925 struct dentry *dfs_naqp;
Himanshu Madhanic4234372017-03-15 09:48:53 -07003926
Quinn Tran33e79972014-09-25 06:14:55 -04003927 struct list_head q_full_list;
3928 uint32_t num_pend_cmds;
3929 uint32_t num_qfull_cmds_alloc;
3930 uint32_t num_qfull_cmds_dropped;
3931 spinlock_t q_full_lock;
3932 uint32_t leak_exchg_thresh_hold;
Quinn Tran75601512015-12-17 14:57:04 -05003933 spinlock_t sess_lock;
Quinn Tran09620eeb2017-06-13 20:47:20 -07003934 int num_act_qpairs;
3935#define DEFAULT_NAQP 2
Quinn Tran2f424b92015-12-17 14:57:07 -05003936 spinlock_t atio_lock ____cacheline_aligned;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003937};
3938
Quinn Tran33e79972014-09-25 06:14:55 -04003939#define MAX_QFULL_CMDS_ALLOC 8192
3940#define Q_FULL_THRESH_HOLD_PERCENT 90
3941#define Q_FULL_THRESH_HOLD(ha) \
Quinn Tran03e8c682015-12-17 14:56:59 -05003942 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
Quinn Tran33e79972014-09-25 06:14:55 -04003943
3944#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3945
Arun Easicbb01c22020-03-31 03:40:13 -07003946struct qla_hw_data_stat {
3947 u32 num_fw_dump;
3948 u32 num_mpi_reset;
3949};
3950
Quinn Tranf7a0ed472021-03-29 01:52:25 -07003951/* refer to pcie_do_recovery reference */
3952typedef enum {
3953 QLA_PCI_RESUME,
3954 QLA_PCI_ERR_DETECTED,
3955 QLA_PCI_MMIO_ENABLED,
3956 QLA_PCI_SLOT_RESET,
3957} pci_error_state_t;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003958/*
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003959 * Qlogic host adapter specific data structure.
3960*/
3961struct qla_hw_data {
3962 struct pci_dev *pdev;
3963 /* SRB cache. */
3964#define SRB_MIN_REQ 128
3965 mempool_t *srb_mempool;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003966
3967 volatile struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003968 uint32_t mbox_int :1;
3969 uint32_t mbox_busy :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003970 uint32_t disable_risc_code_load :1;
3971 uint32_t enable_64bit_addressing :1;
3972 uint32_t enable_lip_reset :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003973 uint32_t enable_target_reset :1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003974 uint32_t enable_lip_full_login :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003975 uint32_t enable_led_scheme :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08003976
Andrew Vasquez3d716442005-07-06 10:30:26 -07003977 uint32_t msi_enabled :1;
3978 uint32_t msix_enabled :1;
Andrew Vasquezd4c760c2006-06-23 16:10:39 -07003979 uint32_t disable_serdes :1;
Andrew Vasquez4346b142006-12-13 19:20:28 -08003980 uint32_t gpsc_supported :1;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003981 uint32_t npiv_supported :1;
Andrew Vasquez85880802009-12-15 21:29:46 -08003982 uint32_t pci_channel_io_perm_failure :1;
Andrew Vasquezdf613b92008-01-17 09:02:17 -08003983 uint32_t fce_enabled :1;
Joe Carnuccio1d2874d2009-03-24 09:08:06 -07003984 uint32_t fac_supported :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08003985
Lalit Chandivade2533cf62009-03-24 09:08:07 -07003986 uint32_t chip_reset_done :1;
Andrew Vasquezcbc8eb62009-06-03 09:55:17 -07003987 uint32_t running_gold_fw :1;
Andrew Vasquez85880802009-12-15 21:29:46 -08003988 uint32_t eeh_busy :1;
Anirban Chakraborty31557542009-12-02 10:36:55 -08003989 uint32_t disable_msix_handshake :1;
Sarang Radke09ff7012010-03-19 17:03:59 -07003990 uint32_t fcp_prio_enabled :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08003991 uint32_t isp82xx_fw_hung:1;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003992 uint32_t nic_core_hung:1;
Giridhar Malavali71905752011-02-23 15:27:10 -08003993
3994 uint32_t quiesce_owner:1;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003995 uint32_t nic_core_reset_hdlr_active:1;
3996 uint32_t nic_core_reset_owner:1;
Giridhar Malavalib6d0d9d2012-05-15 14:34:25 -04003997 uint32_t isp82xx_no_md_cap:1;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003998 uint32_t host_shutting_down:1;
Chad Dupuisbf5b8ad2012-08-22 14:21:24 -04003999 uint32_t idc_compl_status:1;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004000 uint32_t mr_reset_hdlr_active:1;
4001 uint32_t mr_intr_valid:1;
Himanshu Madhanib0d6cab2015-12-17 14:56:56 -05004002
Joe Carnuccio40f38622016-07-06 11:14:28 -04004003 uint32_t dport_enabled:1;
Himanshu Madhani2486c622014-09-25 05:17:00 -04004004 uint32_t fawwpn_enabled:1;
Himanshu Madhanib0d6cab2015-12-17 14:56:56 -05004005 uint32_t exlogins_enabled:1;
Himanshu Madhani2f56a7f2015-12-17 14:56:57 -05004006 uint32_t exchoffld_enabled:1;
Quinn Tran15f30a52017-03-15 09:48:52 -07004007
Quinn Tranec7193e2017-03-15 09:48:55 -07004008 uint32_t lip_ae:1;
4009 uint32_t n2n_ae:1;
Quinn Tran15f30a52017-03-15 09:48:52 -07004010 uint32_t fw_started:1;
Quinn Tranec7193e2017-03-15 09:48:55 -07004011 uint32_t fw_init_done:1;
Quinn Trane4e3a2c2017-08-23 15:05:07 -07004012
Andrew Vasquezb0f18ee2020-02-26 14:40:13 -08004013 uint32_t lr_detected:1;
4014
Quinn Tran9cd883f2017-12-28 12:33:24 -08004015 uint32_t rida_fmt2:1;
Quinn Tranb2000802018-08-02 13:16:52 -07004016 uint32_t purge_mbox:1;
Quinn Tran8777e432018-08-02 13:16:57 -07004017 uint32_t n2n_bigger:1;
Michael Hernandez3f006ac2019-03-12 11:08:22 -07004018 uint32_t secure_adapter:1;
4019 uint32_t secure_fw:1;
Shyam Sundar9f2475f2020-06-30 03:22:29 -07004020 /* Supported by Adapter */
4021 uint32_t scm_supported_a:1;
4022 /* Supported by Firmware */
4023 uint32_t scm_supported_f:1;
4024 /* Enabled in Driver */
4025 uint32_t scm_enabled:1;
Quinn Trand07b75b2021-08-16 22:13:06 -07004026 uint32_t edif_hw:1;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07004027 uint32_t edif_enabled:1;
Quinn Tran4de067e2021-08-16 22:13:08 -07004028 uint32_t n2n_fw_acc_sec:1;
Quinn Tran44f5a372020-09-29 03:21:47 -07004029 uint32_t plogi_template_valid:1;
Saurav Kashyapdbf1f532021-01-11 01:31:28 -08004030 uint32_t port_isolated:1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004031 } flags;
4032
Quinn Trand1e36352017-12-28 12:33:12 -08004033 uint16_t max_exchg;
Andrew Vasquezb0f18ee2020-02-26 14:40:13 -08004034 uint16_t lr_distance; /* 32G & above */
Quinn Trane4e3a2c2017-08-23 15:05:07 -07004035#define LR_DISTANCE_5K 1
4036#define LR_DISTANCE_10K 0
4037
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07004038 /* This spinlock is used to protect "io transactions", you must
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004039 * acquire it before doing any IO to the card, eg with RD_REG*() and
4040 * WRT_REG*() for the duration of your entire commandtransaction.
4041 *
4042 * This spinlock is of lower priority than the io request lock.
4043 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004044
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004045 spinlock_t hardware_lock ____cacheline_aligned;
Andrew Vasquez285d0322007-10-19 15:59:17 -07004046 int bars;
Benjamin Herrenschmidt09483912007-12-20 15:28:09 +11004047 int mem_only;
Chad Dupuisf73cb692014-02-26 04:15:06 -05004048 device_reg_t *iobase; /* Base I/O address */
Andrew Vasquez37765412008-01-17 09:02:09 -08004049 resource_size_t pio_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004050
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004051#define MIN_IOBASE_LEN 0x100
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004052 dma_addr_t bar0_hdl;
4053
4054 void __iomem *cregbase;
4055 dma_addr_t bar2_hdl;
4056#define BAR0_LEN_FX00 (1024 * 1024)
4057#define BAR2_LEN_FX00 (128 * 1024)
4058
4059 uint32_t rqstq_intr_code;
4060 uint32_t mbx_intr_code;
4061 uint32_t req_que_len;
4062 uint32_t rsp_que_len;
4063 uint32_t req_que_off;
4064 uint32_t rsp_que_off;
4065
4066 /* Multi queue data structs */
Chad Dupuisf73cb692014-02-26 04:15:06 -05004067 device_reg_t *mqiobase;
4068 device_reg_t *msixbase;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08004069 uint16_t msix_count;
4070 uint8_t mqenable;
4071 struct req_que **req_q_map;
4072 struct rsp_que **rsp_q_map;
Michael Hernandezd7459522016-12-12 14:40:07 -08004073 struct qla_qpair **queue_pair_map;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08004074 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4075 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
Michael Hernandezd7459522016-12-12 14:40:07 -08004076 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
4077 / sizeof(unsigned long)];
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07004078 uint8_t max_req_queues;
4079 uint8_t max_rsp_queues;
Michael Hernandezd7459522016-12-12 14:40:07 -08004080 uint8_t max_qpairs;
Sawan Chandakb95b9452017-05-24 18:06:20 -07004081 uint8_t num_qpairs;
Michael Hernandezd7459522016-12-12 14:40:07 -08004082 struct qla_qpair *base_qpair;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08004083 struct qla_npiv_entry *npiv_info;
4084 uint16_t nvram_npiv_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004085
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004086 uint16_t switch_cap;
4087#define FLOGI_SEQ_DEL BIT_8
4088#define FLOGI_MID_SUPPORT BIT_10
4089#define FLOGI_VSAN_SUPPORT BIT_12
4090#define FLOGI_SP_SUPPORT BIT_13
Anirban Chakrabortye5b68a62009-04-06 22:33:50 -07004091
4092 uint8_t port_no; /* Physical port of adapter */
Quinn Tranead03852017-01-19 22:28:01 -08004093 uint8_t exch_starvation;
Anirban Chakrabortye5b68a62009-04-06 22:33:50 -07004094
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004095 /* Timeout timers. */
4096 uint8_t loop_down_abort_time; /* port down timer */
4097 atomic_t loop_down_timer; /* loop down timer */
4098 uint8_t link_down_timeout; /* link down timeout */
4099 uint16_t max_loop_id;
Chad Dupuis642ef982012-02-09 11:15:57 -08004100 uint16_t max_fibre_devices; /* Maximum number of targets */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07004101
Linus Torvalds1da177e2005-04-16 15:20:36 -07004102 uint16_t fb_rev;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004103 uint16_t min_external_loopid; /* First external loop Id */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004104
Andrew Vasquezd8b45212006-10-02 12:00:43 -07004105#define PORT_SPEED_UNKNOWN 0xFFFF
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004106#define PORT_SPEED_1GB 0x00
4107#define PORT_SPEED_2GB 0x01
Anil Gurumurthy4910b522019-02-15 14:37:17 -08004108#define PORT_SPEED_AUTO 0x02
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004109#define PORT_SPEED_4GB 0x03
4110#define PORT_SPEED_8GB 0x04
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004111#define PORT_SPEED_16GB 0x05
Chad Dupuisf73cb692014-02-26 04:15:06 -05004112#define PORT_SPEED_32GB 0x06
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004113#define PORT_SPEED_64GB 0x07
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004114#define PORT_SPEED_10GB 0x13
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004115 uint16_t link_data_rate; /* F/W operating speed */
Anil Gurumurthy4910b522019-02-15 14:37:17 -08004116 uint16_t set_data_rate; /* Set by user */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004117
4118 uint8_t current_topology;
4119 uint8_t prev_topology;
4120#define ISP_CFG_NL 1
4121#define ISP_CFG_N 2
4122#define ISP_CFG_FL 4
4123#define ISP_CFG_F 8
4124
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004125 uint8_t operating_mode; /* F/W operating mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004126#define LOOP 0
4127#define P2P 1
4128#define LOOP_P2P 2
4129#define P2P_LOOP 3
Linus Torvalds1da177e2005-04-16 15:20:36 -07004130 uint8_t interrupts_on;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004131 uint32_t isp_abort_cnt;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004132#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4133#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004134#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004135#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4136#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
Chad Dupuisf73cb692014-02-26 04:15:06 -05004137#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04004138#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
Sawan Chandak2b489922015-08-04 13:38:03 -04004139#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004140#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4141#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4142#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4143#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4144#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04004145
Joe Carnuccio9e052e22016-07-06 11:14:31 -04004146 uint32_t isp_type;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004147#define DT_ISP2100 BIT_0
4148#define DT_ISP2200 BIT_1
4149#define DT_ISP2300 BIT_2
4150#define DT_ISP2312 BIT_3
4151#define DT_ISP2322 BIT_4
4152#define DT_ISP6312 BIT_5
4153#define DT_ISP6322 BIT_6
4154#define DT_ISP2422 BIT_7
4155#define DT_ISP2432 BIT_8
4156#define DT_ISP5422 BIT_9
4157#define DT_ISP5432 BIT_10
4158#define DT_ISP2532 BIT_11
4159#define DT_ISP8432 BIT_12
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004160#define DT_ISP8001 BIT_13
Giridhar Malavalia9083012010-04-12 17:59:55 -07004161#define DT_ISP8021 BIT_14
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004162#define DT_ISP2031 BIT_15
4163#define DT_ISP8031 BIT_16
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004164#define DT_ISPFX00 BIT_17
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004165#define DT_ISP8044 BIT_18
Chad Dupuisf73cb692014-02-26 04:15:06 -05004166#define DT_ISP2071 BIT_19
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04004167#define DT_ISP2271 BIT_20
Sawan Chandak2b489922015-08-04 13:38:03 -04004168#define DT_ISP2261 BIT_21
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004169#define DT_ISP2061 BIT_22
4170#define DT_ISP2081 BIT_23
4171#define DT_ISP2089 BIT_24
4172#define DT_ISP2281 BIT_25
4173#define DT_ISP2289 BIT_26
4174#define DT_ISP_LAST (DT_ISP2289 << 1)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004175
Joe Carnuccio9e052e22016-07-06 11:14:31 -04004176 uint32_t device_type;
Arun Easie02587d2011-08-16 11:29:23 -07004177#define DT_T10_PI BIT_25
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004178#define DT_IIDMA BIT_26
4179#define DT_FWI2 BIT_27
4180#define DT_ZIO_SUPPORTED BIT_28
4181#define DT_OEM_001 BIT_29
4182#define DT_ISP2200A BIT_30
4183#define DT_EXTENDED_IDS BIT_31
Joe Carnuccio9e052e22016-07-06 11:14:31 -04004184
4185#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004186#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4187#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4188#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4189#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4190#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4191#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4192#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4193#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4194#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4195#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4196#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4197#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4198#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004199#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004200#define IS_QLA81XX(ha) (IS_QLA8001(ha))
Giridhar Malavalia9083012010-04-12 17:59:55 -07004201#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004202#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004203#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4204#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004205#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
Chad Dupuisf73cb692014-02-26 04:15:06 -05004206#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04004207#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
Sawan Chandak2b489922015-08-04 13:38:03 -04004208#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004209#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4210#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004211
4212#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4213 IS_QLA6312(ha) || IS_QLA6322(ha))
4214#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4215#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4216#define IS_QLA25XX(ha) (IS_QLA2532(ha))
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004217#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004218#define IS_QLA84XX(ha) (IS_QLA8432(ha))
Sawan Chandak2b489922015-08-04 13:38:03 -04004219#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004220#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004221#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4222 IS_QLA84XX(ha))
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004223#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004224 IS_QLA8031(ha) || IS_QLA8044(ha))
4225#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004226#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
Giridhar Malavalia9083012010-04-12 17:59:55 -07004227 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004228 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004229 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4230 IS_QLA28XX(ha))
Himanshu Madhanifd564b52015-04-09 15:00:04 -04004231#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004232 IS_QLA27XX(ha) || IS_QLA28XX(ha))
Giridhar Malavalib77ed252014-02-26 04:15:12 -05004233#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
Chad Dupuisf73cb692014-02-26 04:15:06 -05004234#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004235 IS_QLA27XX(ha) || IS_QLA28XX(ha))
Chad Dupuisf73cb692014-02-26 04:15:06 -05004236#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004237 IS_QLA27XX(ha) || IS_QLA28XX(ha))
Andrew Vasquezac280b62009-08-20 11:06:05 -07004238#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004239
Arun Easie02587d2011-08-16 11:29:23 -07004240#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004241#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4242#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4243#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4244#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4245#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004246#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
Chad Dupuisf73cb692014-02-26 04:15:06 -05004247#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004248 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4249#define IS_BIDI_CAPABLE(ha) \
4250 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
Saurav Kashyap81178772012-08-22 14:21:04 -04004251/* Bit 21 of fw_attributes decides the MCTP capabilities */
4252#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4253 ((ha)->fw_attributes_ext[0] & BIT_0))
Bikash Hazarikaa0465852021-01-11 01:31:31 -08004254#define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
4255#define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4256#define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4257#define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
4258#define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
4259 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4260#define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
4261 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4262#define QLA_ABTS_WAIT_ENABLED(_sp) \
4263 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4264
Himanshu Madhanib20f02e2015-06-10 11:05:18 -04004265#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4266#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
Arun Easi9e522cd2012-08-22 14:21:31 -04004267#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004268#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4269 IS_QLA28XX(ha))
Arun Easi9e522cd2012-08-22 14:21:31 -04004270#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4271 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004272#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4273 IS_QLA28XX(ha))
Arun Easi33c36c02013-01-30 03:34:41 -05004274#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004275#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4276#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4277 IS_QLA28XX(ha))
4278#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4279 IS_QLA28XX(ha))
Quinn Tran99e1b682017-06-02 09:12:03 -07004280#define IS_EXCHG_OFFLD_CAPABLE(ha) \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004281 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
Quinn Tran99e1b682017-06-02 09:12:03 -07004282#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004283 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4284 IS_QLA27XX(ha) || IS_QLA28XX(ha))
Quinn Trana4239942017-12-28 12:33:26 -08004285#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
Joe Carnuccioecc89f22019-03-12 11:08:13 -07004286 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004287
Quinn Tran49db4d42020-09-03 21:51:22 -07004288#define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4289 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4290 (ha->zio_mode == QLA_ZIO_MODE_6))
4291
Linus Torvalds1da177e2005-04-16 15:20:36 -07004292 /* HBA serial number */
4293 uint8_t serial0;
4294 uint8_t serial1;
4295 uint8_t serial2;
4296
4297 /* NVRAM configuration data */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004298#define MAX_NVRAM_SIZE 4096
Bart Van Asschec1c71782019-08-08 20:01:24 -07004299#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
Andrew Vasquez3d716442005-07-06 10:30:26 -07004300 uint16_t nvram_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004301 uint16_t nvram_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07004302 void *nvram;
andrew.vasquez@qlogic.com6f641792006-03-09 14:27:34 -08004303 uint16_t vpd_size;
4304 uint16_t vpd_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07004305 void *vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004306
4307 uint16_t loop_reset_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004308 uint8_t retry_count;
4309 uint8_t login_timeout;
4310 uint16_t r_a_tov;
4311 int port_down_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004312 uint8_t mbx_count;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004313 uint8_t aen_mbx_count;
Quinn Tranb2000802018-08-02 13:16:52 -07004314 atomic_t num_pend_mbx_stage1;
4315 atomic_t num_pend_mbx_stage2;
4316 atomic_t num_pend_mbx_stage3;
Quinn Tran0eaaca42018-08-02 13:16:56 -07004317 uint16_t frame_payload_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004318
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004319 uint32_t login_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004320 /* SNS command interfaces. */
4321 ms_iocb_entry_t *ms_iocb;
4322 dma_addr_t ms_iocb_dma;
4323 struct ct_sns_pkt *ct_sns;
4324 dma_addr_t ct_sns_dma;
4325 /* SNS command interfaces for 2200. */
4326 struct sns_cmd_pkt *sns_cmd;
4327 dma_addr_t sns_cmd_dma;
4328
Quinn Trane4e3a2c2017-08-23 15:05:07 -07004329#define SFP_DEV_SIZE 512
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004330#define SFP_BLOCK_SIZE 64
Joe Carnucciod83a80e2020-02-12 13:44:18 -08004331#define SFP_RTDI_LEN SFP_BLOCK_SIZE
4332
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004333 void *sfp_data;
4334 dma_addr_t sfp_data_dma;
Andrew Vasquez88729e52006-06-23 16:10:50 -07004335
Bart Van Asschea27747a2019-12-18 16:47:06 -08004336 struct qla_flt_header *flt;
Michael Hernandez3f006ac2019-03-12 11:08:22 -07004337 dma_addr_t flt_dma;
4338
Giridhar Malavalib5d03292009-10-13 15:16:48 -07004339#define XGMAC_DATA_SIZE 4096
Andrew Vasquezce0423f2009-06-03 09:55:13 -07004340 void *xgmac_data;
4341 dma_addr_t xgmac_data_dma;
4342
Giridhar Malavalib5d03292009-10-13 15:16:48 -07004343#define DCBX_TLV_DATA_SIZE 4096
Andrew Vasquez11bbc1d2009-06-03 09:55:14 -07004344 void *dcbx_tlv;
4345 dma_addr_t dcbx_tlv_dma;
4346
Christoph Hellwig39a11242006-02-14 18:46:22 +01004347 struct task_struct *dpc_thread;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004348 uint8_t dpc_active; /* DPC routine is active */
4349
Linus Torvalds1da177e2005-04-16 15:20:36 -07004350 dma_addr_t gid_list_dma;
4351 struct gid_list_info *gid_list;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07004352 int gid_list_info_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004353
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07004354 /* Small DMA pool allocations -- maximum 256 bytes in length. */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004355#define DMA_POOL_SIZE 256
Linus Torvalds1da177e2005-04-16 15:20:36 -07004356 struct dma_pool *s_dma_pool;
4357
4358 dma_addr_t init_cb_dma;
Andrew Vasquez3d716442005-07-06 10:30:26 -07004359 init_cb_t *init_cb;
4360 int init_cb_size;
Andrew Vasquezb64b0e82009-03-24 09:08:01 -07004361 dma_addr_t ex_init_cb_dma;
4362 struct ex_init_cb_81xx *ex_init_cb;
Shyam Sundar9f2475f2020-06-30 03:22:29 -07004363 dma_addr_t sf_init_cb_dma;
4364 struct init_sf_cb *sf_init_cb;
4365
4366 void *scm_fpin_els_buff;
4367 uint64_t scm_fpin_els_buff_size;
4368 bool scm_fpin_valid;
4369 bool scm_fpin_payload_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004370
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07004371 void *async_pd;
4372 dma_addr_t async_pd_dma;
4373
Himanshu Madhanib0d6cab2015-12-17 14:56:56 -05004374#define ENABLE_EXTENDED_LOGIN BIT_7
4375
4376 /* Extended Logins */
4377 void *exlogin_buf;
4378 dma_addr_t exlogin_buf_dma;
Quinn Trand38cb842020-09-03 21:51:21 -07004379 uint32_t exlogin_size;
Himanshu Madhanib0d6cab2015-12-17 14:56:56 -05004380
Himanshu Madhani2f56a7f2015-12-17 14:56:57 -05004381#define ENABLE_EXCHANGE_OFFLD BIT_2
4382
4383 /* Exchange Offload */
4384 void *exchoffld_buf;
4385 dma_addr_t exchoffld_buf_dma;
4386 int exchoffld_size;
4387 int exchoffld_count;
4388
Quinn Tran8777e432018-08-02 13:16:57 -07004389 /* n2n */
Quinn Tran44f5a372020-09-29 03:21:47 -07004390 struct fc_els_flogi plogi_els_payld;
4391#define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
Quinn Tran8777e432018-08-02 13:16:57 -07004392
Quinn Trana4239942017-12-28 12:33:26 -08004393 void *swl;
Andrew Vasquez7a677352012-02-09 11:15:56 -08004394
Linus Torvalds1da177e2005-04-16 15:20:36 -07004395 /* These are used by mailbox operations. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004396 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4397 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4398 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004399
4400 mbx_cmd_t *mcp;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004401 struct mbx_cmd_32 *mcp32;
4402
Linus Torvalds1da177e2005-04-16 15:20:36 -07004403 unsigned long mbx_cmd_flags;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004404#define MBX_INTERRUPT 1
4405#define MBX_INTR_WAIT 2
Linus Torvalds1da177e2005-04-16 15:20:36 -07004406#define MBX_UPDATE_FLASH_ACTIVE 3
4407
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004408 struct mutex vport_lock; /* Virtual port synchronization */
Arun Easifeafb7b2010-09-03 14:57:00 -07004409 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
Michael Hernandezd7459522016-12-12 14:40:07 -08004410 struct mutex mq_lock; /* multi-queue synchronization */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004411 struct completion mbx_cmd_comp; /* Serialize mbx access */
Marcus Barrow0b05a1f2008-01-17 09:02:13 -08004412 struct completion mbx_intr_comp; /* Used for completion notification */
Sarang Radke23f2ebd2010-05-28 15:08:21 -07004413 struct completion dcbx_comp; /* For set port config notification */
Chad Dupuisf356bef2013-02-08 01:58:04 -05004414 struct completion lb_portup_comp; /* Used to wait for link up during
4415 * loopback */
4416#define DCBX_COMP_TIMEOUT 20
4417#define LB_PORTUP_COMP_TIMEOUT 10
4418
Sarang Radke23f2ebd2010-05-28 15:08:21 -07004419 int notify_dcbx_comp;
Chad Dupuisf356bef2013-02-08 01:58:04 -05004420 int notify_lb_portup_comp;
Saurav Kashyapa9b6f722012-08-22 14:21:01 -04004421 struct mutex selflogin_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004422
Linus Torvalds1da177e2005-04-16 15:20:36 -07004423 /* Basic firmware related information. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004424 uint16_t fw_major_version;
4425 uint16_t fw_minor_version;
4426 uint16_t fw_subminor_version;
4427 uint16_t fw_attributes;
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004428 uint16_t fw_attributes_h;
Darren Trapp03aaa892019-02-15 14:37:13 -08004429#define FW_ATTR_H_NVME_FBURST BIT_1
Giridhar Malavali171e4902019-01-30 09:50:44 -08004430#define FW_ATTR_H_NVME BIT_10
4431#define FW_ATTR_H_NVME_UPDATED BIT_14
4432
Shyam Sundar9f2475f2020-06-30 03:22:29 -07004433 /* About firmware SCM support */
4434#define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4435 /* Brocade fabric attached */
4436#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4437 /* Cisco fabric attached */
4438#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
Saurav Kashyapcf3c54f2020-09-03 21:51:27 -07004439#define FW_ATTR_EXT0_NVME2 BIT_13
Quinn Trand07b75b2021-08-16 22:13:06 -07004440#define FW_ATTR_EXT0_EDIF BIT_5
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08004441 uint16_t fw_attributes_ext[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004442 uint32_t fw_memory_size;
4443 uint32_t fw_transfer_size;
Andrew Vasquez441d1072006-05-17 15:09:34 -07004444 uint32_t fw_srisc_address;
4445#define RISC_START_ADDRESS_2100 0x1000
4446#define RISC_START_ADDRESS_2300 0x800
4447#define RISC_START_ADDRESS_2400 0x100000
Quinn Tran03e8c682015-12-17 14:56:59 -05004448
4449 uint16_t orig_fw_tgt_xcb_count;
4450 uint16_t cur_fw_tgt_xcb_count;
4451 uint16_t orig_fw_xcb_count;
4452 uint16_t cur_fw_xcb_count;
4453 uint16_t orig_fw_iocb_count;
4454 uint16_t cur_fw_iocb_count;
4455 uint16_t fw_max_fcf_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004456
Chad Dupuisf73cb692014-02-26 04:15:06 -05004457 uint32_t fw_shared_ram_start;
4458 uint32_t fw_shared_ram_end;
Joe Carnuccioad1ef172016-07-06 11:14:18 -04004459 uint32_t fw_ddr_ram_start;
4460 uint32_t fw_ddr_ram_end;
Chad Dupuisf73cb692014-02-26 04:15:06 -05004461
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004462 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004463 uint8_t fw_seriallink_options[4];
Bart Van Assche21038b02020-05-18 14:17:11 -07004464 __le16 fw_seriallink_options24[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004465
Joe Carnuccio2a3192a2019-03-12 11:08:14 -07004466 uint8_t serdes_version[3];
Andrew Vasquez55a96152009-03-24 09:08:03 -07004467 uint8_t mpi_version[3];
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004468 uint32_t mpi_capabilities;
Andrew Vasquez55a96152009-03-24 09:08:03 -07004469 uint8_t phy_version[3];
Sawan Chandak03aa8682015-08-04 13:37:59 -04004470 uint8_t pep_version[3];
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004471
Chad Dupuisf73cb692014-02-26 04:15:06 -05004472 /* Firmware dump template */
Joe Carnuccioa28d9e42019-03-12 11:08:17 -07004473 struct fwdt {
4474 void *template;
4475 ulong length;
4476 ulong dump_size;
4477 } fwdt[2];
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07004478 struct qla2xxx_fw_dump *fw_dump;
4479 uint32_t fw_dump_len;
Quinn Trana4226ec2019-04-02 14:24:27 -07004480 u32 fw_dump_alloc_len;
Joe Carnuccio2a3192a2019-03-12 11:08:14 -07004481 bool fw_dumped;
Hiral Patel61f098d2014-04-11 16:54:21 -04004482 unsigned long fw_dump_cap_flags;
4483#define RISC_PAUSE_CMPL 0
4484#define DMA_SHUTDOWN_CMPL 1
4485#define ISP_RESET_CMPL 2
4486#define RISC_RDY_AFT_RESET 3
4487#define RISC_SRAM_DUMP_CMPL 4
4488#define RISC_EXT_MEM_DUMP_CMPL 5
Himanshu Madhanid14e72f2015-04-09 15:00:03 -04004489#define ISP_MBX_RDY 6
4490#define ISP_SOFT_RESET_CMPL 7
Linus Torvalds1da177e2005-04-16 15:20:36 -07004491 int fw_dump_reading;
Arun Easicbb01c22020-03-31 03:40:13 -07004492 void *mpi_fw_dump;
4493 u32 mpi_fw_dump_len;
Colin Ian King78b874b2020-04-28 11:20:13 +01004494 unsigned int mpi_fw_dump_reading:1;
4495 unsigned int mpi_fw_dumped:1;
Saurav Kashyapedaa5c72014-04-11 16:54:14 -04004496 int prev_minidump_failed;
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07004497 dma_addr_t eft_dma;
4498 void *eft;
Saurav Kashyap81178772012-08-22 14:21:04 -04004499/* Current size of mctp dump is 0x086064 bytes */
4500#define MCTP_DUMP_SIZE 0x086064
4501 dma_addr_t mctp_dump_dma;
4502 void *mctp_dump;
4503 int mctp_dumped;
4504 int mctp_dump_reading;
Andrew Vasquezbb99de62009-01-05 11:18:08 -08004505 uint32_t chain_offset;
Andrew Vasquezdf613b92008-01-17 09:02:17 -08004506 struct dentry *dfs_dir;
4507 struct dentry *dfs_fce;
Himanshu Madhanice1025c2015-12-17 14:56:58 -05004508 struct dentry *dfs_tgt_counters;
Quinn Tran03e8c682015-12-17 14:56:59 -05004509 struct dentry *dfs_fw_resource_cnt;
Himanshu Madhanice1025c2015-12-17 14:56:58 -05004510
Andrew Vasquezdf613b92008-01-17 09:02:17 -08004511 dma_addr_t fce_dma;
4512 void *fce;
4513 uint32_t fce_bufs;
4514 uint16_t fce_mb[8];
4515 uint64_t fce_wr, fce_rd;
4516 struct mutex fce_mutex;
4517
Andrew Vasquez3d716442005-07-06 10:30:26 -07004518 uint32_t pci_attr;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08004519 uint16_t chip_revision;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004520
4521 uint16_t product_id[4];
4522
4523 uint8_t model_number[16+1];
Joe Carnuccio1ee27142008-07-10 16:55:53 -07004524 char model_desc[80];
Andrew Vasquezcca53352005-08-26 19:08:30 -07004525 uint8_t adapter_id[16+1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004526
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08004527 /* Option ROM information. */
4528 char *optrom_buffer;
4529 uint32_t optrom_size;
4530 int optrom_state;
4531#define QLA_SWAITING 0
4532#define QLA_SREADING 1
4533#define QLA_SWRITING 2
Joe Carnucciob7cc1762007-09-20 14:07:35 -07004534 uint32_t optrom_region_start;
4535 uint32_t optrom_region_size;
Chad Dupuis7a8ab9c2014-02-26 04:14:56 -05004536 struct mutex optrom_mutex;
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08004537
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004538/* PCI expansion ROM image information. */
Andrew Vasquez30c47662007-01-29 10:22:21 -08004539#define ROM_CODE_TYPE_BIOS 0
4540#define ROM_CODE_TYPE_FCODE 1
4541#define ROM_CODE_TYPE_EFI 3
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004542 uint8_t bios_revision[2];
4543 uint8_t efi_revision[2];
4544 uint8_t fcode_revision[16];
Andrew Vasquez30c47662007-01-29 10:22:21 -08004545 uint32_t fw_revision[4];
4546
Madhuranath Iyengar0f2d9622010-07-23 15:28:26 +05004547 uint32_t gold_fw_version[4];
4548
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08004549 /* Offsets for flash/nvram access (set to ~0 if not used). */
4550 uint32_t flash_conf_off;
4551 uint32_t flash_data_off;
4552 uint32_t nvram_conf_off;
4553 uint32_t nvram_data_off;
4554
Andrew Vasquez7d232c72008-04-03 13:13:22 -07004555 uint32_t fdt_wrt_disable;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004556 uint32_t fdt_wrt_enable;
Andrew Vasquez7d232c72008-04-03 13:13:22 -07004557 uint32_t fdt_erase_cmd;
4558 uint32_t fdt_block_size;
4559 uint32_t fdt_unprotect_sec_cmd;
4560 uint32_t fdt_protect_sec_cmd;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004561 uint32_t fdt_wrt_sts_reg_cmd;
Andrew Vasquez7d232c72008-04-03 13:13:22 -07004562
Joe Carnuccio5fa87742019-03-12 11:08:21 -07004563 struct {
4564 uint32_t flt_region_flt;
4565 uint32_t flt_region_fdt;
4566 uint32_t flt_region_boot;
4567 uint32_t flt_region_boot_sec;
4568 uint32_t flt_region_fw;
4569 uint32_t flt_region_fw_sec;
4570 uint32_t flt_region_vpd_nvram;
4571 uint32_t flt_region_vpd_nvram_sec;
4572 uint32_t flt_region_vpd;
4573 uint32_t flt_region_vpd_sec;
4574 uint32_t flt_region_nvram;
4575 uint32_t flt_region_nvram_sec;
4576 uint32_t flt_region_npiv_conf;
4577 uint32_t flt_region_gold_fw;
4578 uint32_t flt_region_fcp_prio;
4579 uint32_t flt_region_bootload;
4580 uint32_t flt_region_img_status_pri;
4581 uint32_t flt_region_img_status_sec;
4582 uint32_t flt_region_aux_img_status_pri;
4583 uint32_t flt_region_aux_img_status_sec;
4584 };
Sawan Chandak4243c112016-01-27 12:03:31 -05004585 uint8_t active_image;
Andrew Vasquezc00d8992008-09-11 21:22:49 -07004586
Linus Torvalds1da177e2005-04-16 15:20:36 -07004587 /* Needed for BEACON */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004588 uint16_t beacon_blink_led;
4589 uint8_t beacon_color_state;
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08004590#define QLA_LED_GRN_ON 0x01
4591#define QLA_LED_YLW_ON 0x02
4592#define QLA_LED_ABR_ON 0x04
4593#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4594 /* ISP2322: red, green, amber. */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004595 uint16_t zio_mode;
4596 uint16_t zio_timer;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08004597
Anirban Chakraborty73208df2008-12-09 16:45:39 -08004598 struct qla_msix_entry *msix_entries;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004599
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004600 struct list_head vp_list; /* list of VP */
4601 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4602 sizeof(unsigned long)];
4603 uint16_t num_vhosts; /* number of vports created */
4604 uint16_t num_vsans; /* number of vsan created */
4605 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4606 int cur_vport_count;
4607
4608 struct qla_chip_state_84xx *cs84xx;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004609 struct isp_operations *isp_ops;
Anirban Chakraborty68ca9492009-04-06 22:33:41 -07004610 struct workqueue_struct *wq;
Manish Rangankar3a4e1f32021-09-08 09:46:20 -07004611 struct work_struct heartbeat_work;
Giridhar Malavali9a069e12010-01-12 13:02:47 -08004612 struct qlfc_fw fw_buf;
Sarang Radke09ff7012010-03-19 17:03:59 -07004613
4614 /* FCP_CMND priority support */
4615 struct qla_fcp_prio_cfg *fcp_prio_cfg;
Giridhar Malavalia9083012010-04-12 17:59:55 -07004616
4617 struct dma_pool *dl_dma_pool;
4618#define DSD_LIST_DMA_POOL_SIZE 512
4619
4620 struct dma_pool *fcp_cmnd_dma_pool;
4621 mempool_t *ctx_mempool;
4622#define FCP_CMND_DMA_POOL_SIZE 512
4623
Bart Van Assche8dfa4b5a2015-07-09 07:24:50 -07004624 void __iomem *nx_pcibase; /* Base I/O address */
4625 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4626 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
Giridhar Malavalia9083012010-04-12 17:59:55 -07004627
4628 uint32_t crb_win;
4629 uint32_t curr_window;
4630 uint32_t ddr_mn_window;
4631 unsigned long mn_win_crb;
4632 unsigned long ms_win_crb;
4633 int qdr_sn_window;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04004634 uint32_t fcoe_dev_init_timeout;
4635 uint32_t fcoe_reset_timeout;
Giridhar Malavalia9083012010-04-12 17:59:55 -07004636 rwlock_t hw_lock;
4637 uint16_t portnum; /* port number */
4638 int link_width;
4639 struct fw_blob *hablob;
4640 struct qla82xx_legacy_intr_set nx_legacy_intr;
4641
4642 uint16_t gbl_dsd_inuse;
4643 uint16_t gbl_dsd_avail;
4644 struct list_head gbl_dsd_list;
4645#define NUM_DSD_CHAIN 4096
Harish Zunjarrao9c2b2972010-05-28 15:08:23 -07004646
4647 uint8_t fw_type;
Bart Van Assche21038b02020-05-18 14:17:11 -07004648 uint32_t file_prd_off; /* File firmware product offset */
Giridhar Malavali08de2842011-08-16 11:31:44 -07004649
4650 uint32_t md_template_size;
4651 void *md_tmplt_hdr;
4652 dma_addr_t md_tmplt_hdr_dma;
4653 void *md_dump;
4654 uint32_t md_dump_size;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04004655
Chad Dupuis5f16b332012-08-22 14:21:00 -04004656 void *loop_id_map;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04004657
4658 /* QLA83XX IDC specific fields */
4659 uint32_t idc_audit_ts;
Santosh Vernekar454073c2013-08-27 01:37:48 -04004660 uint32_t idc_extend_tmo;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04004661
4662 /* DPC low-priority workqueue */
4663 struct workqueue_struct *dpc_lp_wq;
4664 struct work_struct idc_aen;
4665 /* DPC high-priority workqueue */
4666 struct workqueue_struct *dpc_hp_wq;
4667 struct work_struct nic_core_reset;
4668 struct work_struct idc_state_handler;
4669 struct work_struct nic_core_unrecoverable;
Chad Dupuisf3ddac12013-10-30 03:38:16 -04004670 struct work_struct board_disable;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04004671
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004672 struct mr_data_fx00 mr;
Quinn Tranb2000802018-08-02 13:16:52 -07004673 uint32_t chip_reset;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004674
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04004675 struct qlt_hw_data tgt;
Chad Dupuisa1b23c52014-02-26 04:15:12 -05004676 int allow_cna_fw_dump;
Joe Carnuccio1f4c7c32017-08-23 15:05:17 -07004677 uint32_t fw_ability_mask;
Joe Carnuccio72a92df2019-03-12 11:08:15 -07004678 uint16_t min_supported_speed;
4679 uint16_t max_supported_speed;
Duane Grigsbydeeae7a2017-07-21 09:32:25 -07004680
Giridhar Malavali50b81272018-12-21 09:33:45 -08004681 /* DMA pool for the DIF bundling buffers */
4682 struct dma_pool *dif_bundl_pool;
4683 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4684 struct {
4685 struct {
4686 struct list_head head;
4687 uint count;
4688 } good;
4689 struct {
4690 struct list_head head;
4691 uint count;
4692 } unusable;
4693 } pool;
4694
4695 unsigned long long dif_bundle_crossed_pages;
4696 unsigned long long dif_bundle_reads;
4697 unsigned long long dif_bundle_writes;
4698 unsigned long long dif_bundle_kallocs;
4699 unsigned long long dif_bundle_dma_allocs;
4700
Duane Grigsbydeeae7a2017-07-21 09:32:25 -07004701 atomic_t nvme_active_aen_cnt;
4702 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
Quinn Tran8b4673b2018-09-04 14:19:14 -07004703
Michael Hernandez84ed3622019-09-12 11:09:12 -07004704 uint8_t fc4_type_priority;
4705
Quinn Tran8b4673b2018-09-04 14:19:14 -07004706 atomic_t zio_threshold;
4707 uint16_t last_zio_threshold;
Joe Carnuccio5fa87742019-03-12 11:08:21 -07004708
Quinn Tran48250342019-01-24 23:23:41 -08004709#define DEFAULT_ZIO_THRESHOLD 5
Arun Easicbb01c22020-03-31 03:40:13 -07004710
4711 struct qla_hw_data_stat stat;
Quinn Tranf7a0ed472021-03-29 01:52:25 -07004712 pci_error_state_t pci_error_state;
Quinn Tran84318a92021-06-23 22:25:58 -07004713 struct dma_pool *purex_dma_pool;
Quinn Tranfac28072021-06-23 22:25:59 -07004714 struct btree_head32 host_map;
Quinn Trandd307062021-06-23 22:26:00 -07004715
4716#define EDIF_NUM_SA_INDEX 512
4717#define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX
4718 void *edif_rx_sa_id_map;
4719 void *edif_tx_sa_id_map;
4720 spinlock_t sadb_fp_lock;
4721
4722 struct list_head sadb_tx_index_list;
4723 struct list_head sadb_rx_index_list;
4724 spinlock_t sadb_lock; /* protects list */
Quinn Tran84318a92021-06-23 22:25:58 -07004725 struct els_reject elsrej;
Quinn Tran4de067e2021-08-16 22:13:08 -07004726 u8 edif_post_stop_cnt_down;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004727};
4728
Quinn Tran84318a92021-06-23 22:25:58 -07004729#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
4730
Joe Carnuccio5fa87742019-03-12 11:08:21 -07004731struct active_regions {
4732 uint8_t global;
4733 struct {
4734 uint8_t board_config;
4735 uint8_t vpd_nvram;
4736 uint8_t npiv_config_0_1;
4737 uint8_t npiv_config_2_3;
4738 } aux;
4739};
4740
Joe Carnuccio1f4c7c32017-08-23 15:05:17 -07004741#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4742#define FW_ABILITY_MAX_SPEED_16G 0x0
4743#define FW_ABILITY_MAX_SPEED_32G 0x1
4744#define FW_ABILITY_MAX_SPEED(ha) \
4745 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4746
Anil Gurumurthy4910b522019-02-15 14:37:17 -08004747#define QLA_GET_DATA_RATE 0
4748#define QLA_SET_DATA_RATE_NOLR 1
4749#define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4750
Shyam Sundar62e9dd12020-06-30 03:22:28 -07004751#define QLA_DEFAULT_PAYLOAD_SIZE 64
4752/*
4753 * This item might be allocated with a size > sizeof(struct purex_item).
4754 * The "size" variable gives the size of the payload (which
4755 * is variable) starting at "iocb".
4756 */
Joe Carnuccio576bfde2020-02-12 13:44:24 -08004757struct purex_item {
4758 struct list_head list;
4759 struct scsi_qla_host *vha;
Shyam Sundar62e9dd12020-06-30 03:22:28 -07004760 void (*process_item)(struct scsi_qla_host *vha,
4761 struct purex_item *pkt);
4762 atomic_t in_use;
4763 uint16_t size;
Joe Carnuccio576bfde2020-02-12 13:44:24 -08004764 struct {
4765 uint8_t iocb[64];
4766 } iocb;
4767};
4768
Quinn Tran7ebb336e2021-06-23 22:25:56 -07004769#include "qla_edif.h"
4770
Shyam Sundar9f2475f2020-06-30 03:22:29 -07004771#define SCM_FLAG_RDF_REJECT 0x00
4772#define SCM_FLAG_RDF_COMPLETED 0x01
4773
4774#define QLA_CON_PRIMITIVE_RECEIVED 0x1
4775#define QLA_CONGESTION_ARB_WARNING 0x1
4776#define QLA_CONGESTION_ARB_ALARM 0X2
4777
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004778/*
4779 * Qlogic scsi host structure
4780 */
4781typedef struct scsi_qla_host {
4782 struct list_head list;
4783 struct list_head vp_fcports; /* list of fcports */
4784 struct list_head work_list;
Andrew Vasquezf999f4c12009-06-03 09:55:28 -07004785 spinlock_t work_lock;
Quinn Tranec7193e2017-03-15 09:48:55 -07004786 struct work_struct iocb_work;
Andrew Vasquezf999f4c12009-06-03 09:55:28 -07004787
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004788 /* Commonly used flags and state information. */
4789 struct Scsi_Host *host;
4790 unsigned long host_no;
4791 uint8_t host_str[16];
4792
4793 volatile struct {
4794 uint32_t init_done :1;
4795 uint32_t online :1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004796 uint32_t reset_active :1;
4797
4798 uint32_t management_server_logged_in :1;
4799 uint32_t process_response_queue :1;
Arun Easibad75002010-05-04 15:01:30 -07004800 uint32_t difdix_supported:1;
Arun Easifeafb7b2010-09-03 14:57:00 -07004801 uint32_t delete_progress:1;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04004802
4803 uint32_t fw_tgt_reported:1;
Sawan Chandak969a6192016-01-27 12:03:32 -05004804 uint32_t bbcr_enable:1;
Michael Hernandezd7459522016-12-12 14:40:07 -08004805 uint32_t qpairs_available:1;
Sawan Chandakd65237c2017-06-13 20:47:19 -07004806 uint32_t qpairs_req_created:1;
4807 uint32_t qpairs_rsp_created:1;
Duane Grigsbya5d42f42017-06-21 13:48:41 -07004808 uint32_t nvme_enabled:1;
Darren Trapp03aaa892019-02-15 14:37:13 -08004809 uint32_t nvme_first_burst:1;
Saurav Kashyapcf3c54f2020-09-03 21:51:27 -07004810 uint32_t nvme2_enabled:1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004811 } flags;
4812
4813 atomic_t loop_state;
4814#define LOOP_TIMEOUT 1
4815#define LOOP_DOWN 2
4816#define LOOP_UP 3
4817#define LOOP_UPDATE 4
4818#define LOOP_READY 5
4819#define LOOP_DEAD 6
4820
Quinn Tran4005a992017-12-04 14:45:06 -08004821 unsigned long relogin_jif;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004822 unsigned long dpc_flags;
4823#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4824#define RESET_ACTIVE 1
4825#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4826#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4827#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4828#define LOOP_RESYNC_ACTIVE 5
4829#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4830#define RSCN_UPDATE 7 /* Perform an RSCN update. */
Shyam Sundarddb9b122009-03-24 09:08:10 -07004831#define RELOGIN_NEEDED 8
4832#define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4833#define ISP_ABORT_RETRY 10 /* ISP aborted. */
4834#define BEACON_BLINK_NEEDED 11
4835#define REGISTER_FDMI_NEEDED 12
4836#define FCPORT_UPDATE_NEEDED 13
4837#define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4838#define UNLOADING 15
4839#define NPIV_CONFIG_NEEDED 16
Giridhar Malavalia9083012010-04-12 17:59:55 -07004840#define ISP_UNRECOVERABLE 17
4841#define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
Madhuranath Iyengarb1d469892010-09-03 15:20:54 -07004842#define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
Saurav Kashyap579d12b2010-12-21 16:00:14 -08004843#define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
Quinn Tran48acad02018-08-02 13:16:44 -07004844#define N2N_LINK_RESET 21
Chad Dupuis50280c02013-10-30 03:38:14 -04004845#define PORT_UPDATE_NEEDED 22
4846#define FX00_RESET_RECOVERY 23
4847#define FX00_TARGET_SCAN 24
4848#define FX00_CRITEMP_RECOVERY 25
Armen Baloyane8f5e952013-10-30 03:38:17 -04004849#define FX00_HOST_INFO_RESEND 26
Michael Hernandezd7459522016-12-12 14:40:07 -08004850#define QPAIR_ONLINE_CHECK_NEEDED 27
Quinn Tranf7a0ed472021-03-29 01:52:25 -07004851#define DO_EEH_RECOVERY 28
Quinn Trane4e3a2c2017-08-23 15:05:07 -07004852#define DETECT_SFP_CHANGE 29
Duane Grigsbyc0c462c2017-10-13 09:34:05 -07004853#define N2N_LOGIN_NEEDED 30
Quinn Tran9b3e0f42017-12-28 12:33:16 -08004854#define IOCB_WORK_ACTIVE 31
Quinn Tran8b4673b2018-09-04 14:19:14 -07004855#define SET_ZIO_THRESHOLD_NEEDED 32
Michael Hernandez3f006ac2019-03-12 11:08:22 -07004856#define ISP_ABORT_TO_ROM 33
Quinn Tranf5187b72019-09-12 11:09:08 -07004857#define VPORT_DELETE 34
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004858
Joe Carnucciod83a80e2020-02-12 13:44:18 -08004859#define PROCESS_PUREX_IOCB 63
4860
Joe Lawrence232792b2014-08-26 17:12:01 -04004861 unsigned long pci_flags;
4862#define PFLG_DISCONNECTED 0 /* PCI device removed */
Joe Lawrencebeb9e312014-08-26 17:12:14 -04004863#define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
Joe Lawrence6b383972014-08-26 17:12:29 -04004864#define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
Joe Lawrence232792b2014-08-26 17:12:01 -04004865
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004866 uint32_t device_flags;
Shyam Sundarddb9b122009-03-24 09:08:10 -07004867#define SWITCH_FOUND BIT_0
4868#define DFLG_NO_CABLE BIT_1
Giridhar Malavalia9083012010-04-12 17:59:55 -07004869#define DFLG_DEV_FAILED BIT_5
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004870
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004871 /* ISP configuration data. */
4872 uint16_t loop_id; /* Host adapter loop id */
Saurav Kashyapa9b6f722012-08-22 14:21:01 -04004873 uint16_t self_login_loop_id; /* host adapter loop id
4874 * get it on self login
4875 */
4876 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4877 * no need of allocating it for
4878 * each command
4879 */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004880
4881 port_id_t d_id; /* Host adapter port id */
4882 uint8_t marker_needed;
4883 uint16_t mgmt_svr_loop_id;
4884
4885
4886
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004887 /* Timeout timers. */
4888 uint8_t loop_down_abort_time; /* port down timer */
4889 atomic_t loop_down_timer; /* loop down timer */
4890 uint8_t link_down_timeout; /* link down timeout */
4891
4892 uint32_t timer_active;
4893 struct timer_list timer;
4894
4895 uint8_t node_name[WWN_SIZE];
4896 uint8_t port_name[WWN_SIZE];
4897 uint8_t fabric_node_name[WWN_SIZE];
Joe Carnuccio818c7f82020-02-12 13:44:17 -08004898 uint8_t fabric_port_name[WWN_SIZE];
Andrew Vasquezbad70012009-04-06 22:33:38 -07004899
Duane Grigsbya5d42f42017-06-21 13:48:41 -07004900 struct nvme_fc_local_port *nvme_local_port;
himanshu.madhani@cavium.com5621b0d2017-07-21 09:32:26 -07004901 struct completion nvme_del_done;
Duane Grigsbya5d42f42017-06-21 13:48:41 -07004902
Andrew Vasquezbad70012009-04-06 22:33:38 -07004903 uint16_t fcoe_vlan_id;
4904 uint16_t fcoe_fcf_idx;
4905 uint8_t fcoe_vn_port_mac[6];
4906
Swapnil Nagle8b2f5ff2015-07-14 16:00:43 -04004907 /* list of commands waiting on workqueue */
4908 struct list_head qla_cmd_list;
4909 struct list_head qla_sess_op_cmd_list;
Quinn Tran41dc5292017-01-19 22:28:03 -08004910 struct list_head unknown_atio_list;
Swapnil Nagle8b2f5ff2015-07-14 16:00:43 -04004911 spinlock_t cmd_list_lock;
Quinn Tran41dc5292017-01-19 22:28:03 -08004912 struct delayed_work unknown_atio_work;
Swapnil Nagle8b2f5ff2015-07-14 16:00:43 -04004913
Alexei Potashnikdf673272015-07-14 16:00:46 -04004914 /* Counter to detect races between ELS and RSCN events */
4915 atomic_t generation_tick;
4916 /* Time when global fcport update has been scheduled */
4917 int total_fcport_update_gen;
Alexei Potashnik71cdc072015-12-17 14:57:01 -05004918 /* List of pending LOGOs, protected by tgt_mutex */
4919 struct list_head logo_list;
Alexei Potashnikb7bd1042015-12-17 14:57:02 -05004920 /* List of pending PLOGI acks, protected by hw lock */
4921 struct list_head plogi_ack_list;
Alexei Potashnikdf673272015-07-14 16:00:46 -04004922
Michael Hernandezd7459522016-12-12 14:40:07 -08004923 struct list_head qp_list;
4924
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004925 uint32_t vp_abort_cnt;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004926
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004927 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004928 uint16_t vp_idx; /* vport ID */
Michael Hernandezd7459522016-12-12 14:40:07 -08004929 struct qla_qpair *qpair; /* base qpair */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004930
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004931 unsigned long vp_flags;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004932#define VP_IDX_ACQUIRED 0 /* bit no 0 */
4933#define VP_CREATE_NEEDED 1
4934#define VP_BIND_NEEDED 2
4935#define VP_DELETE_NEEDED 3
4936#define VP_SCR_NEEDED 4 /* State Change Request registration */
Sawan Chandakded64112015-04-09 15:00:06 -04004937#define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07004938 atomic_t vp_state;
4939#define VP_OFFLINE 0
4940#define VP_ACTIVE 1
4941#define VP_FAILED 2
4942// #define VP_DISABLE 3
4943 uint16_t vp_err_state;
4944 uint16_t vp_prev_err_state;
4945#define VP_ERR_UNKWN 0
4946#define VP_ERR_PORTDWN 1
4947#define VP_ERR_FAB_UNSUPPORTED 2
4948#define VP_ERR_FAB_NORESOURCES 3
4949#define VP_ERR_FAB_LOGOUT 4
4950#define VP_ERR_ADAP_NORESOURCES 5
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08004951 struct qla_hw_data *hw;
Saurav Kashyap0e8cd712014-01-14 20:40:38 -08004952 struct scsi_qlt_host vha_tgt;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07004953 struct req_que *req;
Giridhar Malavalia9083012010-04-12 17:59:55 -07004954 int fw_heartbeat_counter;
4955 int seconds_since_last_heartbeat;
Saurav Kashyap2be21fa2012-05-15 14:34:16 -04004956 struct fc_host_statistics fc_host_stat;
4957 struct qla_statistics qla_stats;
Saurav Kashyapa9b6f722012-08-22 14:21:01 -04004958 struct bidi_statistics bidi_stats;
Arun Easifeafb7b2010-09-03 14:57:00 -07004959 atomic_t vref_count;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004960 struct qla8044_reset_template reset_tmplt;
Sawan Chandak969a6192016-01-27 12:03:32 -05004961 uint16_t bbcr;
Quinn Tran0645cb82018-09-11 10:18:18 -07004962
4963 uint16_t u_ql2xexchoffld;
4964 uint16_t u_ql2xiniexchg;
4965 uint16_t qlini_mode;
4966 uint16_t ql2xexchoffld;
4967 uint16_t ql2xiniexchg;
4968
Arun Easi1e98fb02020-09-03 21:51:17 -07004969 struct dentry *dfs_rport_root;
4970
Joe Carnuccio576bfde2020-02-12 13:44:24 -08004971 struct purex_list {
4972 struct list_head head;
4973 spinlock_t lock;
4974 } purex_list;
Shyam Sundar62e9dd12020-06-30 03:22:28 -07004975 struct purex_item default_item;
Joe Carnuccio576bfde2020-02-12 13:44:24 -08004976
Quinn Tran726b8542017-01-19 22:28:00 -08004977 struct name_list_extended gnl;
4978 /* Count of active session/fcport */
4979 int fcport_count;
4980 wait_queue_head_t fcport_waitQ;
Joe Carnuccioc4a9b532017-03-15 09:48:43 -07004981 wait_queue_head_t vref_waitq;
Joe Carnuccio72a92df2019-03-12 11:08:15 -07004982 uint8_t min_supported_speed;
Duane Grigsbyedd05de2017-10-13 09:34:06 -07004983 uint8_t n2n_node_name[WWN_SIZE];
4984 uint8_t n2n_port_name[WWN_SIZE];
4985 uint16_t n2n_id;
Joe Carnuccioe6ad2b72020-02-12 13:44:14 -08004986 __le16 dport_data[4];
Quinn Tran2d73ac62017-12-04 14:45:02 -08004987 struct list_head gpnid_list;
Quinn Trana4239942017-12-28 12:33:26 -08004988 struct fab_scan scan;
Shyam Sundar9f2475f2020-06-30 03:22:29 -07004989 uint8_t scm_fabric_connection_flags;
Ming Leif0783d42019-01-11 09:40:47 -08004990
4991 unsigned int irq_offset;
Saurav Kashyapdbf1f532021-01-11 01:31:28 -08004992
4993 u64 hw_err_cnt;
4994 u64 interface_err_cnt;
4995 u64 cmd_timeout_cnt;
4996 u64 reset_cmd_err_cnt;
4997 u64 link_down_time;
4998 u64 short_link_down_cnt;
Quinn Tran7ebb336e2021-06-23 22:25:56 -07004999 struct edif_dbell e_dbell;
5000 struct pur_core pur_cinfo;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005001} scsi_qla_host_t;
5002
Sawan Chandak4243c112016-01-27 12:03:31 -05005003struct qla27xx_image_status {
5004 uint8_t image_status_mask;
Bart Van Assche21038b02020-05-18 14:17:11 -07005005 __le16 generation;
Sawan Chandak4243c112016-01-27 12:03:31 -05005006 uint8_t ver_major;
Joe Carnuccio5fa87742019-03-12 11:08:21 -07005007 uint8_t ver_minor;
5008 uint8_t bitmap; /* 28xx only */
5009 uint8_t reserved[2];
Bart Van Assche21038b02020-05-18 14:17:11 -07005010 __le32 checksum;
5011 __le32 signature;
Sawan Chandak4243c112016-01-27 12:03:31 -05005012} __packed;
5013
Joe Carnuccio5fa87742019-03-12 11:08:21 -07005014/* 28xx aux image status bimap values */
5015#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
5016#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
5017#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
5018#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
5019
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04005020#define SET_VP_IDX 1
5021#define SET_AL_PA 2
5022#define RESET_VP_IDX 3
5023#define RESET_AL_PA 4
5024struct qla_tgt_vp_map {
5025 uint8_t idx;
5026 scsi_qla_host_t *vha;
5027};
5028
Michael Hernandezd7459522016-12-12 14:40:07 -08005029struct qla2_sgx {
5030 dma_addr_t dma_addr; /* OUT */
5031 uint32_t dma_len; /* OUT */
5032
5033 uint32_t tot_bytes; /* IN */
5034 struct scatterlist *cur_sg; /* IN */
5035
5036 /* for book keeping, bzero on initial invocation */
5037 uint32_t bytes_consumed;
5038 uint32_t num_bytes;
5039 uint32_t tot_partial;
5040
5041 /* for debugging */
5042 uint32_t num_sg;
5043 srb_t *sp;
5044};
5045
Quinn Tran4b60c822017-06-13 20:47:21 -07005046#define QLA_FW_STARTED(_ha) { \
5047 int i; \
5048 _ha->flags.fw_started = 1; \
5049 _ha->base_qpair->fw_started = 1; \
5050 for (i = 0; i < _ha->max_qpairs; i++) { \
5051 if (_ha->queue_pair_map[i]) \
5052 _ha->queue_pair_map[i]->fw_started = 1; \
5053 } \
5054}
5055
5056#define QLA_FW_STOPPED(_ha) { \
5057 int i; \
5058 _ha->flags.fw_started = 0; \
5059 _ha->base_qpair->fw_started = 0; \
5060 for (i = 0; i < _ha->max_qpairs; i++) { \
5061 if (_ha->queue_pair_map[i]) \
5062 _ha->queue_pair_map[i]->fw_started = 0; \
5063 } \
5064}
5065
Michael Hernandez3f006ac2019-03-12 11:08:22 -07005066
5067#define SFUB_CHECKSUM_SIZE 4
5068
5069struct secure_flash_update_block {
5070 uint32_t block_info;
5071 uint32_t signature_lo;
5072 uint32_t signature_hi;
5073 uint32_t signature_upper[0x3e];
5074};
5075
5076struct secure_flash_update_block_pk {
5077 uint32_t block_info;
5078 uint32_t signature_lo;
5079 uint32_t signature_hi;
5080 uint32_t signature_upper[0x3e];
5081 uint32_t public_key[0x41];
5082};
5083
Linus Torvalds1da177e2005-04-16 15:20:36 -07005084/*
5085 * Macros to help code, maintain, etc.
5086 */
5087#define LOOP_TRANSITION(ha) \
5088 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
Andrew Vasquez23443b12005-12-06 10:57:06 -08005089 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -07005090 atomic_read(&ha->loop_state) == LOOP_DOWN)
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07005091
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04005092#define STATE_TRANSITION(ha) \
5093 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5094 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
5095
Michael Hernandezd7459522016-12-12 14:40:07 -08005096#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
5097 atomic_inc(&__vha->vref_count); \
5098 mb(); \
5099 if (__vha->flags.delete_progress) { \
5100 atomic_dec(&__vha->vref_count); \
Joe Carnuccioc4a9b532017-03-15 09:48:43 -07005101 wake_up(&__vha->vref_waitq); \
Michael Hernandezd7459522016-12-12 14:40:07 -08005102 __bail = 1; \
5103 } else { \
5104 __bail = 0; \
5105 } \
Arun Easifeafb7b2010-09-03 14:57:00 -07005106} while (0)
5107
Joe Carnuccioc4a9b532017-03-15 09:48:43 -07005108#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
Michael Hernandezd7459522016-12-12 14:40:07 -08005109 atomic_dec(&__vha->vref_count); \
Joe Carnuccioc4a9b532017-03-15 09:48:43 -07005110 wake_up(&__vha->vref_waitq); \
5111} while (0) \
Michael Hernandezd7459522016-12-12 14:40:07 -08005112
5113#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
5114 atomic_inc(&__qpair->ref_count); \
5115 mb(); \
5116 if (__qpair->delete_in_progress) { \
5117 atomic_dec(&__qpair->ref_count); \
5118 __bail = 1; \
5119 } else { \
5120 __bail = 0; \
5121 } \
Arun Easifeafb7b2010-09-03 14:57:00 -07005122} while (0)
5123
Michael Hernandezd7459522016-12-12 14:40:07 -08005124#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
Tom Rix8f525bc2020-11-30 12:55:09 -08005125 atomic_dec(&__qpair->ref_count)
Quinn Tran7c3f8fd2017-06-13 20:47:22 -07005126
5127#define QLA_ENA_CONF(_ha) {\
5128 int i;\
5129 _ha->base_qpair->enable_explicit_conf = 1; \
5130 for (i = 0; i < _ha->max_qpairs; i++) { \
5131 if (_ha->queue_pair_map[i]) \
5132 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5133 } \
5134}
5135
5136#define QLA_DIS_CONF(_ha) {\
5137 int i;\
5138 _ha->base_qpair->enable_explicit_conf = 0; \
5139 for (i = 0; i < _ha->max_qpairs; i++) { \
5140 if (_ha->queue_pair_map[i]) \
5141 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5142 } \
5143}
5144
Linus Torvalds1da177e2005-04-16 15:20:36 -07005145/*
5146 * qla2x00 local function return status codes
5147 */
5148#define MBS_MASK 0x3fff
5149
5150#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
5151#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
5152#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5153#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5154#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5155#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5156#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5157#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5158#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5159#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5160
5161#define QLA_FUNCTION_TIMEOUT 0x100
5162#define QLA_FUNCTION_PARAMETER_ERROR 0x101
5163#define QLA_FUNCTION_FAILED 0x102
5164#define QLA_MEMORY_ALLOC_FAILED 0x103
5165#define QLA_LOCK_TIMEOUT 0x104
5166#define QLA_ABORTED 0x105
5167#define QLA_SUSPENDED 0x106
5168#define QLA_BUSY 0x107
Andrew Vasquezcca53352005-08-26 19:08:30 -07005169#define QLA_ALREADY_REGISTERED 0x109
Quinn Tran0c6df592019-07-26 09:07:28 -07005170#define QLA_OS_TIMER_EXPIRED 0x10a
Arun Easi2cabf102021-08-16 22:13:11 -07005171#define QLA_ERR_NO_QPAIR 0x10b
5172#define QLA_ERR_NOT_FOUND 0x10c
5173#define QLA_ERR_FROM_FW 0x10d
Linus Torvalds1da177e2005-04-16 15:20:36 -07005174
Linus Torvalds1da177e2005-04-16 15:20:36 -07005175#define NVRAM_DELAY() udelay(10)
5176
Linus Torvalds1da177e2005-04-16 15:20:36 -07005177/*
5178 * Flash support definitions
5179 */
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08005180#define OPTROM_SIZE_2300 0x20000
5181#define OPTROM_SIZE_2322 0x100000
5182#define OPTROM_SIZE_24XX 0x100000
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07005183#define OPTROM_SIZE_25XX 0x200000
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08005184#define OPTROM_SIZE_81XX 0x400000
Giridhar Malavalia9083012010-04-12 17:59:55 -07005185#define OPTROM_SIZE_82XX 0x800000
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08005186#define OPTROM_SIZE_83XX 0x1000000
Joe Carnuccioecc89f22019-03-12 11:08:13 -07005187#define OPTROM_SIZE_28XX 0x2000000
Giridhar Malavalia9083012010-04-12 17:59:55 -07005188
5189#define OPTROM_BURST_SIZE 0x1000
5190#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005191
Arun Easibad75002010-05-04 15:01:30 -07005192#define QLA_DSDS_PER_IOCB 37
5193
Giridhar Malavali4d78c972010-07-23 15:28:35 +05005194#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
5195
Giridhar Malavali58548cb2010-09-03 15:20:56 -07005196#define QLA_SG_ALL 1024
5197
Giridhar Malavali4d78c972010-07-23 15:28:35 +05005198enum nexus_wait_type {
5199 WAIT_HOST = 0,
5200 WAIT_TARGET,
5201 WAIT_LUN,
5202};
5203
Quinn Trandd307062021-06-23 22:26:00 -07005204#define INVALID_EDIF_SA_INDEX 0xffff
5205#define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe
5206
Quinn Tran84318a92021-06-23 22:25:58 -07005207#define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE
Quinn Trandd307062021-06-23 22:26:00 -07005208
5209/* edif hash element */
5210struct edif_list_entry {
5211 uint16_t handle; /* nport_handle */
5212 uint32_t update_sa_index;
5213 uint32_t delete_sa_index;
5214 uint32_t count; /* counter for filtering sa_index */
5215#define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */
5216 uint32_t flags; /* used by sadb cleanup code */
5217 fc_port_t *fcport; /* needed by rx delay timer function */
5218 struct timer_list timer; /* rx delay timer */
5219 struct list_head next;
5220};
5221
5222#define EDIF_TX_INDX_BASE 512
5223#define EDIF_RX_INDX_BASE 0
5224#define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */
5225
5226/* entry in the sa_index free pool */
5227
5228struct sa_index_pair {
5229 uint16_t sa_index;
5230 uint32_t spi;
5231};
5232
5233/* edif sa_index data structure */
5234struct edif_sa_index_entry {
5235 struct sa_index_pair sa_pair[2];
5236 fc_port_t *fcport;
5237 uint16_t handle;
5238 struct list_head next;
5239};
5240
Quinn Trane4e3a2c2017-08-23 15:05:07 -07005241/* Refer to SNIA SFF 8247 */
5242struct sff_8247_a0 {
5243 u8 txid; /* transceiver id */
5244 u8 ext_txid;
5245 u8 connector;
5246 /* compliance code */
5247 u8 eth_infi_cc3; /* ethernet, inifiband */
5248 u8 sonet_cc4[2];
5249 u8 eth_cc6;
5250 /* link length */
5251#define FC_LL_VL BIT_7 /* very long */
5252#define FC_LL_S BIT_6 /* Short */
5253#define FC_LL_I BIT_5 /* Intermidiate*/
5254#define FC_LL_L BIT_4 /* Long */
5255#define FC_LL_M BIT_3 /* Medium */
5256#define FC_LL_SA BIT_2 /* ShortWave laser */
5257#define FC_LL_LC BIT_1 /* LongWave laser */
5258#define FC_LL_EL BIT_0 /* Electrical inter enclosure */
5259 u8 fc_ll_cc7;
5260 /* FC technology */
5261#define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
5262#define FC_TEC_SN BIT_6 /* short wave w/o OFC */
5263#define FC_TEC_SL BIT_5 /* short wave with OFC */
5264#define FC_TEC_LL BIT_4 /* Longwave Laser */
5265#define FC_TEC_ACT BIT_3 /* Active cable */
5266#define FC_TEC_PAS BIT_2 /* Passive cable */
5267 u8 fc_tec_cc8;
5268 /* Transmission Media */
5269#define FC_MED_TW BIT_7 /* Twin Ax */
5270#define FC_MED_TP BIT_6 /* Twited Pair */
5271#define FC_MED_MI BIT_5 /* Min Coax */
5272#define FC_MED_TV BIT_4 /* Video Coax */
5273#define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
5274#define FC_MED_M5 BIT_2 /* Multimode, 50um */
5275#define FC_MED_SM BIT_0 /* Single Mode */
5276 u8 fc_med_cc9;
5277 /* speed FC_SP_12: 12*100M = 1200 MB/s */
5278#define FC_SP_12 BIT_7
5279#define FC_SP_8 BIT_6
5280#define FC_SP_16 BIT_5
5281#define FC_SP_4 BIT_4
5282#define FC_SP_32 BIT_3
5283#define FC_SP_2 BIT_2
5284#define FC_SP_1 BIT_0
5285 u8 fc_sp_cc10;
5286 u8 encode;
5287 u8 bitrate;
5288 u8 rate_id;
5289 u8 length_km; /* offset 14/eh */
5290 u8 length_100m;
5291 u8 length_50um_10m;
5292 u8 length_62um_10m;
5293 u8 length_om4_10m;
5294 u8 length_om3_10m;
5295#define SFF_VEN_NAME_LEN 16
5296 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
5297 u8 tx_compat;
5298 u8 vendor_oui[3];
5299#define SFF_PART_NAME_LEN 16
5300 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
5301 u8 vendor_rev[4];
5302 u8 wavelength[2];
5303 u8 resv;
5304 u8 cc_base;
5305 u8 options[2]; /* offset 64 */
5306 u8 br_max;
5307 u8 br_min;
5308 u8 vendor_sn[16];
5309 u8 date_code[8];
5310 u8 diag;
5311 u8 enh_options;
5312 u8 sff_revision;
5313 u8 cc_ext;
5314 u8 vendor_specific[32];
5315 u8 resv2[128];
5316};
5317
Andrew Vasquezb0f18ee2020-02-26 14:40:13 -08005318/* BPM -- Buffer Plus Management support. */
5319#define IS_BPM_CAPABLE(ha) \
5320 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5321 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5322#define IS_BPM_RANGE_CAPABLE(ha) \
5323 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5324#define IS_BPM_ENABLED(vha) \
5325 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
Quinn Trane4e3a2c2017-08-23 15:05:07 -07005326
Michael Hernandez3f006ac2019-03-12 11:08:22 -07005327#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5328
Quinn Tran09620eeb2017-06-13 20:47:20 -07005329#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
Joe Carnuccioecc89f22019-03-12 11:08:13 -07005330 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
Quinn Tran09620eeb2017-06-13 20:47:20 -07005331
Quinn Tran9cd883f2017-12-28 12:33:24 -08005332#define SAVE_TOPO(_ha) { \
5333 if (_ha->current_topology) \
5334 _ha->prev_topology = _ha->current_topology; \
5335}
5336
5337#define N2N_TOPO(ha) \
5338 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5339 ha->current_topology == ISP_CFG_N || \
5340 !ha->current_topology)
5341
Arun Easi94eda272020-09-29 03:21:51 -07005342#define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
5343
Michael Hernandez84ed3622019-09-12 11:09:12 -07005344#define NVME_TYPE(fcport) \
5345 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5346
5347#define FCP_TYPE(fcport) \
5348 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5349
5350#define NVME_ONLY_TARGET(fcport) \
5351 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5352
5353#define NVME_FCP_TARGET(fcport) \
5354 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5355
Quinn Tranf8844452021-08-16 22:13:12 -07005356#define NVME_PRIORITY(ha, fcport) \
5357 (NVME_FCP_TARGET(fcport) && \
5358 (ha->fc4_type_priority == FC4_PRIORITY_NVME))
5359
Michael Hernandez84ed3622019-09-12 11:09:12 -07005360#define NVME_TARGET(ha, fcport) \
Quinn Tranf8844452021-08-16 22:13:12 -07005361 (fcport->do_prli_nvme || \
Michael Hernandez84ed3622019-09-12 11:09:12 -07005362 NVME_ONLY_TARGET(fcport)) \
5363
Quinn Tran8aaac2d2019-12-17 14:06:11 -08005364#define PRLI_PHASE(_cls) \
5365 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5366
Saurav Kashyapdbf1f532021-01-11 01:31:28 -08005367enum ql_vnd_host_stat_action {
5368 QLA_STOP = 0,
5369 QLA_START,
5370 QLA_CLEAR,
5371};
5372
5373struct ql_vnd_mng_host_stats_param {
5374 u32 stat_type;
5375 enum ql_vnd_host_stat_action action;
5376} __packed;
5377
5378struct ql_vnd_mng_host_stats_resp {
5379 u32 status;
5380} __packed;
5381
5382struct ql_vnd_stats_param {
5383 u32 stat_type;
5384} __packed;
5385
5386struct ql_vnd_tgt_stats_param {
5387 s32 tgt_id;
5388 u32 stat_type;
5389} __packed;
5390
5391enum ql_vnd_host_port_action {
5392 QLA_ENABLE = 0,
5393 QLA_DISABLE,
5394};
5395
5396struct ql_vnd_mng_host_port_param {
5397 enum ql_vnd_host_port_action action;
5398} __packed;
5399
5400struct ql_vnd_mng_host_port_resp {
5401 u32 status;
5402} __packed;
5403
5404struct ql_vnd_stat_entry {
5405 u32 stat_type; /* Failure type */
5406 u32 tgt_num; /* Target Num */
5407 u64 cnt; /* Counter value */
5408} __packed;
5409
5410struct ql_vnd_stats {
5411 u64 entry_count; /* Num of entries */
5412 u64 rservd;
5413 struct ql_vnd_stat_entry entry[0]; /* Place holder of entries */
5414} __packed;
5415
5416struct ql_vnd_host_stats_resp {
5417 u32 status;
5418 struct ql_vnd_stats stats;
5419} __packed;
5420
5421struct ql_vnd_tgt_stats_resp {
5422 u32 status;
5423 struct ql_vnd_stats stats;
5424} __packed;
5425
Quinn Tranc5419e22017-06-13 20:47:16 -07005426#include "qla_target.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07005427#include "qla_gbl.h"
5428#include "qla_dbg.h"
5429#include "qla_inline.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07005430#endif