Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for the r8a774b1 SoC |
| 4 | * |
| 5 | * Copyright (C) 2019 Renesas Electronics Corp. |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/interrupt-controller/irq.h> |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> |
| 11 | #include <dt-bindings/power/r8a774b1-sysc.h> |
| 12 | |
| 13 | / { |
| 14 | compatible = "renesas,r8a774b1"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | /* |
| 19 | * The external audio clocks are configured as 0 Hz fixed frequency |
| 20 | * clocks by default. |
| 21 | * Boards that provide audio clocks should override them. |
| 22 | */ |
| 23 | audio_clk_a: audio_clk_a { |
| 24 | compatible = "fixed-clock"; |
| 25 | #clock-cells = <0>; |
| 26 | clock-frequency = <0>; |
| 27 | }; |
| 28 | |
| 29 | audio_clk_b: audio_clk_b { |
| 30 | compatible = "fixed-clock"; |
| 31 | #clock-cells = <0>; |
| 32 | clock-frequency = <0>; |
| 33 | }; |
| 34 | |
| 35 | audio_clk_c: audio_clk_c { |
| 36 | compatible = "fixed-clock"; |
| 37 | #clock-cells = <0>; |
| 38 | clock-frequency = <0>; |
| 39 | }; |
| 40 | |
| 41 | /* External CAN clock - to be overridden by boards that provide it */ |
| 42 | can_clk: can { |
| 43 | compatible = "fixed-clock"; |
| 44 | #clock-cells = <0>; |
| 45 | clock-frequency = <0>; |
| 46 | }; |
| 47 | |
Biju Das | ce21f29 | 2019-09-23 15:57:25 +0100 | [diff] [blame] | 48 | cluster0_opp: opp_table0 { |
| 49 | compatible = "operating-points-v2"; |
| 50 | opp-shared; |
| 51 | |
| 52 | opp-500000000 { |
| 53 | opp-hz = /bits/ 64 <500000000>; |
| 54 | opp-microvolt = <830000>; |
| 55 | clock-latency-ns = <300000>; |
| 56 | }; |
| 57 | opp-1000000000 { |
| 58 | opp-hz = /bits/ 64 <1000000000>; |
| 59 | opp-microvolt = <830000>; |
| 60 | clock-latency-ns = <300000>; |
| 61 | }; |
| 62 | opp-1500000000 { |
| 63 | opp-hz = /bits/ 64 <1500000000>; |
| 64 | opp-microvolt = <830000>; |
| 65 | clock-latency-ns = <300000>; |
| 66 | opp-suspend; |
| 67 | }; |
| 68 | }; |
| 69 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 70 | cpus { |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <0>; |
| 73 | |
| 74 | a57_0: cpu@0 { |
| 75 | compatible = "arm,cortex-a57"; |
| 76 | reg = <0x0>; |
| 77 | device_type = "cpu"; |
| 78 | power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; |
| 79 | next-level-cache = <&L2_CA57>; |
| 80 | enable-method = "psci"; |
| 81 | #cooling-cells = <2>; |
| 82 | dynamic-power-coefficient = <854>; |
| 83 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
Biju Das | ce21f29 | 2019-09-23 15:57:25 +0100 | [diff] [blame] | 84 | operating-points-v2 = <&cluster0_opp>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | a57_1: cpu@1 { |
| 88 | compatible = "arm,cortex-a57"; |
| 89 | reg = <0x1>; |
| 90 | device_type = "cpu"; |
| 91 | power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; |
| 92 | next-level-cache = <&L2_CA57>; |
| 93 | enable-method = "psci"; |
| 94 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
Biju Das | ce21f29 | 2019-09-23 15:57:25 +0100 | [diff] [blame] | 95 | operating-points-v2 = <&cluster0_opp>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | L2_CA57: cache-controller-0 { |
| 99 | compatible = "cache"; |
| 100 | power-domains = <&sysc R8A774B1_PD_CA57_SCU>; |
| 101 | cache-unified; |
| 102 | cache-level = <2>; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | extal_clk: extal { |
| 107 | compatible = "fixed-clock"; |
| 108 | #clock-cells = <0>; |
| 109 | /* This value must be overridden by the board */ |
| 110 | clock-frequency = <0>; |
| 111 | }; |
| 112 | |
| 113 | extalr_clk: extalr { |
| 114 | compatible = "fixed-clock"; |
| 115 | #clock-cells = <0>; |
| 116 | /* This value must be overridden by the board */ |
| 117 | clock-frequency = <0>; |
| 118 | }; |
| 119 | |
| 120 | /* External PCIe clock - can be overridden by the board */ |
| 121 | pcie_bus_clk: pcie_bus { |
| 122 | compatible = "fixed-clock"; |
| 123 | #clock-cells = <0>; |
| 124 | clock-frequency = <0>; |
| 125 | }; |
| 126 | |
| 127 | pmu_a57 { |
| 128 | compatible = "arm,cortex-a57-pmu"; |
| 129 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 131 | interrupt-affinity = <&a57_0>, <&a57_1>; |
| 132 | }; |
| 133 | |
| 134 | psci { |
| 135 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| 136 | method = "smc"; |
| 137 | }; |
| 138 | |
| 139 | /* External SCIF clock - to be overridden by boards that provide it */ |
| 140 | scif_clk: scif { |
| 141 | compatible = "fixed-clock"; |
| 142 | #clock-cells = <0>; |
| 143 | clock-frequency = <0>; |
| 144 | }; |
| 145 | |
| 146 | soc { |
| 147 | compatible = "simple-bus"; |
| 148 | interrupt-parent = <&gic>; |
| 149 | #address-cells = <2>; |
| 150 | #size-cells = <2>; |
| 151 | ranges; |
| 152 | |
| 153 | rwdt: watchdog@e6020000 { |
| 154 | reg = <0 0xe6020000 0 0x0c>; |
| 155 | /* placeholder */ |
| 156 | }; |
| 157 | |
| 158 | gpio0: gpio@e6050000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 159 | compatible = "renesas,gpio-r8a774b1", |
| 160 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 161 | reg = <0 0xe6050000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 162 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 163 | #gpio-cells = <2>; |
| 164 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 165 | gpio-ranges = <&pfc 0 0 16>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 166 | #interrupt-cells = <2>; |
| 167 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 168 | clocks = <&cpg CPG_MOD 912>; |
| 169 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 170 | resets = <&cpg 912>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | gpio1: gpio@e6051000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 174 | compatible = "renesas,gpio-r8a774b1", |
| 175 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 176 | reg = <0 0xe6051000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 177 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 178 | #gpio-cells = <2>; |
| 179 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 180 | gpio-ranges = <&pfc 0 32 29>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 181 | #interrupt-cells = <2>; |
| 182 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 183 | clocks = <&cpg CPG_MOD 911>; |
| 184 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 185 | resets = <&cpg 911>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | gpio2: gpio@e6052000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 189 | compatible = "renesas,gpio-r8a774b1", |
| 190 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 191 | reg = <0 0xe6052000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 192 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 193 | #gpio-cells = <2>; |
| 194 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 195 | gpio-ranges = <&pfc 0 64 15>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 196 | #interrupt-cells = <2>; |
| 197 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 198 | clocks = <&cpg CPG_MOD 910>; |
| 199 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 200 | resets = <&cpg 910>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | gpio3: gpio@e6053000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 204 | compatible = "renesas,gpio-r8a774b1", |
| 205 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 206 | reg = <0 0xe6053000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 207 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 208 | #gpio-cells = <2>; |
| 209 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 210 | gpio-ranges = <&pfc 0 96 16>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 211 | #interrupt-cells = <2>; |
| 212 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 213 | clocks = <&cpg CPG_MOD 909>; |
| 214 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 215 | resets = <&cpg 909>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | gpio4: gpio@e6054000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 219 | compatible = "renesas,gpio-r8a774b1", |
| 220 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 221 | reg = <0 0xe6054000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 222 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 223 | #gpio-cells = <2>; |
| 224 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 225 | gpio-ranges = <&pfc 0 128 18>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 226 | #interrupt-cells = <2>; |
| 227 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 228 | clocks = <&cpg CPG_MOD 908>; |
| 229 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 230 | resets = <&cpg 908>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | gpio5: gpio@e6055000 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 234 | compatible = "renesas,gpio-r8a774b1", |
| 235 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 236 | reg = <0 0xe6055000 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 237 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 238 | #gpio-cells = <2>; |
| 239 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 240 | gpio-ranges = <&pfc 0 160 26>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 241 | #interrupt-cells = <2>; |
| 242 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 243 | clocks = <&cpg CPG_MOD 907>; |
| 244 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 245 | resets = <&cpg 907>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | gpio6: gpio@e6055400 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 249 | compatible = "renesas,gpio-r8a774b1", |
| 250 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 251 | reg = <0 0xe6055400 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 252 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 253 | #gpio-cells = <2>; |
| 254 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 255 | gpio-ranges = <&pfc 0 192 32>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 256 | #interrupt-cells = <2>; |
| 257 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 258 | clocks = <&cpg CPG_MOD 906>; |
| 259 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 260 | resets = <&cpg 906>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | gpio7: gpio@e6055800 { |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 264 | compatible = "renesas,gpio-r8a774b1", |
| 265 | "renesas,rcar-gen3-gpio"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 266 | reg = <0 0xe6055800 0 0x50>; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 267 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 268 | #gpio-cells = <2>; |
| 269 | gpio-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 270 | gpio-ranges = <&pfc 0 224 4>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 271 | #interrupt-cells = <2>; |
| 272 | interrupt-controller; |
Biju Das | bbbb919 | 2019-09-30 09:18:45 +0100 | [diff] [blame] | 273 | clocks = <&cpg CPG_MOD 905>; |
| 274 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 275 | resets = <&cpg 905>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | pfc: pin-controller@e6060000 { |
| 279 | compatible = "renesas,pfc-r8a774b1"; |
| 280 | reg = <0 0xe6060000 0 0x50c>; |
| 281 | }; |
| 282 | |
Biju Das | 39040e8 | 2019-09-23 15:57:27 +0100 | [diff] [blame] | 283 | cmt0: timer@e60f0000 { |
| 284 | compatible = "renesas,r8a774b1-cmt0", |
| 285 | "renesas,rcar-gen3-cmt0"; |
| 286 | reg = <0 0xe60f0000 0 0x1004>; |
| 287 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 288 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 289 | clocks = <&cpg CPG_MOD 303>; |
| 290 | clock-names = "fck"; |
| 291 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 292 | resets = <&cpg 303>; |
| 293 | status = "disabled"; |
| 294 | }; |
| 295 | |
| 296 | cmt1: timer@e6130000 { |
| 297 | compatible = "renesas,r8a774b1-cmt1", |
| 298 | "renesas,rcar-gen3-cmt1"; |
| 299 | reg = <0 0xe6130000 0 0x1004>; |
| 300 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 301 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 302 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 303 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| 305 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| 306 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| 307 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| 308 | clocks = <&cpg CPG_MOD 302>; |
| 309 | clock-names = "fck"; |
| 310 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 311 | resets = <&cpg 302>; |
| 312 | status = "disabled"; |
| 313 | }; |
| 314 | |
| 315 | cmt2: timer@e6140000 { |
| 316 | compatible = "renesas,r8a774b1-cmt1", |
| 317 | "renesas,rcar-gen3-cmt1"; |
| 318 | reg = <0 0xe6140000 0 0x1004>; |
| 319 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| 320 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| 321 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| 322 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| 323 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| 324 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| 325 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| 326 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; |
| 327 | clocks = <&cpg CPG_MOD 301>; |
| 328 | clock-names = "fck"; |
| 329 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 330 | resets = <&cpg 301>; |
| 331 | status = "disabled"; |
| 332 | }; |
| 333 | |
| 334 | cmt3: timer@e6148000 { |
| 335 | compatible = "renesas,r8a774b1-cmt1", |
| 336 | "renesas,rcar-gen3-cmt1"; |
| 337 | reg = <0 0xe6148000 0 0x1004>; |
| 338 | interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, |
| 340 | <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, |
| 341 | <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, |
| 342 | <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, |
| 343 | <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, |
| 344 | <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, |
| 345 | <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; |
| 346 | clocks = <&cpg CPG_MOD 300>; |
| 347 | clock-names = "fck"; |
| 348 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 349 | resets = <&cpg 300>; |
| 350 | status = "disabled"; |
| 351 | }; |
| 352 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 353 | cpg: clock-controller@e6150000 { |
| 354 | compatible = "renesas,r8a774b1-cpg-mssr"; |
| 355 | reg = <0 0xe6150000 0 0x1000>; |
| 356 | clocks = <&extal_clk>, <&extalr_clk>; |
| 357 | clock-names = "extal", "extalr"; |
| 358 | #clock-cells = <2>; |
| 359 | #power-domain-cells = <0>; |
| 360 | #reset-cells = <1>; |
| 361 | }; |
| 362 | |
| 363 | rst: reset-controller@e6160000 { |
| 364 | compatible = "renesas,r8a774b1-rst"; |
| 365 | reg = <0 0xe6160000 0 0x0200>; |
| 366 | }; |
| 367 | |
| 368 | sysc: system-controller@e6180000 { |
| 369 | compatible = "renesas,r8a774b1-sysc"; |
| 370 | reg = <0 0xe6180000 0 0x0400>; |
| 371 | #power-domain-cells = <1>; |
| 372 | }; |
| 373 | |
Biju Das | 95b3547 | 2019-09-23 15:57:26 +0100 | [diff] [blame] | 374 | tsc: thermal@e6198000 { |
| 375 | compatible = "renesas,r8a774b1-thermal"; |
| 376 | reg = <0 0xe6198000 0 0x100>, |
| 377 | <0 0xe61a0000 0 0x100>, |
| 378 | <0 0xe61a8000 0 0x100>; |
| 379 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 380 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| 381 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 382 | clocks = <&cpg CPG_MOD 522>; |
| 383 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 384 | resets = <&cpg 522>; |
| 385 | #thermal-sensor-cells = <1>; |
| 386 | }; |
| 387 | |
Biju Das | 928249b | 2019-09-23 15:57:28 +0100 | [diff] [blame] | 388 | tmu0: timer@e61e0000 { |
| 389 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| 390 | reg = <0 0xe61e0000 0 0x30>; |
| 391 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 392 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 393 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | clocks = <&cpg CPG_MOD 125>; |
| 395 | clock-names = "fck"; |
| 396 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 397 | resets = <&cpg 125>; |
| 398 | status = "disabled"; |
| 399 | }; |
| 400 | |
| 401 | tmu1: timer@e6fc0000 { |
| 402 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| 403 | reg = <0 0xe6fc0000 0 0x30>; |
| 404 | interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 405 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 406 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | clocks = <&cpg CPG_MOD 124>; |
| 408 | clock-names = "fck"; |
| 409 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 410 | resets = <&cpg 124>; |
| 411 | status = "disabled"; |
| 412 | }; |
| 413 | |
| 414 | tmu2: timer@e6fd0000 { |
| 415 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| 416 | reg = <0 0xe6fd0000 0 0x30>; |
| 417 | interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, |
| 418 | <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| 419 | <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
| 420 | clocks = <&cpg CPG_MOD 123>; |
| 421 | clock-names = "fck"; |
| 422 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 423 | resets = <&cpg 123>; |
| 424 | status = "disabled"; |
| 425 | }; |
| 426 | |
| 427 | tmu3: timer@e6fe0000 { |
| 428 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| 429 | reg = <0 0xe6fe0000 0 0x30>; |
| 430 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 431 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 432 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| 433 | clocks = <&cpg CPG_MOD 122>; |
| 434 | clock-names = "fck"; |
| 435 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 436 | resets = <&cpg 122>; |
| 437 | status = "disabled"; |
| 438 | }; |
| 439 | |
| 440 | tmu4: timer@ffc00000 { |
| 441 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| 442 | reg = <0 0xffc00000 0 0x30>; |
| 443 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| 444 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| 445 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | clocks = <&cpg CPG_MOD 121>; |
| 447 | clock-names = "fck"; |
| 448 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 449 | resets = <&cpg 121>; |
| 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
Biju Das | 070302d | 2019-09-24 09:22:50 +0100 | [diff] [blame] | 453 | i2c0: i2c@e6500000 { |
| 454 | #address-cells = <1>; |
| 455 | #size-cells = <0>; |
| 456 | compatible = "renesas,i2c-r8a774b1", |
| 457 | "renesas,rcar-gen3-i2c"; |
| 458 | reg = <0 0xe6500000 0 0x40>; |
| 459 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| 460 | clocks = <&cpg CPG_MOD 931>; |
| 461 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 462 | resets = <&cpg 931>; |
| 463 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, |
| 464 | <&dmac2 0x91>, <&dmac2 0x90>; |
| 465 | dma-names = "tx", "rx", "tx", "rx"; |
| 466 | i2c-scl-internal-delay-ns = <110>; |
| 467 | status = "disabled"; |
| 468 | }; |
| 469 | |
| 470 | i2c1: i2c@e6508000 { |
| 471 | #address-cells = <1>; |
| 472 | #size-cells = <0>; |
| 473 | compatible = "renesas,i2c-r8a774b1", |
| 474 | "renesas,rcar-gen3-i2c"; |
| 475 | reg = <0 0xe6508000 0 0x40>; |
| 476 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| 477 | clocks = <&cpg CPG_MOD 930>; |
| 478 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 479 | resets = <&cpg 930>; |
| 480 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, |
| 481 | <&dmac2 0x93>, <&dmac2 0x92>; |
| 482 | dma-names = "tx", "rx", "tx", "rx"; |
| 483 | i2c-scl-internal-delay-ns = <6>; |
| 484 | status = "disabled"; |
| 485 | }; |
| 486 | |
| 487 | i2c2: i2c@e6510000 { |
| 488 | #address-cells = <1>; |
| 489 | #size-cells = <0>; |
| 490 | compatible = "renesas,i2c-r8a774b1", |
| 491 | "renesas,rcar-gen3-i2c"; |
| 492 | reg = <0 0xe6510000 0 0x40>; |
| 493 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| 494 | clocks = <&cpg CPG_MOD 929>; |
| 495 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 496 | resets = <&cpg 929>; |
| 497 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, |
| 498 | <&dmac2 0x95>, <&dmac2 0x94>; |
| 499 | dma-names = "tx", "rx", "tx", "rx"; |
| 500 | i2c-scl-internal-delay-ns = <6>; |
| 501 | status = "disabled"; |
| 502 | }; |
| 503 | |
| 504 | i2c3: i2c@e66d0000 { |
| 505 | #address-cells = <1>; |
| 506 | #size-cells = <0>; |
| 507 | compatible = "renesas,i2c-r8a774b1", |
| 508 | "renesas,rcar-gen3-i2c"; |
| 509 | reg = <0 0xe66d0000 0 0x40>; |
| 510 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| 511 | clocks = <&cpg CPG_MOD 928>; |
| 512 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 513 | resets = <&cpg 928>; |
| 514 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; |
| 515 | dma-names = "tx", "rx"; |
| 516 | i2c-scl-internal-delay-ns = <110>; |
| 517 | status = "disabled"; |
| 518 | }; |
| 519 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 520 | i2c4: i2c@e66d8000 { |
| 521 | #address-cells = <1>; |
| 522 | #size-cells = <0>; |
Biju Das | 070302d | 2019-09-24 09:22:50 +0100 | [diff] [blame] | 523 | compatible = "renesas,i2c-r8a774b1", |
| 524 | "renesas,rcar-gen3-i2c"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 525 | reg = <0 0xe66d8000 0 0x40>; |
Biju Das | 070302d | 2019-09-24 09:22:50 +0100 | [diff] [blame] | 526 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 527 | clocks = <&cpg CPG_MOD 927>; |
| 528 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 529 | resets = <&cpg 927>; |
| 530 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; |
| 531 | dma-names = "tx", "rx"; |
| 532 | i2c-scl-internal-delay-ns = <110>; |
| 533 | status = "disabled"; |
| 534 | }; |
| 535 | |
| 536 | i2c5: i2c@e66e0000 { |
| 537 | #address-cells = <1>; |
| 538 | #size-cells = <0>; |
| 539 | compatible = "renesas,i2c-r8a774b1", |
| 540 | "renesas,rcar-gen3-i2c"; |
| 541 | reg = <0 0xe66e0000 0 0x40>; |
| 542 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 543 | clocks = <&cpg CPG_MOD 919>; |
| 544 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 545 | resets = <&cpg 919>; |
| 546 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; |
| 547 | dma-names = "tx", "rx"; |
| 548 | i2c-scl-internal-delay-ns = <110>; |
| 549 | status = "disabled"; |
| 550 | }; |
| 551 | |
| 552 | i2c6: i2c@e66e8000 { |
| 553 | #address-cells = <1>; |
| 554 | #size-cells = <0>; |
| 555 | compatible = "renesas,i2c-r8a774b1", |
| 556 | "renesas,rcar-gen3-i2c"; |
| 557 | reg = <0 0xe66e8000 0 0x40>; |
| 558 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 559 | clocks = <&cpg CPG_MOD 918>; |
| 560 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 561 | resets = <&cpg 918>; |
| 562 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; |
| 563 | dma-names = "tx", "rx"; |
| 564 | i2c-scl-internal-delay-ns = <6>; |
| 565 | status = "disabled"; |
| 566 | }; |
| 567 | |
| 568 | i2c_dvfs: i2c@e60b0000 { |
| 569 | #address-cells = <1>; |
| 570 | #size-cells = <0>; |
| 571 | compatible = "renesas,iic-r8a774b1", |
| 572 | "renesas,rcar-gen3-iic", |
| 573 | "renesas,rmobile-iic"; |
| 574 | reg = <0 0xe60b0000 0 0x425>; |
| 575 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 576 | clocks = <&cpg CPG_MOD 926>; |
| 577 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 578 | resets = <&cpg 926>; |
| 579 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; |
| 580 | dma-names = "tx", "rx"; |
| 581 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | hscif0: serial@e6540000 { |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 585 | compatible = "renesas,hscif-r8a774b1", |
| 586 | "renesas,rcar-gen3-hscif", |
| 587 | "renesas,hscif"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 588 | reg = <0 0xe6540000 0 0x60>; |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 589 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| 590 | clocks = <&cpg CPG_MOD 520>, |
| 591 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 592 | <&scif_clk>; |
| 593 | clock-names = "fck", "brg_int", "scif_clk"; |
| 594 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, |
| 595 | <&dmac2 0x31>, <&dmac2 0x30>; |
| 596 | dma-names = "tx", "rx", "tx", "rx"; |
| 597 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 598 | resets = <&cpg 520>; |
| 599 | status = "disabled"; |
| 600 | }; |
| 601 | |
| 602 | hscif1: serial@e6550000 { |
| 603 | compatible = "renesas,hscif-r8a774b1", |
| 604 | "renesas,rcar-gen3-hscif", |
| 605 | "renesas,hscif"; |
| 606 | reg = <0 0xe6550000 0 0x60>; |
| 607 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| 608 | clocks = <&cpg CPG_MOD 519>, |
| 609 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 610 | <&scif_clk>; |
| 611 | clock-names = "fck", "brg_int", "scif_clk"; |
| 612 | dmas = <&dmac1 0x33>, <&dmac1 0x32>, |
| 613 | <&dmac2 0x33>, <&dmac2 0x32>; |
| 614 | dma-names = "tx", "rx", "tx", "rx"; |
| 615 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 616 | resets = <&cpg 519>; |
| 617 | status = "disabled"; |
| 618 | }; |
| 619 | |
| 620 | hscif2: serial@e6560000 { |
| 621 | compatible = "renesas,hscif-r8a774b1", |
| 622 | "renesas,rcar-gen3-hscif", |
| 623 | "renesas,hscif"; |
| 624 | reg = <0 0xe6560000 0 0x60>; |
| 625 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| 626 | clocks = <&cpg CPG_MOD 518>, |
| 627 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 628 | <&scif_clk>; |
| 629 | clock-names = "fck", "brg_int", "scif_clk"; |
| 630 | dmas = <&dmac1 0x35>, <&dmac1 0x34>, |
| 631 | <&dmac2 0x35>, <&dmac2 0x34>; |
| 632 | dma-names = "tx", "rx", "tx", "rx"; |
| 633 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 634 | resets = <&cpg 518>; |
| 635 | status = "disabled"; |
| 636 | }; |
| 637 | |
| 638 | hscif3: serial@e66a0000 { |
| 639 | compatible = "renesas,hscif-r8a774b1", |
| 640 | "renesas,rcar-gen3-hscif", |
| 641 | "renesas,hscif"; |
| 642 | reg = <0 0xe66a0000 0 0x60>; |
| 643 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| 644 | clocks = <&cpg CPG_MOD 517>, |
| 645 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 646 | <&scif_clk>; |
| 647 | clock-names = "fck", "brg_int", "scif_clk"; |
| 648 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; |
| 649 | dma-names = "tx", "rx"; |
| 650 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 651 | resets = <&cpg 517>; |
| 652 | status = "disabled"; |
| 653 | }; |
| 654 | |
| 655 | hscif4: serial@e66b0000 { |
| 656 | compatible = "renesas,hscif-r8a774b1", |
| 657 | "renesas,rcar-gen3-hscif", |
| 658 | "renesas,hscif"; |
| 659 | reg = <0 0xe66b0000 0 0x60>; |
| 660 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| 661 | clocks = <&cpg CPG_MOD 516>, |
| 662 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 663 | <&scif_clk>; |
| 664 | clock-names = "fck", "brg_int", "scif_clk"; |
| 665 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; |
| 666 | dma-names = "tx", "rx"; |
| 667 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 668 | resets = <&cpg 516>; |
| 669 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 670 | }; |
| 671 | |
| 672 | hsusb: usb@e6590000 { |
| 673 | reg = <0 0xe6590000 0 0x200>; |
| 674 | /* placeholder */ |
| 675 | }; |
| 676 | |
| 677 | usb3_phy0: usb-phy@e65ee000 { |
| 678 | reg = <0 0xe65ee000 0 0x90>; |
| 679 | #phy-cells = <0>; |
| 680 | /* placeholder */ |
| 681 | }; |
| 682 | |
Biju Das | fd863e5 | 2019-09-30 09:18:43 +0100 | [diff] [blame] | 683 | dmac0: dma-controller@e6700000 { |
| 684 | compatible = "renesas,dmac-r8a774b1", |
| 685 | "renesas,rcar-dmac"; |
| 686 | reg = <0 0xe6700000 0 0x10000>; |
| 687 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| 688 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 689 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 690 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 691 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 692 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 693 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 694 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 695 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 696 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 697 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 698 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 699 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 700 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 701 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 702 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| 703 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| 704 | interrupt-names = "error", |
| 705 | "ch0", "ch1", "ch2", "ch3", |
| 706 | "ch4", "ch5", "ch6", "ch7", |
| 707 | "ch8", "ch9", "ch10", "ch11", |
| 708 | "ch12", "ch13", "ch14", "ch15"; |
| 709 | clocks = <&cpg CPG_MOD 219>; |
| 710 | clock-names = "fck"; |
| 711 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 712 | resets = <&cpg 219>; |
| 713 | #dma-cells = <1>; |
| 714 | dma-channels = <16>; |
Biju Das | c655889 | 2019-09-24 09:22:54 +0100 | [diff] [blame] | 715 | iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| 716 | <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, |
| 717 | <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, |
| 718 | <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, |
| 719 | <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, |
| 720 | <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, |
| 721 | <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, |
| 722 | <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; |
Biju Das | fd863e5 | 2019-09-30 09:18:43 +0100 | [diff] [blame] | 723 | }; |
| 724 | |
| 725 | dmac1: dma-controller@e7300000 { |
| 726 | compatible = "renesas,dmac-r8a774b1", |
| 727 | "renesas,rcar-dmac"; |
| 728 | reg = <0 0xe7300000 0 0x10000>; |
| 729 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 730 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 731 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 732 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 733 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| 734 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| 735 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| 736 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| 737 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| 738 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| 739 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| 740 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| 741 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| 742 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| 743 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| 744 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| 745 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| 746 | interrupt-names = "error", |
| 747 | "ch0", "ch1", "ch2", "ch3", |
| 748 | "ch4", "ch5", "ch6", "ch7", |
| 749 | "ch8", "ch9", "ch10", "ch11", |
| 750 | "ch12", "ch13", "ch14", "ch15"; |
| 751 | clocks = <&cpg CPG_MOD 218>; |
| 752 | clock-names = "fck"; |
| 753 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 754 | resets = <&cpg 218>; |
| 755 | #dma-cells = <1>; |
| 756 | dma-channels = <16>; |
Biju Das | c655889 | 2019-09-24 09:22:54 +0100 | [diff] [blame] | 757 | iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| 758 | <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, |
| 759 | <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, |
| 760 | <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, |
| 761 | <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, |
| 762 | <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, |
| 763 | <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, |
| 764 | <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; |
Biju Das | fd863e5 | 2019-09-30 09:18:43 +0100 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | dmac2: dma-controller@e7310000 { |
| 768 | compatible = "renesas,dmac-r8a774b1", |
| 769 | "renesas,rcar-dmac"; |
| 770 | reg = <0 0xe7310000 0 0x10000>; |
| 771 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| 772 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| 773 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| 774 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| 775 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| 776 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| 777 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| 778 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| 779 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| 780 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| 781 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| 782 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| 783 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| 784 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| 785 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| 786 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| 787 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| 788 | interrupt-names = "error", |
| 789 | "ch0", "ch1", "ch2", "ch3", |
| 790 | "ch4", "ch5", "ch6", "ch7", |
| 791 | "ch8", "ch9", "ch10", "ch11", |
| 792 | "ch12", "ch13", "ch14", "ch15"; |
| 793 | clocks = <&cpg CPG_MOD 217>; |
| 794 | clock-names = "fck"; |
| 795 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 796 | resets = <&cpg 217>; |
| 797 | #dma-cells = <1>; |
| 798 | dma-channels = <16>; |
Biju Das | c655889 | 2019-09-24 09:22:54 +0100 | [diff] [blame] | 799 | iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| 800 | <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, |
| 801 | <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, |
| 802 | <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, |
| 803 | <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, |
| 804 | <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, |
| 805 | <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, |
| 806 | <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; |
Biju Das | fd863e5 | 2019-09-30 09:18:43 +0100 | [diff] [blame] | 807 | }; |
| 808 | |
Biju Das | 63093a8 | 2019-09-24 09:22:51 +0100 | [diff] [blame] | 809 | ipmmu_ds0: mmu@e6740000 { |
| 810 | compatible = "renesas,ipmmu-r8a774b1"; |
| 811 | reg = <0 0xe6740000 0 0x1000>; |
| 812 | renesas,ipmmu-main = <&ipmmu_mm 0>; |
| 813 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 814 | #iommu-cells = <1>; |
| 815 | }; |
| 816 | |
| 817 | ipmmu_ds1: mmu@e7740000 { |
| 818 | compatible = "renesas,ipmmu-r8a774b1"; |
| 819 | reg = <0 0xe7740000 0 0x1000>; |
| 820 | renesas,ipmmu-main = <&ipmmu_mm 1>; |
| 821 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 822 | #iommu-cells = <1>; |
| 823 | }; |
| 824 | |
| 825 | ipmmu_hc: mmu@e6570000 { |
| 826 | compatible = "renesas,ipmmu-r8a774b1"; |
| 827 | reg = <0 0xe6570000 0 0x1000>; |
| 828 | renesas,ipmmu-main = <&ipmmu_mm 2>; |
| 829 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 830 | #iommu-cells = <1>; |
| 831 | }; |
| 832 | |
| 833 | ipmmu_mm: mmu@e67b0000 { |
| 834 | compatible = "renesas,ipmmu-r8a774b1"; |
| 835 | reg = <0 0xe67b0000 0 0x1000>; |
| 836 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 837 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| 838 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 839 | #iommu-cells = <1>; |
| 840 | }; |
| 841 | |
| 842 | ipmmu_mp: mmu@ec670000 { |
| 843 | compatible = "renesas,ipmmu-r8a774b1"; |
| 844 | reg = <0 0xec670000 0 0x1000>; |
| 845 | renesas,ipmmu-main = <&ipmmu_mm 4>; |
| 846 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 847 | #iommu-cells = <1>; |
| 848 | }; |
| 849 | |
| 850 | ipmmu_pv0: mmu@fd800000 { |
| 851 | compatible = "renesas,ipmmu-r8a774b1"; |
| 852 | reg = <0 0xfd800000 0 0x1000>; |
| 853 | renesas,ipmmu-main = <&ipmmu_mm 6>; |
| 854 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 855 | #iommu-cells = <1>; |
| 856 | }; |
| 857 | |
| 858 | ipmmu_vc0: mmu@fe6b0000 { |
| 859 | compatible = "renesas,ipmmu-r8a774b1"; |
| 860 | reg = <0 0xfe6b0000 0 0x1000>; |
| 861 | renesas,ipmmu-main = <&ipmmu_mm 12>; |
| 862 | power-domains = <&sysc R8A774B1_PD_A3VC>; |
| 863 | #iommu-cells = <1>; |
| 864 | }; |
| 865 | |
| 866 | ipmmu_vi0: mmu@febd0000 { |
| 867 | compatible = "renesas,ipmmu-r8a774b1"; |
| 868 | reg = <0 0xfebd0000 0 0x1000>; |
| 869 | renesas,ipmmu-main = <&ipmmu_mm 14>; |
| 870 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 871 | #iommu-cells = <1>; |
| 872 | }; |
| 873 | |
| 874 | ipmmu_vp0: mmu@fe990000 { |
| 875 | compatible = "renesas,ipmmu-r8a774b1"; |
| 876 | reg = <0 0xfe990000 0 0x1000>; |
| 877 | renesas,ipmmu-main = <&ipmmu_mm 16>; |
| 878 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 879 | #iommu-cells = <1>; |
| 880 | }; |
| 881 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 882 | avb: ethernet@e6800000 { |
Biju Das | c722d90 | 2019-09-30 09:18:46 +0100 | [diff] [blame] | 883 | compatible = "renesas,etheravb-r8a774b1", |
| 884 | "renesas,etheravb-rcar-gen3"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 885 | reg = <0 0xe6800000 0 0x800>; |
Biju Das | c722d90 | 2019-09-30 09:18:46 +0100 | [diff] [blame] | 886 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| 887 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 888 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 889 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 890 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| 891 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| 892 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| 893 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| 894 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| 895 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| 896 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| 897 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| 898 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| 899 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| 900 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 901 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 902 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 903 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| 904 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| 905 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| 906 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| 907 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| 908 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| 909 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| 910 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 911 | interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| 912 | "ch4", "ch5", "ch6", "ch7", |
| 913 | "ch8", "ch9", "ch10", "ch11", |
| 914 | "ch12", "ch13", "ch14", "ch15", |
| 915 | "ch16", "ch17", "ch18", "ch19", |
| 916 | "ch20", "ch21", "ch22", "ch23", |
| 917 | "ch24"; |
| 918 | clocks = <&cpg CPG_MOD 812>; |
| 919 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 920 | resets = <&cpg 812>; |
| 921 | phy-mode = "rgmii"; |
Biju Das | 79718f9 | 2019-09-24 09:22:55 +0100 | [diff] [blame] | 922 | iommus = <&ipmmu_ds0 16>; |
Biju Das | c722d90 | 2019-09-30 09:18:46 +0100 | [diff] [blame] | 923 | #address-cells = <1>; |
| 924 | #size-cells = <0>; |
| 925 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 926 | }; |
| 927 | |
| 928 | can0: can@e6c30000 { |
| 929 | reg = <0 0xe6c30000 0 0x1000>; |
| 930 | /* placeholder */ |
| 931 | }; |
| 932 | |
| 933 | can1: can@e6c38000 { |
| 934 | reg = <0 0xe6c38000 0 0x1000>; |
| 935 | /* placeholder */ |
| 936 | }; |
| 937 | |
| 938 | canfd: can@e66c0000 { |
| 939 | reg = <0 0xe66c0000 0 0x8000>; |
| 940 | /* placeholder */ |
| 941 | }; |
| 942 | |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 943 | scif0: serial@e6e60000 { |
| 944 | compatible = "renesas,scif-r8a774b1", |
| 945 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 946 | reg = <0 0xe6e60000 0 0x40>; |
| 947 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| 948 | clocks = <&cpg CPG_MOD 207>, |
| 949 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 950 | <&scif_clk>; |
| 951 | clock-names = "fck", "brg_int", "scif_clk"; |
| 952 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| 953 | <&dmac2 0x51>, <&dmac2 0x50>; |
| 954 | dma-names = "tx", "rx", "tx", "rx"; |
| 955 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 956 | resets = <&cpg 207>; |
| 957 | status = "disabled"; |
| 958 | }; |
| 959 | |
| 960 | scif1: serial@e6e68000 { |
| 961 | compatible = "renesas,scif-r8a774b1", |
| 962 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 963 | reg = <0 0xe6e68000 0 0x40>; |
| 964 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| 965 | clocks = <&cpg CPG_MOD 206>, |
| 966 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 967 | <&scif_clk>; |
| 968 | clock-names = "fck", "brg_int", "scif_clk"; |
| 969 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| 970 | <&dmac2 0x53>, <&dmac2 0x52>; |
| 971 | dma-names = "tx", "rx", "tx", "rx"; |
| 972 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 973 | resets = <&cpg 206>; |
| 974 | status = "disabled"; |
| 975 | }; |
| 976 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 977 | scif2: serial@e6e88000 { |
| 978 | compatible = "renesas,scif-r8a774b1", |
| 979 | "renesas,rcar-gen3-scif", "renesas,scif"; |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 980 | reg = <0 0xe6e88000 0 0x40>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 981 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| 982 | clocks = <&cpg CPG_MOD 310>, |
| 983 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 984 | <&scif_clk>; |
| 985 | clock-names = "fck", "brg_int", "scif_clk"; |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 986 | dmas = <&dmac1 0x13>, <&dmac1 0x12>, |
| 987 | <&dmac2 0x13>, <&dmac2 0x12>; |
| 988 | dma-names = "tx", "rx", "tx", "rx"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 989 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 990 | resets = <&cpg 310>; |
| 991 | status = "disabled"; |
| 992 | }; |
| 993 | |
Biju Das | 83e7620 | 2019-09-30 09:18:44 +0100 | [diff] [blame] | 994 | scif3: serial@e6c50000 { |
| 995 | compatible = "renesas,scif-r8a774b1", |
| 996 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 997 | reg = <0 0xe6c50000 0 0x40>; |
| 998 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 999 | clocks = <&cpg CPG_MOD 204>, |
| 1000 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 1001 | <&scif_clk>; |
| 1002 | clock-names = "fck", "brg_int", "scif_clk"; |
| 1003 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| 1004 | dma-names = "tx", "rx"; |
| 1005 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1006 | resets = <&cpg 204>; |
| 1007 | status = "disabled"; |
| 1008 | }; |
| 1009 | |
| 1010 | scif4: serial@e6c40000 { |
| 1011 | compatible = "renesas,scif-r8a774b1", |
| 1012 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 1013 | reg = <0 0xe6c40000 0 0x40>; |
| 1014 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| 1015 | clocks = <&cpg CPG_MOD 203>, |
| 1016 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 1017 | <&scif_clk>; |
| 1018 | clock-names = "fck", "brg_int", "scif_clk"; |
| 1019 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| 1020 | dma-names = "tx", "rx"; |
| 1021 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1022 | resets = <&cpg 203>; |
| 1023 | status = "disabled"; |
| 1024 | }; |
| 1025 | |
| 1026 | scif5: serial@e6f30000 { |
| 1027 | compatible = "renesas,scif-r8a774b1", |
| 1028 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 1029 | reg = <0 0xe6f30000 0 0x40>; |
| 1030 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 1031 | clocks = <&cpg CPG_MOD 202>, |
| 1032 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 1033 | <&scif_clk>; |
| 1034 | clock-names = "fck", "brg_int", "scif_clk"; |
| 1035 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, |
| 1036 | <&dmac2 0x5b>, <&dmac2 0x5a>; |
| 1037 | dma-names = "tx", "rx", "tx", "rx"; |
| 1038 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1039 | resets = <&cpg 202>; |
| 1040 | status = "disabled"; |
| 1041 | }; |
| 1042 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1043 | rcar_sound: sound@ec500000 { |
| 1044 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1045 | <0 0xec5a0000 0 0x100>, /* ADG */ |
| 1046 | <0 0xec540000 0 0x1000>, /* SSIU */ |
| 1047 | <0 0xec541000 0 0x280>, /* SSI */ |
| 1048 | <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ |
| 1049 | |
| 1050 | rcar_sound,ssi { |
| 1051 | ssi0: ssi-0 { }; |
| 1052 | ssi1: ssi-1 { }; |
| 1053 | ssi2: ssi-2 { }; |
| 1054 | ssi3: ssi-3 { }; |
| 1055 | ssi4: ssi-4 { }; |
| 1056 | ssi5: ssi-5 { }; |
| 1057 | ssi6: ssi-6 { }; |
| 1058 | ssi7: ssi-7 { }; |
| 1059 | ssi8: ssi-8 { }; |
| 1060 | ssi9: ssi-9 { }; |
| 1061 | }; |
| 1062 | }; |
| 1063 | |
| 1064 | xhci0: usb@ee000000 { |
| 1065 | reg = <0 0xee000000 0 0xc00>; |
| 1066 | /* placeholder */ |
| 1067 | }; |
| 1068 | |
| 1069 | usb3_peri0: usb@ee020000 { |
| 1070 | reg = <0 0xee020000 0 0x400>; |
| 1071 | /* placeholder */ |
| 1072 | }; |
| 1073 | |
| 1074 | ohci0: usb@ee080000 { |
| 1075 | reg = <0 0xee080000 0 0x100>; |
| 1076 | /* placeholder */ |
| 1077 | }; |
| 1078 | |
| 1079 | ohci1: usb@ee0a0000 { |
| 1080 | reg = <0 0xee0a0000 0 0x100>; |
| 1081 | /* placeholder */ |
| 1082 | }; |
| 1083 | |
| 1084 | ehci0: usb@ee080100 { |
| 1085 | reg = <0 0xee080100 0 0x100>; |
| 1086 | /* placeholder */ |
| 1087 | }; |
| 1088 | |
| 1089 | ehci1: usb@ee0a0100 { |
| 1090 | reg = <0 0xee0a0100 0 0x100>; |
| 1091 | /* placeholder */ |
| 1092 | }; |
| 1093 | |
| 1094 | usb2_phy0: usb-phy@ee080200 { |
| 1095 | reg = <0 0xee080200 0 0x700>; |
| 1096 | /* placeholder */ |
| 1097 | }; |
| 1098 | |
| 1099 | usb2_phy1: usb-phy@ee0a0200 { |
| 1100 | reg = <0 0xee0a0200 0 0x700>; |
| 1101 | /* placeholder */ |
| 1102 | }; |
| 1103 | |
| 1104 | sdhi0: sd@ee100000 { |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1105 | compatible = "renesas,sdhi-r8a774b1", |
| 1106 | "renesas,rcar-gen3-sdhi"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1107 | reg = <0 0xee100000 0 0x2000>; |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1108 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| 1109 | clocks = <&cpg CPG_MOD 314>; |
| 1110 | max-frequency = <200000000>; |
| 1111 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1112 | resets = <&cpg 314>; |
| 1113 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1114 | }; |
| 1115 | |
| 1116 | sdhi1: sd@ee120000 { |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1117 | compatible = "renesas,sdhi-r8a774b1", |
| 1118 | "renesas,rcar-gen3-sdhi"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1119 | reg = <0 0xee120000 0 0x2000>; |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1120 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| 1121 | clocks = <&cpg CPG_MOD 313>; |
| 1122 | max-frequency = <200000000>; |
| 1123 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1124 | resets = <&cpg 313>; |
| 1125 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1126 | }; |
| 1127 | |
| 1128 | sdhi2: sd@ee140000 { |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1129 | compatible = "renesas,sdhi-r8a774b1", |
| 1130 | "renesas,rcar-gen3-sdhi"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1131 | reg = <0 0xee140000 0 0x2000>; |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1132 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| 1133 | clocks = <&cpg CPG_MOD 312>; |
| 1134 | max-frequency = <200000000>; |
| 1135 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1136 | resets = <&cpg 312>; |
| 1137 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1138 | }; |
| 1139 | |
| 1140 | sdhi3: sd@ee160000 { |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1141 | compatible = "renesas,sdhi-r8a774b1", |
| 1142 | "renesas,rcar-gen3-sdhi"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1143 | reg = <0 0xee160000 0 0x2000>; |
Biju Das | 6317736 | 2019-09-24 09:22:49 +0100 | [diff] [blame] | 1144 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 1145 | clocks = <&cpg CPG_MOD 311>; |
| 1146 | max-frequency = <200000000>; |
| 1147 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1148 | resets = <&cpg 311>; |
| 1149 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1150 | }; |
| 1151 | |
| 1152 | gic: interrupt-controller@f1010000 { |
| 1153 | compatible = "arm,gic-400"; |
| 1154 | #interrupt-cells = <3>; |
| 1155 | #address-cells = <0>; |
| 1156 | interrupt-controller; |
| 1157 | reg = <0x0 0xf1010000 0 0x1000>, |
| 1158 | <0x0 0xf1020000 0 0x20000>, |
| 1159 | <0x0 0xf1040000 0 0x20000>, |
| 1160 | <0x0 0xf1060000 0 0x20000>; |
| 1161 | interrupts = <GIC_PPI 9 |
| 1162 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 1163 | clocks = <&cpg CPG_MOD 408>; |
| 1164 | clock-names = "clk"; |
| 1165 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1166 | resets = <&cpg 408>; |
| 1167 | }; |
| 1168 | |
| 1169 | pciec0: pcie@fe000000 { |
| 1170 | reg = <0 0xfe000000 0 0x80000>; |
| 1171 | #address-cells = <3>; |
| 1172 | #size-cells = <2>; |
| 1173 | bus-range = <0x00 0xff>; |
| 1174 | /* placeholder */ |
| 1175 | }; |
| 1176 | |
| 1177 | pciec1: pcie@ee800000 { |
| 1178 | reg = <0 0xee800000 0 0x80000>; |
| 1179 | #address-cells = <3>; |
| 1180 | #size-cells = <2>; |
| 1181 | bus-range = <0x00 0xff>; |
| 1182 | /* placeholder */ |
| 1183 | }; |
| 1184 | |
Biju Das | ab46816 | 2019-10-02 16:20:15 +0100 | [diff] [blame^] | 1185 | fdp1@fe940000 { |
| 1186 | compatible = "renesas,fdp1"; |
| 1187 | reg = <0 0xfe940000 0 0x2400>; |
| 1188 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; |
| 1189 | clocks = <&cpg CPG_MOD 119>; |
| 1190 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1191 | resets = <&cpg 119>; |
| 1192 | renesas,fcp = <&fcpf0>; |
| 1193 | }; |
| 1194 | |
Biju Das | 955ceb5 | 2019-09-24 09:22:52 +0100 | [diff] [blame] | 1195 | fcpf0: fcp@fe950000 { |
| 1196 | compatible = "renesas,fcpf"; |
| 1197 | reg = <0 0xfe950000 0 0x200>; |
| 1198 | clocks = <&cpg CPG_MOD 615>; |
| 1199 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1200 | resets = <&cpg 615>; |
| 1201 | }; |
| 1202 | |
Biju Das | 966607b | 2019-09-24 09:22:53 +0100 | [diff] [blame] | 1203 | vspb: vsp@fe960000 { |
| 1204 | compatible = "renesas,vsp2"; |
| 1205 | reg = <0 0xfe960000 0 0x8000>; |
| 1206 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; |
| 1207 | clocks = <&cpg CPG_MOD 626>; |
| 1208 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1209 | resets = <&cpg 626>; |
| 1210 | |
| 1211 | renesas,fcp = <&fcpvb0>; |
| 1212 | }; |
| 1213 | |
| 1214 | vspi0: vsp@fe9a0000 { |
| 1215 | compatible = "renesas,vsp2"; |
| 1216 | reg = <0 0xfe9a0000 0 0x8000>; |
| 1217 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; |
| 1218 | clocks = <&cpg CPG_MOD 631>; |
| 1219 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1220 | resets = <&cpg 631>; |
| 1221 | |
| 1222 | renesas,fcp = <&fcpvi0>; |
| 1223 | }; |
| 1224 | |
| 1225 | vspd0: vsp@fea20000 { |
| 1226 | compatible = "renesas,vsp2"; |
| 1227 | reg = <0 0xfea20000 0 0x5000>; |
| 1228 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; |
| 1229 | clocks = <&cpg CPG_MOD 623>; |
| 1230 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1231 | resets = <&cpg 623>; |
| 1232 | |
| 1233 | renesas,fcp = <&fcpvd0>; |
| 1234 | }; |
| 1235 | |
| 1236 | vspd1: vsp@fea28000 { |
| 1237 | compatible = "renesas,vsp2"; |
| 1238 | reg = <0 0xfea28000 0 0x5000>; |
| 1239 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; |
| 1240 | clocks = <&cpg CPG_MOD 622>; |
| 1241 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1242 | resets = <&cpg 622>; |
| 1243 | |
| 1244 | renesas,fcp = <&fcpvd1>; |
| 1245 | }; |
| 1246 | |
Biju Das | 955ceb5 | 2019-09-24 09:22:52 +0100 | [diff] [blame] | 1247 | fcpvb0: fcp@fe96f000 { |
| 1248 | compatible = "renesas,fcpv"; |
| 1249 | reg = <0 0xfe96f000 0 0x200>; |
| 1250 | clocks = <&cpg CPG_MOD 607>; |
| 1251 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1252 | resets = <&cpg 607>; |
| 1253 | }; |
| 1254 | |
| 1255 | fcpvd0: fcp@fea27000 { |
| 1256 | compatible = "renesas,fcpv"; |
| 1257 | reg = <0 0xfea27000 0 0x200>; |
| 1258 | clocks = <&cpg CPG_MOD 603>; |
| 1259 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1260 | resets = <&cpg 603>; |
| 1261 | }; |
| 1262 | |
| 1263 | fcpvd1: fcp@fea2f000 { |
| 1264 | compatible = "renesas,fcpv"; |
| 1265 | reg = <0 0xfea2f000 0 0x200>; |
| 1266 | clocks = <&cpg CPG_MOD 602>; |
| 1267 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1268 | resets = <&cpg 602>; |
| 1269 | }; |
| 1270 | |
| 1271 | fcpvi0: fcp@fe9af000 { |
| 1272 | compatible = "renesas,fcpv"; |
| 1273 | reg = <0 0xfe9af000 0 0x200>; |
| 1274 | clocks = <&cpg CPG_MOD 611>; |
| 1275 | power-domains = <&sysc R8A774B1_PD_A3VP>; |
| 1276 | resets = <&cpg 611>; |
| 1277 | }; |
| 1278 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1279 | hdmi0: hdmi@fead0000 { |
Biju Das | 3a02555 | 2019-10-02 16:20:13 +0100 | [diff] [blame] | 1280 | compatible = "renesas,r8a774b1-hdmi", |
| 1281 | "renesas,rcar-gen3-hdmi"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1282 | reg = <0 0xfead0000 0 0x10000>; |
Biju Das | 3a02555 | 2019-10-02 16:20:13 +0100 | [diff] [blame] | 1283 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; |
| 1284 | clocks = <&cpg CPG_MOD 729>, |
| 1285 | <&cpg CPG_CORE R8A774B1_CLK_HDMI>; |
| 1286 | clock-names = "iahb", "isfr"; |
| 1287 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1288 | resets = <&cpg 729>; |
| 1289 | status = "disabled"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1290 | |
| 1291 | ports { |
| 1292 | #address-cells = <1>; |
| 1293 | #size-cells = <0>; |
| 1294 | |
| 1295 | port@0 { |
| 1296 | reg = <0>; |
| 1297 | dw_hdmi0_in: endpoint { |
Biju Das | 3a02555 | 2019-10-02 16:20:13 +0100 | [diff] [blame] | 1298 | remote-endpoint = <&du_out_hdmi0>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1299 | }; |
| 1300 | }; |
| 1301 | port@1 { |
| 1302 | reg = <1>; |
| 1303 | }; |
Biju Das | 3a02555 | 2019-10-02 16:20:13 +0100 | [diff] [blame] | 1304 | port@2 { |
| 1305 | /* HDMI sound */ |
| 1306 | reg = <2>; |
| 1307 | }; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1308 | }; |
| 1309 | }; |
| 1310 | |
| 1311 | du: display@feb00000 { |
Biju Das | 04e4bad | 2019-10-02 16:20:12 +0100 | [diff] [blame] | 1312 | compatible = "renesas,du-r8a774b1"; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1313 | reg = <0 0xfeb00000 0 0x80000>; |
Biju Das | 04e4bad | 2019-10-02 16:20:12 +0100 | [diff] [blame] | 1314 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 1315 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| 1316 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| 1317 | clocks = <&cpg CPG_MOD 724>, |
| 1318 | <&cpg CPG_MOD 723>, |
| 1319 | <&cpg CPG_MOD 721>; |
| 1320 | clock-names = "du.0", "du.1", "du.3"; |
| 1321 | status = "disabled"; |
| 1322 | |
| 1323 | vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1324 | |
| 1325 | ports { |
| 1326 | #address-cells = <1>; |
| 1327 | #size-cells = <0>; |
| 1328 | |
| 1329 | port@0 { |
| 1330 | reg = <0>; |
| 1331 | du_out_rgb: endpoint { |
| 1332 | }; |
| 1333 | }; |
| 1334 | port@1 { |
| 1335 | reg = <1>; |
| 1336 | du_out_hdmi0: endpoint { |
Biju Das | 3a02555 | 2019-10-02 16:20:13 +0100 | [diff] [blame] | 1337 | remote-endpoint = <&dw_hdmi0_in>; |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1338 | }; |
| 1339 | }; |
| 1340 | port@2 { |
| 1341 | reg = <2>; |
| 1342 | du_out_lvds0: endpoint { |
Biju Das | 04e4bad | 2019-10-02 16:20:12 +0100 | [diff] [blame] | 1343 | remote-endpoint = <&lvds0_in>; |
| 1344 | }; |
| 1345 | }; |
| 1346 | }; |
| 1347 | }; |
| 1348 | |
| 1349 | lvds0: lvds@feb90000 { |
| 1350 | compatible = "renesas,r8a774b1-lvds"; |
| 1351 | reg = <0 0xfeb90000 0 0x14>; |
| 1352 | clocks = <&cpg CPG_MOD 727>; |
| 1353 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 1354 | resets = <&cpg 727>; |
| 1355 | status = "disabled"; |
| 1356 | |
| 1357 | ports { |
| 1358 | #address-cells = <1>; |
| 1359 | #size-cells = <0>; |
| 1360 | |
| 1361 | port@0 { |
| 1362 | reg = <0>; |
| 1363 | lvds0_in: endpoint { |
| 1364 | remote-endpoint = <&du_out_lvds0>; |
| 1365 | }; |
| 1366 | }; |
| 1367 | port@1 { |
| 1368 | reg = <1>; |
| 1369 | lvds0_out: endpoint { |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1370 | }; |
| 1371 | }; |
| 1372 | }; |
| 1373 | }; |
| 1374 | |
| 1375 | prr: chipid@fff00044 { |
| 1376 | compatible = "renesas,prr"; |
| 1377 | reg = <0 0xfff00044 0 4>; |
| 1378 | }; |
| 1379 | }; |
| 1380 | |
Biju Das | 95b3547 | 2019-09-23 15:57:26 +0100 | [diff] [blame] | 1381 | thermal-zones { |
| 1382 | sensor_thermal1: sensor-thermal1 { |
| 1383 | polling-delay-passive = <250>; |
| 1384 | polling-delay = <1000>; |
| 1385 | thermal-sensors = <&tsc 0>; |
| 1386 | sustainable-power = <2439>; |
| 1387 | |
| 1388 | trips { |
| 1389 | sensor1_crit: sensor1-crit { |
| 1390 | temperature = <120000>; |
| 1391 | hysteresis = <1000>; |
| 1392 | type = "critical"; |
| 1393 | }; |
| 1394 | }; |
| 1395 | }; |
| 1396 | |
| 1397 | sensor_thermal2: sensor-thermal2 { |
| 1398 | polling-delay-passive = <250>; |
| 1399 | polling-delay = <1000>; |
| 1400 | thermal-sensors = <&tsc 1>; |
| 1401 | sustainable-power = <2439>; |
| 1402 | |
| 1403 | trips { |
| 1404 | sensor2_crit: sensor2-crit { |
| 1405 | temperature = <120000>; |
| 1406 | hysteresis = <1000>; |
| 1407 | type = "critical"; |
| 1408 | }; |
| 1409 | }; |
| 1410 | }; |
| 1411 | |
| 1412 | sensor_thermal3: sensor-thermal3 { |
| 1413 | polling-delay-passive = <250>; |
| 1414 | polling-delay = <1000>; |
| 1415 | thermal-sensors = <&tsc 2>; |
| 1416 | sustainable-power = <2439>; |
| 1417 | |
| 1418 | cooling-maps { |
| 1419 | map0 { |
| 1420 | trip = <&target>; |
| 1421 | cooling-device = <&a57_0 0 2>; |
| 1422 | contribution = <1024>; |
| 1423 | }; |
| 1424 | }; |
| 1425 | trips { |
| 1426 | target: trip-point1 { |
| 1427 | temperature = <100000>; |
| 1428 | hysteresis = <1000>; |
| 1429 | type = "passive"; |
| 1430 | }; |
| 1431 | |
| 1432 | sensor3_crit: sensor3-crit { |
| 1433 | temperature = <120000>; |
| 1434 | hysteresis = <1000>; |
| 1435 | type = "critical"; |
| 1436 | }; |
| 1437 | }; |
| 1438 | }; |
| 1439 | }; |
| 1440 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1441 | timer { |
| 1442 | compatible = "arm,armv8-timer"; |
| 1443 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 1444 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 1445 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 1446 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 1447 | }; |
| 1448 | |
| 1449 | /* External USB clocks - can be overridden by the board */ |
| 1450 | usb3s0_clk: usb3s0 { |
| 1451 | compatible = "fixed-clock"; |
| 1452 | #clock-cells = <0>; |
| 1453 | clock-frequency = <0>; |
| 1454 | }; |
| 1455 | |
| 1456 | usb_extal_clk: usb_extal { |
| 1457 | compatible = "fixed-clock"; |
| 1458 | #clock-cells = <0>; |
| 1459 | clock-frequency = <0>; |
| 1460 | }; |
| 1461 | }; |