Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for the r8a774b1 SoC |
| 4 | * |
| 5 | * Copyright (C) 2019 Renesas Electronics Corp. |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/interrupt-controller/irq.h> |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> |
| 11 | #include <dt-bindings/power/r8a774b1-sysc.h> |
| 12 | |
| 13 | / { |
| 14 | compatible = "renesas,r8a774b1"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | /* |
| 19 | * The external audio clocks are configured as 0 Hz fixed frequency |
| 20 | * clocks by default. |
| 21 | * Boards that provide audio clocks should override them. |
| 22 | */ |
| 23 | audio_clk_a: audio_clk_a { |
| 24 | compatible = "fixed-clock"; |
| 25 | #clock-cells = <0>; |
| 26 | clock-frequency = <0>; |
| 27 | }; |
| 28 | |
| 29 | audio_clk_b: audio_clk_b { |
| 30 | compatible = "fixed-clock"; |
| 31 | #clock-cells = <0>; |
| 32 | clock-frequency = <0>; |
| 33 | }; |
| 34 | |
| 35 | audio_clk_c: audio_clk_c { |
| 36 | compatible = "fixed-clock"; |
| 37 | #clock-cells = <0>; |
| 38 | clock-frequency = <0>; |
| 39 | }; |
| 40 | |
| 41 | /* External CAN clock - to be overridden by boards that provide it */ |
| 42 | can_clk: can { |
| 43 | compatible = "fixed-clock"; |
| 44 | #clock-cells = <0>; |
| 45 | clock-frequency = <0>; |
| 46 | }; |
| 47 | |
| 48 | cpus { |
| 49 | #address-cells = <1>; |
| 50 | #size-cells = <0>; |
| 51 | |
| 52 | a57_0: cpu@0 { |
| 53 | compatible = "arm,cortex-a57"; |
| 54 | reg = <0x0>; |
| 55 | device_type = "cpu"; |
| 56 | power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; |
| 57 | next-level-cache = <&L2_CA57>; |
| 58 | enable-method = "psci"; |
| 59 | #cooling-cells = <2>; |
| 60 | dynamic-power-coefficient = <854>; |
| 61 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
| 62 | }; |
| 63 | |
| 64 | a57_1: cpu@1 { |
| 65 | compatible = "arm,cortex-a57"; |
| 66 | reg = <0x1>; |
| 67 | device_type = "cpu"; |
| 68 | power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; |
| 69 | next-level-cache = <&L2_CA57>; |
| 70 | enable-method = "psci"; |
| 71 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
| 72 | }; |
| 73 | |
| 74 | L2_CA57: cache-controller-0 { |
| 75 | compatible = "cache"; |
| 76 | power-domains = <&sysc R8A774B1_PD_CA57_SCU>; |
| 77 | cache-unified; |
| 78 | cache-level = <2>; |
| 79 | }; |
| 80 | }; |
| 81 | |
| 82 | extal_clk: extal { |
| 83 | compatible = "fixed-clock"; |
| 84 | #clock-cells = <0>; |
| 85 | /* This value must be overridden by the board */ |
| 86 | clock-frequency = <0>; |
| 87 | }; |
| 88 | |
| 89 | extalr_clk: extalr { |
| 90 | compatible = "fixed-clock"; |
| 91 | #clock-cells = <0>; |
| 92 | /* This value must be overridden by the board */ |
| 93 | clock-frequency = <0>; |
| 94 | }; |
| 95 | |
| 96 | /* External PCIe clock - can be overridden by the board */ |
| 97 | pcie_bus_clk: pcie_bus { |
| 98 | compatible = "fixed-clock"; |
| 99 | #clock-cells = <0>; |
| 100 | clock-frequency = <0>; |
| 101 | }; |
| 102 | |
| 103 | pmu_a57 { |
| 104 | compatible = "arm,cortex-a57-pmu"; |
| 105 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 107 | interrupt-affinity = <&a57_0>, <&a57_1>; |
| 108 | }; |
| 109 | |
| 110 | psci { |
| 111 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| 112 | method = "smc"; |
| 113 | }; |
| 114 | |
| 115 | /* External SCIF clock - to be overridden by boards that provide it */ |
| 116 | scif_clk: scif { |
| 117 | compatible = "fixed-clock"; |
| 118 | #clock-cells = <0>; |
| 119 | clock-frequency = <0>; |
| 120 | }; |
| 121 | |
| 122 | soc { |
| 123 | compatible = "simple-bus"; |
| 124 | interrupt-parent = <&gic>; |
| 125 | #address-cells = <2>; |
| 126 | #size-cells = <2>; |
| 127 | ranges; |
| 128 | |
| 129 | rwdt: watchdog@e6020000 { |
| 130 | reg = <0 0xe6020000 0 0x0c>; |
| 131 | /* placeholder */ |
| 132 | }; |
| 133 | |
| 134 | gpio0: gpio@e6050000 { |
| 135 | reg = <0 0xe6050000 0 0x50>; |
| 136 | #gpio-cells = <2>; |
| 137 | gpio-controller; |
| 138 | #interrupt-cells = <2>; |
| 139 | interrupt-controller; |
| 140 | /* placeholder */ |
| 141 | }; |
| 142 | |
| 143 | gpio1: gpio@e6051000 { |
| 144 | reg = <0 0xe6051000 0 0x50>; |
| 145 | #gpio-cells = <2>; |
| 146 | gpio-controller; |
| 147 | #interrupt-cells = <2>; |
| 148 | interrupt-controller; |
| 149 | /* placeholder */ |
| 150 | }; |
| 151 | |
| 152 | gpio2: gpio@e6052000 { |
| 153 | reg = <0 0xe6052000 0 0x50>; |
| 154 | #gpio-cells = <2>; |
| 155 | gpio-controller; |
| 156 | #interrupt-cells = <2>; |
| 157 | interrupt-controller; |
| 158 | /* placeholder */ |
| 159 | }; |
| 160 | |
| 161 | gpio3: gpio@e6053000 { |
| 162 | reg = <0 0xe6053000 0 0x50>; |
| 163 | #gpio-cells = <2>; |
| 164 | gpio-controller; |
| 165 | #interrupt-cells = <2>; |
| 166 | interrupt-controller; |
| 167 | /* placeholder */ |
| 168 | }; |
| 169 | |
| 170 | gpio4: gpio@e6054000 { |
| 171 | reg = <0 0xe6054000 0 0x50>; |
| 172 | #gpio-cells = <2>; |
| 173 | gpio-controller; |
| 174 | #interrupt-cells = <2>; |
| 175 | interrupt-controller; |
| 176 | /* placeholder */ |
| 177 | }; |
| 178 | |
| 179 | gpio5: gpio@e6055000 { |
| 180 | reg = <0 0xe6055000 0 0x50>; |
| 181 | #gpio-cells = <2>; |
| 182 | gpio-controller; |
| 183 | #interrupt-cells = <2>; |
| 184 | interrupt-controller; |
| 185 | /* placeholder */ |
| 186 | }; |
| 187 | |
| 188 | gpio6: gpio@e6055400 { |
| 189 | reg = <0 0xe6055400 0 0x50>; |
| 190 | #gpio-cells = <2>; |
| 191 | gpio-controller; |
| 192 | #interrupt-cells = <2>; |
| 193 | interrupt-controller; |
| 194 | /* placeholder */ |
| 195 | }; |
| 196 | |
| 197 | gpio7: gpio@e6055800 { |
| 198 | reg = <0 0xe6055800 0 0x50>; |
| 199 | #gpio-cells = <2>; |
| 200 | gpio-controller; |
| 201 | #interrupt-cells = <2>; |
| 202 | interrupt-controller; |
| 203 | /* placeholder */ |
| 204 | }; |
| 205 | |
| 206 | pfc: pin-controller@e6060000 { |
| 207 | compatible = "renesas,pfc-r8a774b1"; |
| 208 | reg = <0 0xe6060000 0 0x50c>; |
| 209 | }; |
| 210 | |
| 211 | cpg: clock-controller@e6150000 { |
| 212 | compatible = "renesas,r8a774b1-cpg-mssr"; |
| 213 | reg = <0 0xe6150000 0 0x1000>; |
| 214 | clocks = <&extal_clk>, <&extalr_clk>; |
| 215 | clock-names = "extal", "extalr"; |
| 216 | #clock-cells = <2>; |
| 217 | #power-domain-cells = <0>; |
| 218 | #reset-cells = <1>; |
| 219 | }; |
| 220 | |
| 221 | rst: reset-controller@e6160000 { |
| 222 | compatible = "renesas,r8a774b1-rst"; |
| 223 | reg = <0 0xe6160000 0 0x0200>; |
| 224 | }; |
| 225 | |
| 226 | sysc: system-controller@e6180000 { |
| 227 | compatible = "renesas,r8a774b1-sysc"; |
| 228 | reg = <0 0xe6180000 0 0x0400>; |
| 229 | #power-domain-cells = <1>; |
| 230 | }; |
| 231 | |
| 232 | i2c4: i2c@e66d8000 { |
| 233 | #address-cells = <1>; |
| 234 | #size-cells = <0>; |
| 235 | reg = <0 0xe66d8000 0 0x40>; |
| 236 | /* placeholder */ |
| 237 | }; |
| 238 | |
| 239 | hscif0: serial@e6540000 { |
| 240 | reg = <0 0xe6540000 0 0x60>; |
| 241 | /* placeholder */ |
| 242 | }; |
| 243 | |
| 244 | hsusb: usb@e6590000 { |
| 245 | reg = <0 0xe6590000 0 0x200>; |
| 246 | /* placeholder */ |
| 247 | }; |
| 248 | |
| 249 | usb3_phy0: usb-phy@e65ee000 { |
| 250 | reg = <0 0xe65ee000 0 0x90>; |
| 251 | #phy-cells = <0>; |
| 252 | /* placeholder */ |
| 253 | }; |
| 254 | |
Biju Das | fd863e5 | 2019-09-30 09:18:43 +0100 | [diff] [blame^] | 255 | dmac0: dma-controller@e6700000 { |
| 256 | compatible = "renesas,dmac-r8a774b1", |
| 257 | "renesas,rcar-dmac"; |
| 258 | reg = <0 0xe6700000 0 0x10000>; |
| 259 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| 260 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 261 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 262 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 263 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 264 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 265 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 266 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 267 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 268 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 269 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 270 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 271 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 272 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 273 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 274 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| 275 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| 276 | interrupt-names = "error", |
| 277 | "ch0", "ch1", "ch2", "ch3", |
| 278 | "ch4", "ch5", "ch6", "ch7", |
| 279 | "ch8", "ch9", "ch10", "ch11", |
| 280 | "ch12", "ch13", "ch14", "ch15"; |
| 281 | clocks = <&cpg CPG_MOD 219>; |
| 282 | clock-names = "fck"; |
| 283 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 284 | resets = <&cpg 219>; |
| 285 | #dma-cells = <1>; |
| 286 | dma-channels = <16>; |
| 287 | }; |
| 288 | |
| 289 | dmac1: dma-controller@e7300000 { |
| 290 | compatible = "renesas,dmac-r8a774b1", |
| 291 | "renesas,rcar-dmac"; |
| 292 | reg = <0 0xe7300000 0 0x10000>; |
| 293 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 294 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 295 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 296 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 297 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| 298 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| 299 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| 300 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| 301 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| 302 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| 303 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| 304 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| 305 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| 306 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| 307 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| 308 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| 309 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| 310 | interrupt-names = "error", |
| 311 | "ch0", "ch1", "ch2", "ch3", |
| 312 | "ch4", "ch5", "ch6", "ch7", |
| 313 | "ch8", "ch9", "ch10", "ch11", |
| 314 | "ch12", "ch13", "ch14", "ch15"; |
| 315 | clocks = <&cpg CPG_MOD 218>; |
| 316 | clock-names = "fck"; |
| 317 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 318 | resets = <&cpg 218>; |
| 319 | #dma-cells = <1>; |
| 320 | dma-channels = <16>; |
| 321 | }; |
| 322 | |
| 323 | dmac2: dma-controller@e7310000 { |
| 324 | compatible = "renesas,dmac-r8a774b1", |
| 325 | "renesas,rcar-dmac"; |
| 326 | reg = <0 0xe7310000 0 0x10000>; |
| 327 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| 328 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| 329 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| 330 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| 331 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| 332 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| 333 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| 334 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| 335 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| 336 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| 337 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| 338 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| 339 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| 340 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| 341 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| 342 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| 343 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| 344 | interrupt-names = "error", |
| 345 | "ch0", "ch1", "ch2", "ch3", |
| 346 | "ch4", "ch5", "ch6", "ch7", |
| 347 | "ch8", "ch9", "ch10", "ch11", |
| 348 | "ch12", "ch13", "ch14", "ch15"; |
| 349 | clocks = <&cpg CPG_MOD 217>; |
| 350 | clock-names = "fck"; |
| 351 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 352 | resets = <&cpg 217>; |
| 353 | #dma-cells = <1>; |
| 354 | dma-channels = <16>; |
| 355 | }; |
| 356 | |
Biju Das | 9b33e30 | 2019-09-27 14:06:24 +0100 | [diff] [blame] | 357 | avb: ethernet@e6800000 { |
| 358 | reg = <0 0xe6800000 0 0x800>; |
| 359 | /* placeholder */ |
| 360 | }; |
| 361 | |
| 362 | can0: can@e6c30000 { |
| 363 | reg = <0 0xe6c30000 0 0x1000>; |
| 364 | /* placeholder */ |
| 365 | }; |
| 366 | |
| 367 | can1: can@e6c38000 { |
| 368 | reg = <0 0xe6c38000 0 0x1000>; |
| 369 | /* placeholder */ |
| 370 | }; |
| 371 | |
| 372 | canfd: can@e66c0000 { |
| 373 | reg = <0 0xe66c0000 0 0x8000>; |
| 374 | /* placeholder */ |
| 375 | }; |
| 376 | |
| 377 | scif2: serial@e6e88000 { |
| 378 | compatible = "renesas,scif-r8a774b1", |
| 379 | "renesas,rcar-gen3-scif", "renesas,scif"; |
| 380 | reg = <0 0xe6e88000 0 64>; |
| 381 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| 382 | clocks = <&cpg CPG_MOD 310>, |
| 383 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| 384 | <&scif_clk>; |
| 385 | clock-names = "fck", "brg_int", "scif_clk"; |
| 386 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 387 | resets = <&cpg 310>; |
| 388 | status = "disabled"; |
| 389 | }; |
| 390 | |
| 391 | rcar_sound: sound@ec500000 { |
| 392 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 393 | <0 0xec5a0000 0 0x100>, /* ADG */ |
| 394 | <0 0xec540000 0 0x1000>, /* SSIU */ |
| 395 | <0 0xec541000 0 0x280>, /* SSI */ |
| 396 | <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ |
| 397 | |
| 398 | rcar_sound,ssi { |
| 399 | ssi0: ssi-0 { }; |
| 400 | ssi1: ssi-1 { }; |
| 401 | ssi2: ssi-2 { }; |
| 402 | ssi3: ssi-3 { }; |
| 403 | ssi4: ssi-4 { }; |
| 404 | ssi5: ssi-5 { }; |
| 405 | ssi6: ssi-6 { }; |
| 406 | ssi7: ssi-7 { }; |
| 407 | ssi8: ssi-8 { }; |
| 408 | ssi9: ssi-9 { }; |
| 409 | }; |
| 410 | }; |
| 411 | |
| 412 | xhci0: usb@ee000000 { |
| 413 | reg = <0 0xee000000 0 0xc00>; |
| 414 | /* placeholder */ |
| 415 | }; |
| 416 | |
| 417 | usb3_peri0: usb@ee020000 { |
| 418 | reg = <0 0xee020000 0 0x400>; |
| 419 | /* placeholder */ |
| 420 | }; |
| 421 | |
| 422 | ohci0: usb@ee080000 { |
| 423 | reg = <0 0xee080000 0 0x100>; |
| 424 | /* placeholder */ |
| 425 | }; |
| 426 | |
| 427 | ohci1: usb@ee0a0000 { |
| 428 | reg = <0 0xee0a0000 0 0x100>; |
| 429 | /* placeholder */ |
| 430 | }; |
| 431 | |
| 432 | ehci0: usb@ee080100 { |
| 433 | reg = <0 0xee080100 0 0x100>; |
| 434 | /* placeholder */ |
| 435 | }; |
| 436 | |
| 437 | ehci1: usb@ee0a0100 { |
| 438 | reg = <0 0xee0a0100 0 0x100>; |
| 439 | /* placeholder */ |
| 440 | }; |
| 441 | |
| 442 | usb2_phy0: usb-phy@ee080200 { |
| 443 | reg = <0 0xee080200 0 0x700>; |
| 444 | /* placeholder */ |
| 445 | }; |
| 446 | |
| 447 | usb2_phy1: usb-phy@ee0a0200 { |
| 448 | reg = <0 0xee0a0200 0 0x700>; |
| 449 | /* placeholder */ |
| 450 | }; |
| 451 | |
| 452 | sdhi0: sd@ee100000 { |
| 453 | reg = <0 0xee100000 0 0x2000>; |
| 454 | /* placeholder */ |
| 455 | }; |
| 456 | |
| 457 | sdhi1: sd@ee120000 { |
| 458 | reg = <0 0xee120000 0 0x2000>; |
| 459 | /* placeholder */ |
| 460 | }; |
| 461 | |
| 462 | sdhi2: sd@ee140000 { |
| 463 | reg = <0 0xee140000 0 0x2000>; |
| 464 | /* placeholder */ |
| 465 | }; |
| 466 | |
| 467 | sdhi3: sd@ee160000 { |
| 468 | reg = <0 0xee160000 0 0x2000>; |
| 469 | /* placeholder */ |
| 470 | }; |
| 471 | |
| 472 | gic: interrupt-controller@f1010000 { |
| 473 | compatible = "arm,gic-400"; |
| 474 | #interrupt-cells = <3>; |
| 475 | #address-cells = <0>; |
| 476 | interrupt-controller; |
| 477 | reg = <0x0 0xf1010000 0 0x1000>, |
| 478 | <0x0 0xf1020000 0 0x20000>, |
| 479 | <0x0 0xf1040000 0 0x20000>, |
| 480 | <0x0 0xf1060000 0 0x20000>; |
| 481 | interrupts = <GIC_PPI 9 |
| 482 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 483 | clocks = <&cpg CPG_MOD 408>; |
| 484 | clock-names = "clk"; |
| 485 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| 486 | resets = <&cpg 408>; |
| 487 | }; |
| 488 | |
| 489 | pciec0: pcie@fe000000 { |
| 490 | reg = <0 0xfe000000 0 0x80000>; |
| 491 | #address-cells = <3>; |
| 492 | #size-cells = <2>; |
| 493 | bus-range = <0x00 0xff>; |
| 494 | /* placeholder */ |
| 495 | }; |
| 496 | |
| 497 | pciec1: pcie@ee800000 { |
| 498 | reg = <0 0xee800000 0 0x80000>; |
| 499 | #address-cells = <3>; |
| 500 | #size-cells = <2>; |
| 501 | bus-range = <0x00 0xff>; |
| 502 | /* placeholder */ |
| 503 | }; |
| 504 | |
| 505 | hdmi0: hdmi@fead0000 { |
| 506 | reg = <0 0xfead0000 0 0x10000>; |
| 507 | |
| 508 | ports { |
| 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
| 511 | |
| 512 | port@0 { |
| 513 | reg = <0>; |
| 514 | dw_hdmi0_in: endpoint { |
| 515 | }; |
| 516 | }; |
| 517 | port@1 { |
| 518 | reg = <1>; |
| 519 | }; |
| 520 | }; |
| 521 | }; |
| 522 | |
| 523 | du: display@feb00000 { |
| 524 | reg = <0 0xfeb00000 0 0x80000>; |
| 525 | |
| 526 | ports { |
| 527 | #address-cells = <1>; |
| 528 | #size-cells = <0>; |
| 529 | |
| 530 | port@0 { |
| 531 | reg = <0>; |
| 532 | du_out_rgb: endpoint { |
| 533 | }; |
| 534 | }; |
| 535 | port@1 { |
| 536 | reg = <1>; |
| 537 | du_out_hdmi0: endpoint { |
| 538 | }; |
| 539 | }; |
| 540 | port@2 { |
| 541 | reg = <2>; |
| 542 | du_out_lvds0: endpoint { |
| 543 | }; |
| 544 | }; |
| 545 | }; |
| 546 | }; |
| 547 | |
| 548 | prr: chipid@fff00044 { |
| 549 | compatible = "renesas,prr"; |
| 550 | reg = <0 0xfff00044 0 4>; |
| 551 | }; |
| 552 | }; |
| 553 | |
| 554 | timer { |
| 555 | compatible = "arm,armv8-timer"; |
| 556 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 557 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 558 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 559 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 560 | }; |
| 561 | |
| 562 | /* External USB clocks - can be overridden by the board */ |
| 563 | usb3s0_clk: usb3s0 { |
| 564 | compatible = "fixed-clock"; |
| 565 | #clock-cells = <0>; |
| 566 | clock-frequency = <0>; |
| 567 | }; |
| 568 | |
| 569 | usb_extal_clk: usb_extal { |
| 570 | compatible = "fixed-clock"; |
| 571 | #clock-cells = <0>; |
| 572 | clock-frequency = <0>; |
| 573 | }; |
| 574 | }; |