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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7f59b319111bbc3a5f32730c8a43b201e9522f52 / . / arch / arm / boot / dts / imx23.dtsi
blob: ac2a9da62b6ce81e4130c44185300ac95c31b2ca [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]12#include "imx23-pinfunc.h"
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]13
14/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]15 #address-cells = <1>;
16 #size-cells = <1>;
17
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]18 interrupt-parent = <&icoll>;
19
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]24 serial0 = &auart0;
25 serial1 = &auart1;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]26 spi0 = &ssp0;
27 spi1 = &ssp1;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]28 usbphy0 = &usbphy0;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]29 };
30
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]31 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]32 #address-cells = <0>;
33 #size-cells = <0>;
34
35 cpu {
36 compatible = "arm,arm926ej-s";
37 device_type = "cpu";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]38 };
39 };
40
41 apb@80000000 {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 reg = <0x80000000 0x80000>;
46 ranges;
47
48 apbh@80000000 {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 reg = <0x80000000 0x40000>;
53 ranges;
54
55 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]56 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x80000000 0x2000>;
60 };
61
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]62 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]63 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]64 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]65 interrupts = <0 14 20 0
66 13 13 13 13>;
67 interrupt-names = "empty", "ssp0", "ssp1", "empty",
68 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
69 #dma-cells = <1>;
70 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]71 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]72 };
73
74 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]75 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]76 status = "disabled";
77 };
78
Marek Vasuta217c462012-06-09 01:21:55 +0200[diff] [blame]79 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]80 compatible = "fsl,imx23-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]84 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]85 interrupts = <56>;
86 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]87 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]88 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]89 dmas = <&dma_apbh 4>;
90 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]91 status = "disabled";
92 };
93
94 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]95 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]96 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]97 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]98 dmas = <&dma_apbh 1>;
99 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]100 status = "disabled";
101 };
102
103 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]104 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]105 status = "disabled";
106 };
107
108 pinctrl@80018000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]111 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]112 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]113
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]114 gpio0: gpio@0 {
115 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]116 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]117 interrupts = <16>;
118 gpio-controller;
119 #gpio-cells = <2>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 };
123
124 gpio1: gpio@1 {
125 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]126 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]127 interrupts = <17>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 };
133
134 gpio2: gpio@2 {
135 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]136 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]137 interrupts = <18>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]144 duart_pins_a: duart@0 {
145 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]146 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]147 MX23_PAD_PWM0__DUART_RX
148 MX23_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]149 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]150 fsl,drive-strength = <MXS_DRIVE_4mA>;
151 fsl,voltage = <MXS_VOLTAGE_HIGH>;
152 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]153 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]154
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]155 auart0_pins_a: auart0@0 {
156 reg = <0>;
157 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]158 MX23_PAD_AUART1_RX__AUART1_RX
159 MX23_PAD_AUART1_TX__AUART1_TX
160 MX23_PAD_AUART1_CTS__AUART1_CTS
161 MX23_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]162 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]163 fsl,drive-strength = <MXS_DRIVE_4mA>;
164 fsl,voltage = <MXS_VOLTAGE_HIGH>;
165 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]166 };
167
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]168 auart0_2pins_a: auart0-2pins@0 {
169 reg = <0>;
170 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]171 MX23_PAD_I2C_SCL__AUART1_TX
172 MX23_PAD_I2C_SDA__AUART1_RX
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]173 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]174 fsl,drive-strength = <MXS_DRIVE_4mA>;
175 fsl,voltage = <MXS_VOLTAGE_HIGH>;
176 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]177 };
178
Marek Vasutd33c7312016-06-09 21:43:11 +0200[diff] [blame]179 auart1_2pins_a: auart1-2pins@0 {
180 reg = <0>;
181 fsl,pinmux-ids = <
182 MX23_PAD_GPMI_D14__AUART2_RX
183 MX23_PAD_GPMI_D15__AUART2_TX
184 >;
185 fsl,drive-strength = <MXS_DRIVE_4mA>;
186 fsl,voltage = <MXS_VOLTAGE_HIGH>;
187 fsl,pull-up = <MXS_PULL_DISABLE>;
188 };
189
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]190 gpmi_pins_a: gpmi-nand@0 {
191 reg = <0>;
192 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]193 MX23_PAD_GPMI_D00__GPMI_D00
194 MX23_PAD_GPMI_D01__GPMI_D01
195 MX23_PAD_GPMI_D02__GPMI_D02
196 MX23_PAD_GPMI_D03__GPMI_D03
197 MX23_PAD_GPMI_D04__GPMI_D04
198 MX23_PAD_GPMI_D05__GPMI_D05
199 MX23_PAD_GPMI_D06__GPMI_D06
200 MX23_PAD_GPMI_D07__GPMI_D07
201 MX23_PAD_GPMI_CLE__GPMI_CLE
202 MX23_PAD_GPMI_ALE__GPMI_ALE
203 MX23_PAD_GPMI_RDY0__GPMI_RDY0
204 MX23_PAD_GPMI_RDY1__GPMI_RDY1
205 MX23_PAD_GPMI_WPN__GPMI_WPN
206 MX23_PAD_GPMI_WRN__GPMI_WRN
207 MX23_PAD_GPMI_RDN__GPMI_RDN
208 MX23_PAD_GPMI_CE1N__GPMI_CE1N
209 MX23_PAD_GPMI_CE0N__GPMI_CE0N
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]210 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]211 fsl,drive-strength = <MXS_DRIVE_4mA>;
212 fsl,voltage = <MXS_VOLTAGE_HIGH>;
213 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]214 };
215
216 gpmi_pins_fixup: gpmi-pins-fixup {
217 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]218 MX23_PAD_GPMI_WPN__GPMI_WPN
219 MX23_PAD_GPMI_WRN__GPMI_WRN
220 MX23_PAD_GPMI_RDN__GPMI_RDN
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]221 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]222 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]223 };
224
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]225 mmc0_4bit_pins_a: mmc0-4bit@0 {
226 reg = <0>;
227 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]228 MX23_PAD_SSP1_DATA0__SSP1_DATA0
229 MX23_PAD_SSP1_DATA1__SSP1_DATA1
230 MX23_PAD_SSP1_DATA2__SSP1_DATA2
231 MX23_PAD_SSP1_DATA3__SSP1_DATA3
232 MX23_PAD_SSP1_CMD__SSP1_CMD
233 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]234 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]235 fsl,drive-strength = <MXS_DRIVE_8mA>;
236 fsl,voltage = <MXS_VOLTAGE_HIGH>;
237 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]238 };
239
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]240 mmc0_8bit_pins_a: mmc0-8bit@0 {
241 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]242 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]243 MX23_PAD_SSP1_DATA0__SSP1_DATA0
244 MX23_PAD_SSP1_DATA1__SSP1_DATA1
245 MX23_PAD_SSP1_DATA2__SSP1_DATA2
246 MX23_PAD_SSP1_DATA3__SSP1_DATA3
247 MX23_PAD_GPMI_D08__SSP1_DATA4
248 MX23_PAD_GPMI_D09__SSP1_DATA5
249 MX23_PAD_GPMI_D10__SSP1_DATA6
250 MX23_PAD_GPMI_D11__SSP1_DATA7
251 MX23_PAD_SSP1_CMD__SSP1_CMD
252 MX23_PAD_SSP1_DETECT__SSP1_DETECT
253 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]254 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]255 fsl,drive-strength = <MXS_DRIVE_8mA>;
256 fsl,voltage = <MXS_VOLTAGE_HIGH>;
257 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]258 };
259
260 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]261 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]262 MX23_PAD_SSP1_DETECT__SSP1_DETECT
263 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]264 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]265 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]266 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]267
Marek Vasut1ebcb162016-06-09 21:43:10 +0200[diff] [blame]268 mmc1_4bit_pins_a: mmc1-4bit@0 {
269 reg = <0>;
270 fsl,pinmux-ids = <
271 MX23_PAD_GPMI_D00__SSP2_DATA0
272 MX23_PAD_GPMI_D01__SSP2_DATA1
273 MX23_PAD_GPMI_D02__SSP2_DATA2
274 MX23_PAD_GPMI_D03__SSP2_DATA3
275 MX23_PAD_GPMI_RDY1__SSP2_CMD
276 MX23_PAD_GPMI_WRN__SSP2_SCK
277 >;
278 fsl,drive-strength = <MXS_DRIVE_8mA>;
279 fsl,voltage = <MXS_VOLTAGE_HIGH>;
280 fsl,pull-up = <MXS_PULL_ENABLE>;
281 };
282
283 mmc1_8bit_pins_a: mmc1-8bit@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 MX23_PAD_GPMI_D00__SSP2_DATA0
287 MX23_PAD_GPMI_D01__SSP2_DATA1
288 MX23_PAD_GPMI_D02__SSP2_DATA2
289 MX23_PAD_GPMI_D03__SSP2_DATA3
290 MX23_PAD_GPMI_D04__SSP2_DATA4
291 MX23_PAD_GPMI_D05__SSP2_DATA5
292 MX23_PAD_GPMI_D06__SSP2_DATA6
293 MX23_PAD_GPMI_D07__SSP2_DATA7
294 MX23_PAD_GPMI_RDY1__SSP2_CMD
295 MX23_PAD_GPMI_WRN__SSP2_SCK
296 >;
297 fsl,drive-strength = <MXS_DRIVE_8mA>;
298 fsl,voltage = <MXS_VOLTAGE_HIGH>;
299 fsl,pull-up = <MXS_PULL_ENABLE>;
300 };
301
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]302 pwm2_pins_a: pwm2@0 {
303 reg = <0>;
304 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]305 MX23_PAD_PWM2__PWM2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]306 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]307 fsl,drive-strength = <MXS_DRIVE_4mA>;
308 fsl,voltage = <MXS_VOLTAGE_HIGH>;
309 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]310 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]311
312 lcdif_24bit_pins_a: lcdif-24bit@0 {
313 reg = <0>;
314 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]315 MX23_PAD_LCD_D00__LCD_D00
316 MX23_PAD_LCD_D01__LCD_D01
317 MX23_PAD_LCD_D02__LCD_D02
318 MX23_PAD_LCD_D03__LCD_D03
319 MX23_PAD_LCD_D04__LCD_D04
320 MX23_PAD_LCD_D05__LCD_D05
321 MX23_PAD_LCD_D06__LCD_D06
322 MX23_PAD_LCD_D07__LCD_D07
323 MX23_PAD_LCD_D08__LCD_D08
324 MX23_PAD_LCD_D09__LCD_D09
325 MX23_PAD_LCD_D10__LCD_D10
326 MX23_PAD_LCD_D11__LCD_D11
327 MX23_PAD_LCD_D12__LCD_D12
328 MX23_PAD_LCD_D13__LCD_D13
329 MX23_PAD_LCD_D14__LCD_D14
330 MX23_PAD_LCD_D15__LCD_D15
331 MX23_PAD_LCD_D16__LCD_D16
332 MX23_PAD_LCD_D17__LCD_D17
333 MX23_PAD_GPMI_D08__LCD_D18
334 MX23_PAD_GPMI_D09__LCD_D19
335 MX23_PAD_GPMI_D10__LCD_D20
336 MX23_PAD_GPMI_D11__LCD_D21
337 MX23_PAD_GPMI_D12__LCD_D22
338 MX23_PAD_GPMI_D13__LCD_D23
339 MX23_PAD_LCD_DOTCK__LCD_DOTCK
340 MX23_PAD_LCD_ENABLE__LCD_ENABLE
341 MX23_PAD_LCD_HSYNC__LCD_HSYNC
342 MX23_PAD_LCD_VSYNC__LCD_VSYNC
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]343 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]347 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]348
349 spi2_pins_a: spi2@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]352 MX23_PAD_GPMI_WRN__SSP2_SCK
353 MX23_PAD_GPMI_RDY1__SSP2_CMD
354 MX23_PAD_GPMI_D00__SSP2_DATA0
355 MX23_PAD_GPMI_D03__SSP2_DATA3
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]356 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]357 fsl,drive-strength = <MXS_DRIVE_8mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_ENABLE>;
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]360 };
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]361
362 i2c_pins_a: i2c@0 {
363 reg = <0>;
364 fsl,pinmux-ids = <
365 MX23_PAD_I2C_SCL__I2C_SCL
366 MX23_PAD_I2C_SDA__I2C_SDA
367 >;
368 fsl,drive-strength = <MXS_DRIVE_8mA>;
369 fsl,voltage = <MXS_VOLTAGE_HIGH>;
370 fsl,pull-up = <MXS_PULL_ENABLE>;
371 };
372
373 i2c_pins_b: i2c@1 {
374 reg = <1>;
375 fsl,pinmux-ids = <
376 MX23_PAD_LCD_ENABLE__I2C_SCL
377 MX23_PAD_LCD_HSYNC__I2C_SDA
378 >;
379 fsl,drive-strength = <MXS_DRIVE_8mA>;
380 fsl,voltage = <MXS_VOLTAGE_HIGH>;
381 fsl,pull-up = <MXS_PULL_ENABLE>;
382 };
383
384 i2c_pins_c: i2c@2 {
385 reg = <2>;
386 fsl,pinmux-ids = <
387 MX23_PAD_SSP1_DATA1__I2C_SCL
388 MX23_PAD_SSP1_DATA2__I2C_SDA
389 >;
390 fsl,drive-strength = <MXS_DRIVE_8mA>;
391 fsl,voltage = <MXS_VOLTAGE_HIGH>;
392 fsl,pull-up = <MXS_PULL_ENABLE>;
393 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]394 };
395
396 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800[diff] [blame]397 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]398 reg = <0x8001c000 2000>;
399 status = "disabled";
400 };
401
402 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]403 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]404 status = "disabled";
405 };
406
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]407 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]408 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]409 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]410 interrupts = <7 5 9 26
411 19 0 25 23
412 60 58 9 0
413 0 0 0 0>;
414 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
415 "saif0", "empty", "auart0-rx", "auart0-tx",
416 "auart1-rx", "auart1-tx", "saif1", "empty",
417 "empty", "empty", "empty", "empty";
418 #dma-cells = <1>;
419 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]420 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]421 };
422
423 dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]424 compatible = "fsl,imx23-dcp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]425 reg = <0x80028000 0x2000>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]426 interrupts = <53 54>;
427 status = "okay";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]428 };
429
430 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]431 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]432 status = "disabled";
433 };
434
435 ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]436 compatible = "fsl,imx23-ocotp", "fsl,ocotp";
437 #address-cells = <1>;
438 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]439 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]440 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]441 };
442
443 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]444 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]445 status = "disabled";
446 };
447
448 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]449 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]450 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]451 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]452 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]453 status = "disabled";
454 };
455
456 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]457 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]458 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]459 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]460 dmas = <&dma_apbh 2>;
461 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]462 status = "disabled";
463 };
464
465 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]466 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]467 status = "disabled";
468 };
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]469 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]470
471 apbx@80040000 {
472 compatible = "simple-bus";
473 #address-cells = <1>;
474 #size-cells = <1>;
475 reg = <0x80040000 0x40000>;
476 ranges;
477
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]478 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]479 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]480 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]481 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]482 };
483
484 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]485 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]486 dmas = <&dma_apbx 4>;
487 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]488 status = "disabled";
489 };
490
491 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]492 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]493 status = "disabled";
494 };
495
496 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]497 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]498 dmas = <&dma_apbx 10>;
499 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]500 status = "disabled";
501 };
502
503 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]504 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]505 dmas = <&dma_apbx 1>;
506 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]507 status = "disabled";
508 };
509
510 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]511 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]512 dmas = <&dma_apbx 0>;
513 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]514 status = "disabled";
515 };
516
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]517 lradc: lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]518 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]519 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]520 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]521 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]522 clocks = <&clks 26>;
Stefan Wahrene8e94ed2015-06-02 22:03:28 +0000[diff] [blame]523 #io-channel-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]524 };
525
526 spdif@80054000 {
527 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]528 dmas = <&dma_apbx 2>;
529 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]530 status = "disabled";
531 };
532
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]533 i2c: i2c@80058000 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "fsl,imx23-i2c";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]537 reg = <0x80058000 0x2000>;
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]538 interrupts = <27>;
539 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]540 dmas = <&dma_apbx 3>;
541 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]542 status = "disabled";
543 };
544
545 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]546 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]547 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]548 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]549 };
550
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]551 pwm: pwm@80064000 {
552 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]553 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]554 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]555 #pwm-cells = <2>;
556 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]557 status = "disabled";
558 };
559
560 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]561 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]562 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]563 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]564 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]565 };
566
567 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]568 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]569 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]570 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]571 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]572 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
573 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]574 status = "disabled";
575 };
576
577 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]578 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]579 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]580 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]581 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]582 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
583 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]584 status = "disabled";
585 };
586
587 duart: serial@80070000 {
588 compatible = "arm,pl011", "arm,primecell";
589 reg = <0x80070000 0x2000>;
590 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]591 clocks = <&clks 32>, <&clks 16>;
592 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]593 status = "disabled";
594 };
595
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]596 usbphy0: usbphy@8007c000 {
597 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]598 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]599 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]600 status = "disabled";
601 };
602 };
603 };
604
605 ahb@80080000 {
606 compatible = "simple-bus";
607 #address-cells = <1>;
608 #size-cells = <1>;
609 reg = <0x80080000 0x80000>;
610 ranges;
611
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]612 usb0: usb@80080000 {
613 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]614 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]615 interrupts = <11>;
616 fsl,usbphy = <&usbphy0>;
617 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]618 status = "disabled";
619 };
620 };
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]621
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]622 iio-hwmon {
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]623 compatible = "iio-hwmon";
624 io-channels = <&lradc 8>;
625 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]626};