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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / a5206553bab2a7d5777e0fdfb5ac8c534a28f15a / . / arch / arm / boot / dts / am33xx.dtsi
blob: af18c4738bef45350567ea268c30c3757cef550a [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]47
Dave Gerlach4317be12016-05-18 18:36:27 -0500[diff] [blame]48 operating-points-v2 = <&cpu0_opp_table>;
49 ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
50 ti,syscon-rev = <&scm_conf 0x600>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]55 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]56 };
57 };
58
Dave Gerlach4317be12016-05-18 18:36:27 -0500[diff] [blame]59 cpu0_opp_table: opp_table0 {
60 compatible = "operating-points-v2";
61
62 /*
63 * The three following nodes are marked with opp-suspend
64 * because the can not be enabled simultaneously on a
65 * single SoC.
66 */
67 opp50@300000000 {
68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <950000 931000 969000>;
70 opp-supported-hw = <0x06 0x0010>;
71 opp-suspend;
72 };
73
74 opp100@275000000 {
75 opp-hz = /bits/ 64 <275000000>;
76 opp-microvolt = <1100000 1078000 1122000>;
77 opp-supported-hw = <0x01 0x00FF>;
78 opp-suspend;
79 };
80
81 opp100@300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <1100000 1078000 1122000>;
84 opp-supported-hw = <0x06 0x0020>;
85 opp-suspend;
86 };
87
88 opp100@500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 opp-microvolt = <1100000 1078000 1122000>;
91 opp-supported-hw = <0x01 0xFFFF>;
92 };
93
94 opp100@600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <1100000 1078000 1122000>;
97 opp-supported-hw = <0x06 0x0040>;
98 };
99
100 opp120@600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1200000 1176000 1224000>;
103 opp-supported-hw = <0x01 0xFFFF>;
104 };
105
106 opp120@720000000 {
107 opp-hz = /bits/ 64 <720000000>;
108 opp-microvolt = <1200000 1176000 1224000>;
109 opp-supported-hw = <0x06 0x0080>;
110 };
111
112 oppturbo@720000000 {
113 opp-hz = /bits/ 64 <720000000>;
114 opp-microvolt = <1260000 1234800 1285200>;
115 opp-supported-hw = <0x01 0xFFFF>;
116 };
117
118 oppturbo@800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1260000 1234800 1285200>;
121 opp-supported-hw = <0x06 0x0100>;
122 };
123
124 oppnitro@1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1325000 1298500 1351500>;
127 opp-supported-hw = <0x04 0x0200>;
128 };
129 };
130
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]131 pmu {
132 compatible = "arm,cortex-a8-pmu";
133 interrupts = <3>;
134 };
135
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]136 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]137 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]138 * that are not memory mapped in the MPU view or for the MPU itself.
139 */
140 soc {
141 compatible = "ti,omap-infra";
142 mpu {
143 compatible = "ti,omap3-mpu";
144 ti,hwmods = "mpu";
145 };
146 };
147
148 /*
149 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]150 * The real AM33XX interconnect network is quite complex. Since
151 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]152 * for the moment, just use a fake OCP bus entry to represent
153 * the whole bus hierarchy.
154 */
155 ocp {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges;
160 ti,hwmods = "l3_main";
161
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]162 l4_wkup: l4_wkup@44c00000 {
163 compatible = "ti,am3-l4-wkup", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]167
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]168 wkup_m3: wkup_m3@100000 {
169 compatible = "ti,am3352-wkup-m3";
170 reg = <0x100000 0x4000>,
171 <0x180000 0x2000>;
172 reg-names = "umem", "dmem";
173 ti,hwmods = "wkup_m3";
174 ti,pm-firmware = "am335x-pm-firmware.elf";
175 };
176
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]177 prcm: prcm@200000 {
178 compatible = "ti,am3-prcm";
179 reg = <0x200000 0x4000>;
180
181 prcm_clocks: clocks {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185
186 prcm_clockdomains: clockdomains {
187 };
188 };
189
190 scm: scm@210000 {
191 compatible = "ti,am3-scm", "simple-bus";
192 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]193 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]194 #size-cells = <1>;
195 ranges = <0 0x210000 0x2000>;
196
197 am33xx_pinmux: pinmux@800 {
198 compatible = "pinctrl-single";
199 reg = <0x800 0x238>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 pinctrl-single,register-width = <32>;
203 pinctrl-single,function-mask = <0x7f>;
204 };
205
206 scm_conf: scm_conf@0 {
207 compatible = "syscon";
208 reg = <0x0 0x800>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211
212 scm_clocks: clocks {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 };
216 };
217
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]218 wkup_m3_ipc: wkup_m3_ipc@1324 {
219 compatible = "ti,am3352-wkup-m3-ipc";
220 reg = <0x1324 0x24>;
221 interrupts = <78>;
222 ti,rproc = <&wkup_m3>;
223 mboxes = <&mailbox &mbox_wkupm3>;
224 };
225
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]226 edma_xbar: dma-router@f90 {
227 compatible = "ti,am335x-edma-crossbar";
228 reg = <0xf90 0x40>;
229 #dma-cells = <3>;
230 dma-requests = <32>;
231 dma-masters = <&edma>;
232 };
233
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]234 scm_clockdomains: clockdomains {
235 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]236 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]237 };
238
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]239 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]240 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]241 interrupt-controller;
242 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]243 reg = <0x48200000 0x1000>;
244 };
245
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]246 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]247 compatible = "ti,edma3-tpcc";
248 ti,hwmods = "tpcc";
249 reg = <0x49000000 0x10000>;
250 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]251 interrupts = <12 13 14>;
Robert P. J. Daya5206552016-05-24 17:20:28 -0400[diff] [blame^]252 interrupt-names = "edma3_ccint", "edma3_mperr",
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]253 "edma3_ccerrint";
254 dma-requests = <64>;
255 #dma-cells = <2>;
256
257 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
258 <&edma_tptc2 0>;
259
260 ti,edma-memcpy-channels = <20 21>;
261 };
262
263 edma_tptc0: tptc@49800000 {
264 compatible = "ti,edma3-tptc";
265 ti,hwmods = "tptc0";
266 reg = <0x49800000 0x100000>;
267 interrupts = <112>;
268 interrupt-names = "edma3_tcerrint";
269 };
270
271 edma_tptc1: tptc@49900000 {
272 compatible = "ti,edma3-tptc";
273 ti,hwmods = "tptc1";
274 reg = <0x49900000 0x100000>;
275 interrupts = <113>;
276 interrupt-names = "edma3_tcerrint";
277 };
278
279 edma_tptc2: tptc@49a00000 {
280 compatible = "ti,edma3-tptc";
281 ti,hwmods = "tptc2";
282 reg = <0x49a00000 0x100000>;
283 interrupts = <114>;
284 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]285 };
286
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]287 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]288 compatible = "ti,omap4-gpio";
289 ti,hwmods = "gpio1";
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]293 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]294 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]295 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]296 };
297
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]298 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]299 compatible = "ti,omap4-gpio";
300 ti,hwmods = "gpio2";
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]304 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]305 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]306 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]307 };
308
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]309 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]310 compatible = "ti,omap4-gpio";
311 ti,hwmods = "gpio3";
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]315 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]316 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]317 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]318 };
319
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]320 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]321 compatible = "ti,omap4-gpio";
322 ti,hwmods = "gpio4";
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]326 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]327 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]328 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]329 };
330
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]331 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]332 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]333 ti,hwmods = "uart1";
334 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]335 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]336 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]337 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]338 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]339 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]340 };
341
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]342 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]343 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]344 ti,hwmods = "uart2";
345 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]346 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]347 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]348 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]349 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]350 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]351 };
352
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]353 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]354 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]355 ti,hwmods = "uart3";
356 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]357 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]358 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]359 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]360 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]361 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]362 };
363
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]364 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]365 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]366 ti,hwmods = "uart4";
367 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]368 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]369 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]370 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]371 };
372
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]373 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]374 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]375 ti,hwmods = "uart5";
376 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]377 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]378 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]379 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]380 };
381
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]382 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]383 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]384 ti,hwmods = "uart6";
385 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]386 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]387 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]388 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]389 };
390
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]391 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]392 compatible = "ti,omap4-i2c";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]396 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]397 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]398 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]399 };
400
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]401 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]402 compatible = "ti,omap4-i2c";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]406 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]407 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]408 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]409 };
410
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]411 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]412 compatible = "ti,omap4-i2c";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]416 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]417 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]418 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]419 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]420
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]421 mmc1: mmc@48060000 {
422 compatible = "ti,omap4-hsmmc";
423 ti,hwmods = "mmc1";
424 ti,dual-volt;
425 ti,needs-special-reset;
426 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]427 dmas = <&edma_xbar 24 0 0
428 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]429 dma-names = "tx", "rx";
430 interrupts = <64>;
431 interrupt-parent = <&intc>;
432 reg = <0x48060000 0x1000>;
433 status = "disabled";
434 };
435
436 mmc2: mmc@481d8000 {
437 compatible = "ti,omap4-hsmmc";
438 ti,hwmods = "mmc2";
439 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]440 dmas = <&edma 2 0
441 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]442 dma-names = "tx", "rx";
443 interrupts = <28>;
444 interrupt-parent = <&intc>;
445 reg = <0x481d8000 0x1000>;
446 status = "disabled";
447 };
448
449 mmc3: mmc@47810000 {
450 compatible = "ti,omap4-hsmmc";
451 ti,hwmods = "mmc3";
452 ti,needs-special-reset;
453 interrupts = <29>;
454 interrupt-parent = <&intc>;
455 reg = <0x47810000 0x1000>;
456 status = "disabled";
457 };
458
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]459 hwspinlock: spinlock@480ca000 {
460 compatible = "ti,omap4-hwspinlock";
461 reg = <0x480ca000 0x1000>;
462 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]463 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]464 };
465
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]466 wdt2: wdt@44e35000 {
467 compatible = "ti,omap3-wdt";
468 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]469 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]470 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]471 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]472
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]473 dcan0: can@481cc000 {
474 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]475 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]476 reg = <0x481cc000 0x2000>;
477 clocks = <&dcan0_fck>;
478 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]479 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]480 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]481 status = "disabled";
482 };
483
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]484 dcan1: can@481d0000 {
485 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]486 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]487 reg = <0x481d0000 0x2000>;
488 clocks = <&dcan1_fck>;
489 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]490 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]491 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]492 status = "disabled";
493 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]494
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]495 mailbox: mailbox@480C8000 {
496 compatible = "ti,omap4-mailbox";
497 reg = <0x480C8000 0x200>;
498 interrupts = <77>;
499 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]500 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]501 ti,mbox-num-users = <4>;
502 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]503 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]504 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]505 ti,mbox-tx = <0 0 0>;
506 ti,mbox-rx = <0 0 3>;
507 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]508 };
509
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]510 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]511 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]512 reg = <0x44e31000 0x400>;
513 interrupts = <67>;
514 ti,hwmods = "timer1";
515 ti,timer-alwon;
516 };
517
518 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]519 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]520 reg = <0x48040000 0x400>;
521 interrupts = <68>;
522 ti,hwmods = "timer2";
523 };
524
525 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]526 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]527 reg = <0x48042000 0x400>;
528 interrupts = <69>;
529 ti,hwmods = "timer3";
530 };
531
532 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]533 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]534 reg = <0x48044000 0x400>;
535 interrupts = <92>;
536 ti,hwmods = "timer4";
537 ti,timer-pwm;
538 };
539
540 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]541 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]542 reg = <0x48046000 0x400>;
543 interrupts = <93>;
544 ti,hwmods = "timer5";
545 ti,timer-pwm;
546 };
547
548 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]549 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]550 reg = <0x48048000 0x400>;
551 interrupts = <94>;
552 ti,hwmods = "timer6";
553 ti,timer-pwm;
554 };
555
556 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]557 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]558 reg = <0x4804a000 0x400>;
559 interrupts = <95>;
560 ti,hwmods = "timer7";
561 ti,timer-pwm;
562 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]563
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]564 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]565 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]566 reg = <0x44e3e000 0x1000>;
567 interrupts = <75
568 76>;
569 ti,hwmods = "rtc";
570 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]571
572 spi0: spi@48030000 {
573 compatible = "ti,omap4-mcspi";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]577 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]578 ti,spi-num-cs = <2>;
579 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]580 dmas = <&edma 16 0
581 &edma 17 0
582 &edma 18 0
583 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]584 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]585 status = "disabled";
586 };
587
588 spi1: spi@481a0000 {
589 compatible = "ti,omap4-mcspi";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]593 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]594 ti,spi-num-cs = <2>;
595 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]596 dmas = <&edma 42 0
597 &edma 43 0
598 &edma 44 0
599 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]600 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]601 status = "disabled";
602 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]603
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]604 usb: usb@47400000 {
605 compatible = "ti,am33xx-usb";
606 reg = <0x47400000 0x1000>;
607 ranges;
608 #address-cells = <1>;
609 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]610 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]611 status = "disabled";
612
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]613 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]614 compatible = "ti,am335x-usb-ctrl-module";
615 reg = <0x44e10620 0x10
616 0x44e10648 0x4>;
617 reg-names = "phy_ctrl", "wakeup";
618 status = "disabled";
619 };
620
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]621 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]622 compatible = "ti,am335x-usb-phy";
623 reg = <0x47401300 0x100>;
624 reg-names = "phy";
625 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]626 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]627 };
628
629 usb0: usb@47401000 {
630 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]631 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]632 reg = <0x47401400 0x400
633 0x47401000 0x200>;
634 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]635
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]636 interrupts = <18>;
637 interrupt-names = "mc";
638 dr_mode = "otg";
639 mentor,multipoint = <1>;
640 mentor,num-eps = <16>;
641 mentor,ram-bits = <12>;
642 mentor,power = <500>;
643 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]644
645 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
646 &cppi41dma 2 0 &cppi41dma 3 0
647 &cppi41dma 4 0 &cppi41dma 5 0
648 &cppi41dma 6 0 &cppi41dma 7 0
649 &cppi41dma 8 0 &cppi41dma 9 0
650 &cppi41dma 10 0 &cppi41dma 11 0
651 &cppi41dma 12 0 &cppi41dma 13 0
652 &cppi41dma 14 0 &cppi41dma 0 1
653 &cppi41dma 1 1 &cppi41dma 2 1
654 &cppi41dma 3 1 &cppi41dma 4 1
655 &cppi41dma 5 1 &cppi41dma 6 1
656 &cppi41dma 7 1 &cppi41dma 8 1
657 &cppi41dma 9 1 &cppi41dma 10 1
658 &cppi41dma 11 1 &cppi41dma 12 1
659 &cppi41dma 13 1 &cppi41dma 14 1>;
660 dma-names =
661 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
662 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
663 "rx14", "rx15",
664 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
665 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
666 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]667 };
668
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]669 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]670 compatible = "ti,am335x-usb-phy";
671 reg = <0x47401b00 0x100>;
672 reg-names = "phy";
673 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]674 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]675 };
676
677 usb1: usb@47401800 {
678 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]679 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]680 reg = <0x47401c00 0x400
681 0x47401800 0x200>;
682 reg-names = "mc", "control";
683 interrupts = <19>;
684 interrupt-names = "mc";
685 dr_mode = "otg";
686 mentor,multipoint = <1>;
687 mentor,num-eps = <16>;
688 mentor,ram-bits = <12>;
689 mentor,power = <500>;
690 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]691
692 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
693 &cppi41dma 17 0 &cppi41dma 18 0
694 &cppi41dma 19 0 &cppi41dma 20 0
695 &cppi41dma 21 0 &cppi41dma 22 0
696 &cppi41dma 23 0 &cppi41dma 24 0
697 &cppi41dma 25 0 &cppi41dma 26 0
698 &cppi41dma 27 0 &cppi41dma 28 0
699 &cppi41dma 29 0 &cppi41dma 15 1
700 &cppi41dma 16 1 &cppi41dma 17 1
701 &cppi41dma 18 1 &cppi41dma 19 1
702 &cppi41dma 20 1 &cppi41dma 21 1
703 &cppi41dma 22 1 &cppi41dma 23 1
704 &cppi41dma 24 1 &cppi41dma 25 1
705 &cppi41dma 26 1 &cppi41dma 27 1
706 &cppi41dma 28 1 &cppi41dma 29 1>;
707 dma-names =
708 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
709 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
710 "rx14", "rx15",
711 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
712 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
713 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]714 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]715
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]716 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]717 compatible = "ti,am3359-cppi41";
718 reg = <0x47400000 0x1000
719 0x47402000 0x1000
720 0x47403000 0x1000
721 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]722 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]723 interrupts = <17>;
724 interrupt-names = "glue";
725 #dma-cells = <2>;
726 #dma-channels = <30>;
727 #dma-requests = <256>;
728 status = "disabled";
729 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]730 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]731
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]732 epwmss0: epwmss@48300000 {
733 compatible = "ti,am33xx-pwmss";
734 reg = <0x48300000 0x10>;
735 ti,hwmods = "epwmss0";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 status = "disabled";
739 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
740 0x48300180 0x48300180 0x80 /* EQEP */
741 0x48300200 0x48300200 0x80>; /* EHRPWM */
742
743 ecap0: ecap@48300100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]744 compatible = "ti,am3352-ecap",
745 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]746 #pwm-cells = <3>;
747 reg = <0x48300100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]748 clocks = <&l4ls_gclk>;
749 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]750 interrupts = <31>;
751 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]752 status = "disabled";
753 };
754
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]755 ehrpwm0: pwm@48300200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]756 compatible = "ti,am3352-ehrpwm",
757 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]758 #pwm-cells = <3>;
759 reg = <0x48300200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]760 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
761 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]762 status = "disabled";
763 };
764 };
765
766 epwmss1: epwmss@48302000 {
767 compatible = "ti,am33xx-pwmss";
768 reg = <0x48302000 0x10>;
769 ti,hwmods = "epwmss1";
770 #address-cells = <1>;
771 #size-cells = <1>;
772 status = "disabled";
773 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
774 0x48302180 0x48302180 0x80 /* EQEP */
775 0x48302200 0x48302200 0x80>; /* EHRPWM */
776
777 ecap1: ecap@48302100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]778 compatible = "ti,am3352-ecap",
779 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]780 #pwm-cells = <3>;
781 reg = <0x48302100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]782 clocks = <&l4ls_gclk>;
783 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]784 interrupts = <47>;
785 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]786 status = "disabled";
787 };
788
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]789 ehrpwm1: pwm@48302200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]790 compatible = "ti,am3352-ehrpwm",
791 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]792 #pwm-cells = <3>;
793 reg = <0x48302200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]794 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
795 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]796 status = "disabled";
797 };
798 };
799
800 epwmss2: epwmss@48304000 {
801 compatible = "ti,am33xx-pwmss";
802 reg = <0x48304000 0x10>;
803 ti,hwmods = "epwmss2";
804 #address-cells = <1>;
805 #size-cells = <1>;
806 status = "disabled";
807 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
808 0x48304180 0x48304180 0x80 /* EQEP */
809 0x48304200 0x48304200 0x80>; /* EHRPWM */
810
811 ecap2: ecap@48304100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]812 compatible = "ti,am3352-ecap",
813 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]814 #pwm-cells = <3>;
815 reg = <0x48304100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]816 clocks = <&l4ls_gclk>;
817 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]818 interrupts = <61>;
819 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]820 status = "disabled";
821 };
822
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]823 ehrpwm2: pwm@48304200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]824 compatible = "ti,am3352-ehrpwm",
825 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]826 #pwm-cells = <3>;
827 reg = <0x48304200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]828 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
829 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]830 status = "disabled";
831 };
832 };
833
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]834 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]835 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]836 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]837 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
838 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]839 cpdma_channels = <8>;
840 ale_entries = <1024>;
841 bd_ram_size = <0x2000>;
842 no_bd_ram = <0>;
843 rx_descs = <64>;
844 mac_control = <0x20>;
845 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]846 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]847 cpts_clock_mult = <0x80000000>;
848 cpts_clock_shift = <29>;
849 reg = <0x4a100000 0x800
850 0x4a101200 0x100>;
851 #address-cells = <1>;
852 #size-cells = <1>;
853 interrupt-parent = <&intc>;
854 /*
855 * c0_rx_thresh_pend
856 * c0_rx_pend
857 * c0_tx_pend
858 * c0_misc_pend
859 */
860 interrupts = <40 41 42 43>;
861 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]862 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]863 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]864
865 davinci_mdio: mdio@4a101000 {
866 compatible = "ti,davinci_mdio";
867 #address-cells = <1>;
868 #size-cells = <0>;
869 ti,hwmods = "davinci_mdio";
870 bus_freq = <1000000>;
871 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]872 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]873 };
874
875 cpsw_emac0: slave@4a100200 {
876 /* Filled in by U-Boot */
877 mac-address = [ 00 00 00 00 00 00 ];
878 };
879
880 cpsw_emac1: slave@4a100300 {
881 /* Filled in by U-Boot */
882 mac-address = [ 00 00 00 00 00 00 ];
883 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]884
885 phy_sel: cpsw-phy-sel@44e10650 {
886 compatible = "ti,am3352-cpsw-phy-sel";
887 reg= <0x44e10650 0x4>;
888 reg-names = "gmii-sel";
889 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]890 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]891
892 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]893 compatible = "mmio-sram";
894 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]895 };
896
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]897 elm: elm@48080000 {
898 compatible = "ti,am3352-elm";
899 reg = <0x48080000 0x2000>;
900 interrupts = <4>;
901 ti,hwmods = "elm";
902 status = "disabled";
903 };
904
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]905 lcdc: lcdc@4830e000 {
906 compatible = "ti,am33xx-tilcdc";
907 reg = <0x4830e000 0x1000>;
908 interrupt-parent = <&intc>;
909 interrupts = <36>;
910 ti,hwmods = "lcdc";
911 status = "disabled";
912 };
913
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]914 tscadc: tscadc@44e0d000 {
915 compatible = "ti,am3359-tscadc";
916 reg = <0x44e0d000 0x1000>;
917 interrupt-parent = <&intc>;
918 interrupts = <16>;
919 ti,hwmods = "adc_tsc";
920 status = "disabled";
921
922 tsc {
923 compatible = "ti,am3359-tsc";
924 };
925 am335x_adc: adc {
926 #io-channel-cells = <1>;
927 compatible = "ti,am3359-adc";
928 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]929 };
930
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]931 gpmc: gpmc@50000000 {
932 compatible = "ti,am3352-gpmc";
933 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe22013-10-15 12:37:50 +0530[diff] [blame]934 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]935 reg = <0x50000000 0x2000>;
936 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame]937 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]938 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]939 gpmc,num-cs = <7>;
940 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]941 #address-cells = <2>;
942 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]943 interrupt-controller;
944 #interrupt-cells = <2>;
Roger Quadros4eb4dd52016-04-07 13:25:32 +0300[diff] [blame]945 gpio-controller;
946 #gpio-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]947 status = "disabled";
948 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]949
950 sham: sham@53100000 {
951 compatible = "ti,omap4-sham";
952 ti,hwmods = "sham";
953 reg = <0x53100000 0x200>;
954 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]955 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]956 dma-names = "rx";
957 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]958
959 aes: aes@53500000 {
960 compatible = "ti,omap4-aes";
961 ti,hwmods = "aes";
962 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]963 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]964 dmas = <&edma 6 0>,
965 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]966 dma-names = "tx", "rx";
967 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]968
969 mcasp0: mcasp@48038000 {
970 compatible = "ti,am33xx-mcasp-audio";
971 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]972 reg = <0x48038000 0x2000>,
973 <0x46000000 0x400000>;
974 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]975 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]976 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]977 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]978 dmas = <&edma 8 2>,
979 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]980 dma-names = "tx", "rx";
981 };
982
983 mcasp1: mcasp@4803C000 {
984 compatible = "ti,am33xx-mcasp-audio";
985 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]986 reg = <0x4803C000 0x2000>,
987 <0x46400000 0x400000>;
988 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]989 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]990 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]991 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]992 dmas = <&edma 10 2>,
993 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]994 dma-names = "tx", "rx";
995 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]996
997 rng: rng@48310000 {
998 compatible = "ti,omap4-rng";
999 ti,hwmods = "rng";
1000 reg = <0x48310000 0x2000>;
1001 interrupts = <111>;
1002 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1003 };
1004};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]1005
1006/include/ "am33xx-clocks.dtsi"