Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 0a7486c93ed3355efee8e7e10ca370c2d83d8df9 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 0b9e4163fec2697f842ff429a5c1acd5eb0233bb [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]29 };
30
31 cpus {
32 cpu@0 {
33 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]34
35 /*
36 * To consider voltage drop between PMIC and SoC,
37 * tolerance value is reduced to 2% from 4% and
38 * voltage value is increased as a precaution.
39 */
40 operating-points = <
41 /* kHz uV */
42 720000 1285000
43 600000 1225000
44 500000 1125000
45 275000 1125000
46 >;
47 voltage-tolerance = <2>; /* 2 percentage */
48 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]49 };
50 };
51
52 /*
53 * The soc node represents the soc top level view. It is uses for IPs
54 * that are not memory mapped in the MPU view or for the MPU itself.
55 */
56 soc {
57 compatible = "ti,omap-infra";
58 mpu {
59 compatible = "ti,omap3-mpu";
60 ti,hwmods = "mpu";
61 };
62 };
63
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]64 am33xx_pinmux: pinmux@44e10800 {
65 compatible = "pinctrl-single";
66 reg = <0x44e10800 0x0238>;
67 #address-cells = <1>;
68 #size-cells = <0>;
69 pinctrl-single,register-width = <32>;
70 pinctrl-single,function-mask = <0x7f>;
71 };
72
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]73 /*
74 * XXX: Use a flat representation of the AM33XX interconnect.
75 * The real AM33XX interconnect network is quite complex.Since
76 * that will not bring real advantage to represent that in DT
77 * for the moment, just use a fake OCP bus entry to represent
78 * the whole bus hierarchy.
79 */
80 ocp {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85 ti,hwmods = "l3_main";
86
87 intc: interrupt-controller@48200000 {
88 compatible = "ti,omap2-intc";
89 interrupt-controller;
90 #interrupt-cells = <1>;
91 ti,intc-size = <128>;
92 reg = <0x48200000 0x1000>;
93 };
94
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]95 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]96 compatible = "ti,omap4-gpio";
97 ti,hwmods = "gpio1";
98 gpio-controller;
99 #gpio-cells = <2>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]102 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]103 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]104 };
105
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]106 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]107 compatible = "ti,omap4-gpio";
108 ti,hwmods = "gpio2";
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]113 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]114 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]115 };
116
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]117 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]118 compatible = "ti,omap4-gpio";
119 ti,hwmods = "gpio3";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]124 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]125 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]126 };
127
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]128 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]129 compatible = "ti,omap4-gpio";
130 ti,hwmods = "gpio4";
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]135 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]136 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]137 };
138
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]139 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]140 compatible = "ti,omap3-uart";
141 ti,hwmods = "uart1";
142 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]143 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]144 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]145 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]146 };
147
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]148 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]149 compatible = "ti,omap3-uart";
150 ti,hwmods = "uart2";
151 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]153 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]154 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]155 };
156
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]157 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]158 compatible = "ti,omap3-uart";
159 ti,hwmods = "uart3";
160 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]161 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]162 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]163 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]164 };
165
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]166 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]167 compatible = "ti,omap3-uart";
168 ti,hwmods = "uart4";
169 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]171 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]172 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]173 };
174
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]175 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]176 compatible = "ti,omap3-uart";
177 ti,hwmods = "uart5";
178 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]180 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]181 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 };
183
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]184 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]185 compatible = "ti,omap3-uart";
186 ti,hwmods = "uart6";
187 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]188 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]189 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]190 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]191 };
192
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]193 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]194 compatible = "ti,omap4-i2c";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]198 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]199 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]200 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]201 };
202
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]203 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]204 compatible = "ti,omap4-i2c";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]208 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]210 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]211 };
212
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]213 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]214 compatible = "ti,omap4-i2c";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]218 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]219 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]220 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]221 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]222
223 wdt2: wdt@44e35000 {
224 compatible = "ti,omap3-wdt";
225 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]228 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]229
230 dcan0: d_can@481cc000 {
231 compatible = "bosch,d_can";
232 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]233 reg = <0x481cc000 0x2000
234 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]235 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]236 status = "disabled";
237 };
238
239 dcan1: d_can@481d0000 {
240 compatible = "bosch,d_can";
241 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]242 reg = <0x481d0000 0x2000
243 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]244 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]245 status = "disabled";
246 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]247
248 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]249 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]250 reg = <0x44e31000 0x400>;
251 interrupts = <67>;
252 ti,hwmods = "timer1";
253 ti,timer-alwon;
254 };
255
256 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]257 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]258 reg = <0x48040000 0x400>;
259 interrupts = <68>;
260 ti,hwmods = "timer2";
261 };
262
263 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]264 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]265 reg = <0x48042000 0x400>;
266 interrupts = <69>;
267 ti,hwmods = "timer3";
268 };
269
270 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]271 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]272 reg = <0x48044000 0x400>;
273 interrupts = <92>;
274 ti,hwmods = "timer4";
275 ti,timer-pwm;
276 };
277
278 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]279 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]280 reg = <0x48046000 0x400>;
281 interrupts = <93>;
282 ti,hwmods = "timer5";
283 ti,timer-pwm;
284 };
285
286 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]287 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]288 reg = <0x48048000 0x400>;
289 interrupts = <94>;
290 ti,hwmods = "timer6";
291 ti,timer-pwm;
292 };
293
294 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]295 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]296 reg = <0x4804a000 0x400>;
297 interrupts = <95>;
298 ti,hwmods = "timer7";
299 ti,timer-pwm;
300 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]301
302 rtc@44e3e000 {
303 compatible = "ti,da830-rtc";
304 reg = <0x44e3e000 0x1000>;
305 interrupts = <75
306 76>;
307 ti,hwmods = "rtc";
308 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]309
310 spi0: spi@48030000 {
311 compatible = "ti,omap4-mcspi";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]315 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]316 ti,spi-num-cs = <2>;
317 ti,hwmods = "spi0";
318 status = "disabled";
319 };
320
321 spi1: spi@481a0000 {
322 compatible = "ti,omap4-mcspi";
323 #address-cells = <1>;
324 #size-cells = <0>;
325 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]326 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]327 ti,spi-num-cs = <2>;
328 ti,hwmods = "spi1";
329 status = "disabled";
330 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]331
332 usb@47400000 {
333 compatible = "ti,musb-am33xx";
334 reg = <0x47400000 0x1000 /* usbss */
335 0x47401000 0x800 /* musb instance 0 */
336 0x47401800 0x800>; /* musb instance 1 */
337 interrupts = <17 /* usbss */
338 18 /* musb instance 0 */
339 19>; /* musb instance 1 */
340 multipoint = <1>;
341 num-eps = <16>;
342 ram-bits = <12>;
343 port0-mode = <3>;
344 port1-mode = <3>;
345 power = <250>;
346 ti,hwmods = "usb_otg_hs";
347 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]348
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame^]349 epwmss0: epwmss@48300000 {
350 compatible = "ti,am33xx-pwmss";
351 reg = <0x48300000 0x10>;
352 ti,hwmods = "epwmss0";
353 #address-cells = <1>;
354 #size-cells = <1>;
355 status = "disabled";
356 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
357 0x48300180 0x48300180 0x80 /* EQEP */
358 0x48300200 0x48300200 0x80>; /* EHRPWM */
359
360 ecap0: ecap@48300100 {
361 compatible = "ti,am33xx-ecap";
362 #pwm-cells = <3>;
363 reg = <0x48300100 0x80>;
364 ti,hwmods = "ecap0";
365 status = "disabled";
366 };
367
368 ehrpwm0: ehrpwm@48300200 {
369 compatible = "ti,am33xx-ehrpwm";
370 #pwm-cells = <3>;
371 reg = <0x48300200 0x80>;
372 ti,hwmods = "ehrpwm0";
373 status = "disabled";
374 };
375 };
376
377 epwmss1: epwmss@48302000 {
378 compatible = "ti,am33xx-pwmss";
379 reg = <0x48302000 0x10>;
380 ti,hwmods = "epwmss1";
381 #address-cells = <1>;
382 #size-cells = <1>;
383 status = "disabled";
384 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
385 0x48302180 0x48302180 0x80 /* EQEP */
386 0x48302200 0x48302200 0x80>; /* EHRPWM */
387
388 ecap1: ecap@48302100 {
389 compatible = "ti,am33xx-ecap";
390 #pwm-cells = <3>;
391 reg = <0x48302100 0x80>;
392 ti,hwmods = "ecap1";
393 status = "disabled";
394 };
395
396 ehrpwm1: ehrpwm@48302200 {
397 compatible = "ti,am33xx-ehrpwm";
398 #pwm-cells = <3>;
399 reg = <0x48302200 0x80>;
400 ti,hwmods = "ehrpwm1";
401 status = "disabled";
402 };
403 };
404
405 epwmss2: epwmss@48304000 {
406 compatible = "ti,am33xx-pwmss";
407 reg = <0x48304000 0x10>;
408 ti,hwmods = "epwmss2";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 status = "disabled";
412 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
413 0x48304180 0x48304180 0x80 /* EQEP */
414 0x48304200 0x48304200 0x80>; /* EHRPWM */
415
416 ecap2: ecap@48304100 {
417 compatible = "ti,am33xx-ecap";
418 #pwm-cells = <3>;
419 reg = <0x48304100 0x80>;
420 ti,hwmods = "ecap2";
421 status = "disabled";
422 };
423
424 ehrpwm2: ehrpwm@48304200 {
425 compatible = "ti,am33xx-ehrpwm";
426 #pwm-cells = <3>;
427 reg = <0x48304200 0x80>;
428 ti,hwmods = "ehrpwm2";
429 status = "disabled";
430 };
431 };
432
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]433 mac: ethernet@4a100000 {
434 compatible = "ti,cpsw";
435 ti,hwmods = "cpgmac0";
436 cpdma_channels = <8>;
437 ale_entries = <1024>;
438 bd_ram_size = <0x2000>;
439 no_bd_ram = <0>;
440 rx_descs = <64>;
441 mac_control = <0x20>;
442 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]443 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]444 cpts_clock_mult = <0x80000000>;
445 cpts_clock_shift = <29>;
446 reg = <0x4a100000 0x800
447 0x4a101200 0x100>;
448 #address-cells = <1>;
449 #size-cells = <1>;
450 interrupt-parent = <&intc>;
451 /*
452 * c0_rx_thresh_pend
453 * c0_rx_pend
454 * c0_tx_pend
455 * c0_misc_pend
456 */
457 interrupts = <40 41 42 43>;
458 ranges;
459
460 davinci_mdio: mdio@4a101000 {
461 compatible = "ti,davinci_mdio";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 ti,hwmods = "davinci_mdio";
465 bus_freq = <1000000>;
466 reg = <0x4a101000 0x100>;
467 };
468
469 cpsw_emac0: slave@4a100200 {
470 /* Filled in by U-Boot */
471 mac-address = [ 00 00 00 00 00 00 ];
472 };
473
474 cpsw_emac1: slave@4a100300 {
475 /* Filled in by U-Boot */
476 mac-address = [ 00 00 00 00 00 00 ];
477 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]478 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]479
480 ocmcram: ocmcram@40300000 {
481 compatible = "ti,am3352-ocmcram";
482 reg = <0x40300000 0x10000>;
483 ti,hwmods = "ocmcram";
484 ti,no_idle_on_suspend;
485 };
486
487 wkup_m3: wkup_m3@44d00000 {
488 compatible = "ti,am3353-wkup-m3";
489 reg = <0x44d00000 0x4000 /* M3 UMEM */
490 0x44d80000 0x2000>; /* M3 DMEM */
491 ti,hwmods = "wkup_m3";
492 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]493
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]494 elm: elm@48080000 {
495 compatible = "ti,am3352-elm";
496 reg = <0x48080000 0x2000>;
497 interrupts = <4>;
498 ti,hwmods = "elm";
499 status = "disabled";
500 };
501
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]502 gpmc: gpmc@50000000 {
503 compatible = "ti,am3352-gpmc";
504 ti,hwmods = "gpmc";
505 reg = <0x50000000 0x2000>;
506 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]507 gpmc,num-cs = <7>;
508 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]509 #address-cells = <2>;
510 #size-cells = <1>;
511 status = "disabled";
512 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]513 };
514};