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Carlo Caione6b112e22014-09-09 22:12:56 +02001/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
Martin Blumenstingl5239e052017-06-15 23:33:44 +020048#include <dt-bindings/interrupt-controller/irq.h>
49#include <dt-bindings/interrupt-controller/arm-gic.h>
Carlo Caione6b112e22014-09-09 22:12:56 +020050/include/ "skeleton.dtsi"
51
52/ {
53 interrupt-parent = <&gic>;
54
Beniamino Galvani550ab392014-11-18 15:30:35 +010055 L2: l2-cache-controller@c4200000 {
56 compatible = "arm,pl310-cache";
57 reg = <0xc4200000 0x1000>;
58 cache-unified;
59 cache-level = <2>;
60 };
61
Carlo Caione6b112e22014-09-09 22:12:56 +020062 gic: interrupt-controller@c4301000 {
63 compatible = "arm,cortex-a9-gic";
64 reg = <0xc4301000 0x1000>,
65 <0xc4300100 0x0100>;
66 interrupt-controller;
67 #interrupt-cells = <3>;
68 };
69
Carlo Caione6b112e22014-09-09 22:12:56 +020070 soc {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
Martin Blumenstingl200a5752017-04-17 23:39:37 +020076 cbus: cbus@c1100000 {
77 compatible = "simple-bus";
78 reg = <0xc1100000 0x200000>;
Beniamino Galvani8fba96f2014-11-13 20:32:03 +010079 #address-cells = <1>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +020080 #size-cells = <1>;
81 ranges = <0x0 0xc1100000 0x200000>;
82
83 uart_A: serial@84c0 {
84 compatible = "amlogic,meson-uart";
85 reg = <0x84c0 0x18>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +020086 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +020087 status = "disabled";
88 };
89
90 uart_B: serial@84dc {
91 compatible = "amlogic,meson-uart";
92 reg = <0x84dc 0x18>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +020093 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +020094 status = "disabled";
95 };
96
97 i2c_A: i2c@8500 {
98 compatible = "amlogic,meson6-i2c";
99 reg = <0x8500 0x20>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200100 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200101 #address-cells = <1>;
102 #size-cells = <0>;
103 status = "disabled";
104 };
105
Martin Blumenstingla39a3b92017-06-15 23:33:47 +0200106 saradc: adc@8680 {
107 compatible = "amlogic,meson-saradc";
108 reg = <0x8680 0x34>;
109 #io-channel-cells = <1>;
110 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
111 status = "disabled";
112 };
113
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200114 uart_C: serial@8700 {
115 compatible = "amlogic,meson-uart";
116 reg = <0x8700 0x18>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200117 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200118 status = "disabled";
119 };
120
121 i2c_B: i2c@87c0 {
122 compatible = "amlogic,meson6-i2c";
123 reg = <0x87c0 0x20>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200124 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200125 #address-cells = <1>;
126 #size-cells = <0>;
127 status = "disabled";
128 };
129
130 spifc: spi@8c80 {
131 compatible = "amlogic,meson6-spifc";
132 reg = <0x8c80 0x80>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 status = "disabled";
136 };
137
138 wdt: watchdog@9900 {
139 compatible = "amlogic,meson6-wdt";
140 reg = <0x9900 0x8>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200141 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200142 };
143
144 timer@9940 {
145 compatible = "amlogic,meson6-timer";
146 reg = <0x9940 0x18>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200147 interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200148 };
Beniamino Galvani8fba96f2014-11-13 20:32:03 +0100149 };
150
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200151 aobus: aobus@c8100000 {
152 compatible = "simple-bus";
153 reg = <0xc8100000 0x100000>;
Beniamino Galvani8fba96f2014-11-13 20:32:03 +0100154 #address-cells = <1>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200155 #size-cells = <1>;
156 ranges = <0x0 0xc8100000 0x100000>;
Beniamino Galvani8fba96f2014-11-13 20:32:03 +0100157
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200158 ir_receiver: ir-receiver@480 {
159 compatible= "amlogic,meson6-ir";
160 reg = <0x480 0x20>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200161 interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200162 status = "disabled";
163 };
Linus Torvalds2183a582014-12-11 11:49:23 -0800164
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200165 uart_AO: serial@4c0 {
166 compatible = "amlogic,meson-uart";
167 reg = <0x4c0 0x18>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200168 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200169 status = "disabled";
170 };
Beniamino Galvani03bb9512015-03-01 20:39:51 +0100171
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200172 i2c_AO: i2c@500 {
173 compatible = "amlogic,meson6-i2c";
174 reg = <0x500 0x20>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200175 interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
Martin Blumenstingl200a5752017-04-17 23:39:37 +0200176 #address-cells = <1>;
177 #size-cells = <0>;
178 status = "disabled";
179 };
Beniamino Galvani03bb9512015-03-01 20:39:51 +0100180 };
Beniamino Galvani2345d502015-03-01 20:45:37 +0100181
182 ethmac: ethernet@c9410000 {
183 compatible = "amlogic,meson6-dwmac", "snps,dwmac";
184 reg = <0xc9410000 0x10000
185 0xc1108108 0x4>;
Martin Blumenstingl5239e052017-06-15 23:33:44 +0200186 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
Beniamino Galvani2345d502015-03-01 20:45:37 +0100187 interrupt-names = "macirq";
Beniamino Galvani2345d502015-03-01 20:45:37 +0100188 status = "disabled";
189 };
Carlo Caione6b112e22014-09-09 22:12:56 +0200190 };
191}; /* end of / */