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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 84b3e42564accd94c2680e3ba42717c32c8b5fc4 / . / Documentation / devicetree / bindings / watchdog / mtk-wdt.txt
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Matthias Brugger9a4c8802015-01-13 13:28:56 +0100[diff] [blame]1Mediatek SoCs Watchdog timer
2
Wang Qing5f8ebd42021-04-25 09:52:07 +0800[diff] [blame]3The watchdog supports a pre-timeout interrupt that fires timeout-sec/2
4before the expiry.
5
Matthias Brugger9a4c8802015-01-13 13:28:56 +0100[diff] [blame]6Required properties:
7
Erin Lo02eca172015-10-20 14:34:30 +0800[diff] [blame]8- compatible should contain:
Matthias Brugger275e8592017-07-20 12:22:44 +0200[diff] [blame]9 "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
Crystal Guoe547aa02020-10-14 21:19:33 +0800[diff] [blame]10 "mediatek,mt2712-wdt": for MT2712
Matthias Brugger275e8592017-07-20 12:22:44 +0200[diff] [blame]11 "mediatek,mt6589-wdt": for MT6589
Matthias Bruggerf4fdb9c2017-07-20 12:22:45 +0200[diff] [blame]12 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
Linus Torvalds939ae582017-09-14 13:28:30 -0700[diff] [blame]13 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
14 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
Ryder Lee4d9c6e92018-11-07 15:10:36 +0800[diff] [blame]15 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
Sam Shih41e73fe2021-08-17 15:45:55 +0800[diff] [blame]16 "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
Crystal Guoe547aa02020-10-14 21:19:33 +0800[diff] [blame]17 "mediatek,mt8183-wdt": for MT8183
Matteo Crocef6cc8b32019-03-18 02:19:15 +0100[diff] [blame]18 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
Crystal Guo53526be2020-10-14 21:19:34 +0800[diff] [blame]19 "mediatek,mt8192-wdt": for MT8192
Seiya Wangb326f2c2021-03-16 19:14:36 +0800[diff] [blame]20 "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
Erin Lo02eca172015-10-20 14:34:30 +0800[diff] [blame]21
Matthias Brugger9a4c8802015-01-13 13:28:56 +0100[diff] [blame]22- reg : Specifies base physical address and size of the registers.
23
Marcus Folkessonb82e6952018-02-11 21:08:45 +0100[diff] [blame]24Optional properties:
Wang Qing5f8ebd42021-04-25 09:52:07 +0800[diff] [blame]25- interrupts: Watchdog pre-timeout (bark) interrupt.
Marcus Folkessonb82e6952018-02-11 21:08:45 +0100[diff] [blame]26- timeout-sec: contains the watchdog timeout in seconds.
yong.liangf43f97a2020-01-15 16:58:25 +0800[diff] [blame]27- #reset-cells: Should be 1.
Marcus Folkessonb82e6952018-02-11 21:08:45 +0100[diff] [blame]28
Matthias Brugger9a4c8802015-01-13 13:28:56 +0100[diff] [blame]29Example:
30
yong.liangf43f97a2020-01-15 16:58:25 +0800[diff] [blame]31watchdog: watchdog@10007000 {
32 compatible = "mediatek,mt8183-wdt",
33 "mediatek,mt6589-wdt";
34 reg = <0 0x10007000 0 0x100>;
Wang Qing5f8ebd42021-04-25 09:52:07 +0800[diff] [blame]35 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
Marcus Folkessonb82e6952018-02-11 21:08:45 +0100[diff] [blame]36 timeout-sec = <10>;
yong.liangf43f97a2020-01-15 16:58:25 +0800[diff] [blame]37 #reset-cells = <1>;
Matthias Brugger9a4c8802015-01-13 13:28:56 +0100[diff] [blame]38};