blob: a9261cf48293b90ad5b423477d07db1e5e6835df [file] [log] [blame]
Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Mark Rutlandfa8ad782015-07-06 12:23:53 +01002#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
Mark Rutlandbddb9b62017-06-13 13:45:51 +01007 depends on PERF_EVENTS
Mark Rutlandfa8ad782015-07-06 12:23:53 +01008
Robin Murphy3de6be72018-02-15 18:51:42 +00009config ARM_CCI_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010010 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
Robin Murphy3de6be72018-02-15 18:51:42 +000012 select ARM_CCI
Robin Murphy8b0c93c2018-05-14 14:34:53 +010013 help
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
16
17 If compiled as a module, it will be called arm-cci.
Robin Murphy3de6be72018-02-15 18:51:42 +000018
19config ARM_CCI400_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010020 bool "support CCI-400"
21 default y
22 depends on ARM_CCI_PMU
Robin Murphy3de6be72018-02-15 18:51:42 +000023 select ARM_CCI400_COMMON
Robin Murphy3de6be72018-02-15 18:51:42 +000024 help
Robin Murphy8b0c93c2018-05-14 14:34:53 +010025 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
Robin Murphy3de6be72018-02-15 18:51:42 +000027
28config ARM_CCI5xx_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010029 bool "support CCI-500/CCI-550"
30 default y
31 depends on ARM_CCI_PMU
Robin Murphy3de6be72018-02-15 18:51:42 +000032 help
Robin Murphy8b0c93c2018-05-14 14:34:53 +010033 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
Robin Murphy3de6be72018-02-15 18:51:42 +000036
Robin Murphy1888d3d2018-02-15 18:51:41 +000037config ARM_CCN
38 tristate "ARM CCN driver support"
39 depends on ARM || ARM64
40 help
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42 interconnect.
43
Mark Rutlandfa8ad782015-07-06 12:23:53 +010044config ARM_PMU
Mark Rutlandbddb9b62017-06-13 13:45:51 +010045 depends on ARM || ARM64
Mark Rutlandfa8ad782015-07-06 12:23:53 +010046 bool "ARM PMU framework"
47 default y
48 help
49 Say y if you want to use CPU performance monitors on ARM-based
50 systems.
51
Mark Rutland45736a72017-04-11 09:39:55 +010052config ARM_PMU_ACPI
53 depends on ARM_PMU && ACPI
54 def_bool y
55
Neil Leeder7d839b42019-03-26 15:17:51 +000056config ARM_SMMU_V3_PMU
57 tristate "ARM SMMUv3 Performance Monitors Extension"
58 depends on ARM64 && ACPI && ARM_SMMU_V3
59 help
60 Provides support for the ARM SMMUv3 Performance Monitor Counter
61 Groups (PMCG), which provide monitoring of transactions passing
62 through the SMMU and allow the resulting information to be filtered
63 based on the Stream ID of the corresponding master.
64
Suzuki K Poulose7520fa92018-01-02 11:25:33 +000065config ARM_DSU_PMU
66 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
67 depends on ARM64
68 help
69 Provides support for performance monitor unit in ARM DynamIQ Shared
70 Unit (DSU). The DSU integrates one or more cores with an L3 memory
71 system, control logic. The PMU allows counting various events related
72 to DSU.
73
Frank Li9a66d362019-05-01 18:43:29 +000074config FSL_IMX8_DDR_PMU
75 tristate "Freescale i.MX8 DDR perf monitor"
76 depends on ARCH_MXC
77 help
78 Provides support for the DDR performance monitor in i.MX8, which
79 can give information about memory throughput and other related
80 events.
81
Neil Leeder21bdbb72017-02-07 13:14:04 -050082config QCOM_L2_PMU
83 bool "Qualcomm Technologies L2-cache PMU"
Mark Rutlandbddb9b62017-06-13 13:45:51 +010084 depends on ARCH_QCOM && ARM64 && ACPI
Neil Leeder21bdbb72017-02-07 13:14:04 -050085 help
86 Provides support for the L2 cache performance monitor unit (PMU)
87 in Qualcomm Technologies processors.
88 Adds the L2 cache PMU into the perf events subsystem for
89 monitoring L2 cache events.
90
Agustin Vega-Frias3071f132017-03-31 14:13:43 -040091config QCOM_L3_PMU
92 bool "Qualcomm Technologies L3-cache PMU"
Mark Rutlandbddb9b62017-06-13 13:45:51 +010093 depends on ARCH_QCOM && ARM64 && ACPI
Agustin Vega-Frias3071f132017-03-31 14:13:43 -040094 select QCOM_IRQ_COMBINER
95 help
96 Provides support for the L3 cache performance monitor unit (PMU)
97 in Qualcomm Technologies processors.
98 Adds the L3 cache PMU into the perf events subsystem for
99 monitoring L3 cache events.
100
Kulkarni, Ganapatrao69c32972018-12-06 11:51:31 +0000101config THUNDERX2_PMU
102 tristate "Cavium ThunderX2 SoC PMU UNCORE"
103 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
104 default m
105 help
106 Provides support for ThunderX2 UNCORE events.
107 The SoC has PMU support in its L3 cache controller (L3C) and
108 in the DDR4 Memory Controller (DMC).
109
Tai Nguyen832c9272016-07-15 10:38:04 -0700110config XGENE_PMU
Mark Rutlandbddb9b62017-06-13 13:45:51 +0100111 depends on ARCH_XGENE
Tai Nguyen832c9272016-07-15 10:38:04 -0700112 bool "APM X-Gene SoC PMU"
113 default n
114 help
115 Say y if you want to use APM X-Gene SoC performance monitors.
116
Will Deacond5d96962016-09-22 11:36:32 +0100117config ARM_SPE_PMU
118 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
John Garryb89205b2018-05-22 23:54:04 +0800119 depends on ARM64
Will Deacond5d96962016-09-22 11:36:32 +0100120 help
121 Enable perf support for the ARMv8.2 Statistical Profiling
122 Extension, which provides periodic sampling of operations in
123 the CPU pipeline and reports this via the perf AUX interface.
124
Zhou Wang97807322020-05-07 10:58:25 +0800125source "drivers/perf/hisilicon/Kconfig"
126
Mark Rutlandfa8ad782015-07-06 12:23:53 +0100127endmenu