| Suman Anna | eebba71 | 2018-05-11 12:03:16 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| Ohad Ben-Cohen | bd9a4c7 | 2011-02-17 09:52:03 -0800 | [diff] [blame] | 2 | # |
| 3 | # Generic HWSPINLOCK framework |
| 4 | # |
| 5 | |
| Vincent Legoll | 35fc8a0 | 2017-04-11 16:21:02 +0200 | [diff] [blame] | 6 | menuconfig HWSPINLOCK |
| Baolin Wang | d048236 | 2017-11-04 14:37:48 +0800 | [diff] [blame] | 7 | bool "Hardware Spinlock drivers" |
| Simon Que | 70ba4cc | 2011-02-17 09:52:03 -0800 | [diff] [blame] | 8 | |
| Ezequiel Garcia | 285e74a | 2020-04-14 19:09:43 -0300 | [diff] [blame] | 9 | if HWSPINLOCK |
| 10 | |
| Simon Que | 70ba4cc | 2011-02-17 09:52:03 -0800 | [diff] [blame] | 11 | config HWSPINLOCK_OMAP |
| 12 | tristate "OMAP Hardware Spinlock device" |
| Baolin Wang | ffd0bbf | 2020-02-10 17:01:07 +0800 | [diff] [blame] | 13 | depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX || SOC_AM43XX || ARCH_K3 || COMPILE_TEST |
| Simon Que | 70ba4cc | 2011-02-17 09:52:03 -0800 | [diff] [blame] | 14 | help |
| 15 | Say y here to support the OMAP Hardware Spinlock device (firstly |
| 16 | introduced in OMAP4). |
| 17 | |
| 18 | If unsure, say N. |
| Ohad Ben-Cohen | 315d8f5 | 2011-09-04 23:19:51 +0300 | [diff] [blame] | 19 | |
| Bjorn Andersson | 19a0f61 | 2015-03-24 10:11:05 -0700 | [diff] [blame] | 20 | config HWSPINLOCK_QCOM |
| 21 | tristate "Qualcomm Hardware Spinlock device" |
| Baolin Wang | ffd0bbf | 2020-02-10 17:01:07 +0800 | [diff] [blame] | 22 | depends on ARCH_QCOM || COMPILE_TEST |
| Bjorn Andersson | 19a0f61 | 2015-03-24 10:11:05 -0700 | [diff] [blame] | 23 | select MFD_SYSCON |
| 24 | help |
| 25 | Say y here to support the Qualcomm Hardware Mutex functionality, which |
| 26 | provides a synchronisation mechanism for the various processors on |
| 27 | the SoC. |
| 28 | |
| 29 | If unsure, say N. |
| 30 | |
| Baolin Wang | d8c8bbb | 2017-05-17 13:59:29 +0800 | [diff] [blame] | 31 | config HWSPINLOCK_SPRD |
| 32 | tristate "SPRD Hardware Spinlock device" |
| Baolin Wang | ffd0bbf | 2020-02-10 17:01:07 +0800 | [diff] [blame] | 33 | depends on ARCH_SPRD || COMPILE_TEST |
| Baolin Wang | d8c8bbb | 2017-05-17 13:59:29 +0800 | [diff] [blame] | 34 | help |
| 35 | Say y here to support the SPRD Hardware Spinlock device. |
| 36 | |
| 37 | If unsure, say N. |
| 38 | |
| Benjamin Gaignard | f24fcff | 2018-11-14 10:00:25 +0100 | [diff] [blame] | 39 | config HWSPINLOCK_STM32 |
| 40 | tristate "STM32 Hardware Spinlock device" |
| Baolin Wang | ffd0bbf | 2020-02-10 17:01:07 +0800 | [diff] [blame] | 41 | depends on MACH_STM32MP157 || COMPILE_TEST |
| Benjamin Gaignard | f24fcff | 2018-11-14 10:00:25 +0100 | [diff] [blame] | 42 | help |
| 43 | Say y here to support the STM32 Hardware Spinlock device. |
| 44 | |
| 45 | If unsure, say N. |
| 46 | |
| Wilken Gottwalt | 3c881e0 | 2021-03-14 10:31:13 +0100 | [diff] [blame] | 47 | config HWSPINLOCK_SUN6I |
| 48 | tristate "SUN6I Hardware Spinlock device" |
| 49 | depends on ARCH_SUNXI || COMPILE_TEST |
| 50 | help |
| 51 | Say y here to support the SUN6I Hardware Spinlock device which can be |
| 52 | found in most of the sun6i compatible Allwinner SoCs. |
| 53 | |
| 54 | If unsure, say N. |
| 55 | |
| Mathieu J. Poirier | f84a8ec | 2011-09-08 22:47:40 +0300 | [diff] [blame] | 56 | config HSEM_U8500 |
| 57 | tristate "STE Hardware Semaphore functionality" |
| Baolin Wang | ffd0bbf | 2020-02-10 17:01:07 +0800 | [diff] [blame] | 58 | depends on ARCH_U8500 || COMPILE_TEST |
| Mathieu J. Poirier | f84a8ec | 2011-09-08 22:47:40 +0300 | [diff] [blame] | 59 | help |
| 60 | Say y here to support the STE Hardware Semaphore functionality, which |
| 61 | provides a synchronisation mechanism for the various processor on the |
| 62 | SoC. |
| 63 | |
| 64 | If unsure, say N. |
| Ezequiel Garcia | 285e74a | 2020-04-14 19:09:43 -0300 | [diff] [blame] | 65 | |
| 66 | endif # HWSPINLOCK |