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Michael Walle815364d2019-12-10 00:43:50 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Device Tree file for the Kontron SMARC-sAL28 board.
4 *
Michael Walle67833802021-08-31 15:40:12 +02005 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
Michael Walle815364d2019-12-10 00:43:50 +01006 *
7 */
8
9/dts-v1/;
10#include "fsl-ls1028a.dtsi"
Michael Wallec86e4202020-09-14 23:43:37 +020011#include <dt-bindings/interrupt-controller/irq.h>
Michael Walle945710b2020-09-14 23:43:38 +020012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
Michael Walle815364d2019-12-10 00:43:50 +010014
15/ {
16 model = "Kontron SMARC-sAL28";
17 compatible = "kontron,sl28", "fsl,ls1028a";
18
19 aliases {
20 crypto = &crypto;
21 serial0 = &duart0;
22 serial1 = &duart1;
Michael Wallea0a44422020-05-05 17:00:37 +020023 serial2 = &lpuart1;
Michael Walle1bc72a42020-03-11 08:49:26 +010024 spi0 = &fspi;
25 spi1 = &dspi2;
Vladimir Oltean2e6cde92020-11-19 18:38:21 +020026 mmc0 = &esdhc1;
27 mmc1 = &esdhc;
Michael Walle51c8eaa2021-03-23 16:07:57 +010028 rtc0 = &rtc;
Michael Wallec75dc982021-03-23 16:07:56 +010029 rtc1 = &ftm_alarm0;
Michael Walle815364d2019-12-10 00:43:50 +010030 };
31
Michael Walle945710b2020-09-14 23:43:38 +020032 buttons0 {
33 compatible = "gpio-keys";
34
35 power-button {
36 interrupts-extended = <&sl28cpld_intc
37 4 IRQ_TYPE_EDGE_BOTH>;
38 linux,code = <KEY_POWER>;
39 label = "Power";
40 };
41
42 sleep-button {
43 interrupts-extended = <&sl28cpld_intc
44 5 IRQ_TYPE_EDGE_BOTH>;
45 linux,code = <KEY_SLEEP>;
46 label = "Sleep";
47 };
48 };
49
50 buttons1 {
51 compatible = "gpio-keys-polled";
52 poll-interval = <200>;
53
54 lid-switch {
55 linux,input-type = <EV_SW>;
56 linux,code = <SW_LID>;
57 gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>;
58 label = "Lid";
59 };
60 };
61
Michael Walle815364d2019-12-10 00:43:50 +010062 chosen {
63 stdout-path = "serial0:115200n8";
64 };
65};
66
Michael Walle7e2ac9d2020-10-01 11:11:31 +020067&can0 {
68 status = "okay";
69};
70
Michael Walle1bc72a42020-03-11 08:49:26 +010071&dspi2 {
72 status = "okay";
73};
74
Michael Walle815364d2019-12-10 00:43:50 +010075&duart0 {
76 status = "okay";
77};
78
79&duart1 {
80 status = "okay";
81};
82
Michael Walle67833802021-08-31 15:40:12 +020083&enetc_mdio_pf3 {
84 phy0: ethernet-phy@5 {
85 reg = <0x5>;
86 eee-broken-1000t;
87 eee-broken-100tx;
88 };
89};
90
Michael Walle815364d2019-12-10 00:43:50 +010091&enetc_port0 {
92 phy-handle = <&phy0>;
Michael Wallecaa355c2021-08-31 15:40:13 +020093 phy-mode = "sgmii";
Michael Walledf392ae2020-11-09 12:04:36 +010094 managed = "in-band-status";
Michael Wallee46b08b2020-02-24 12:50:52 +010095 status = "okay";
Michael Walle815364d2019-12-10 00:43:50 +010096};
97
98&esdhc {
99 sd-uhs-sdr104;
100 sd-uhs-sdr50;
101 sd-uhs-sdr25;
102 sd-uhs-sdr12;
103 status = "okay";
104};
105
106&esdhc1 {
107 mmc-hs200-1_8v;
108 mmc-hs400-1_8v;
109 bus-width = <8>;
110 status = "okay";
111};
112
113&fspi {
114 status = "okay";
115
116 flash@0 {
Michael Walle815364d2019-12-10 00:43:50 +0100117 compatible = "jedec,spi-nor";
118 m25p,fast-read;
119 spi-max-frequency = <133000000>;
120 reg = <0>;
121 /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
122 spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
123 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
124
Michael Walleaa494332021-03-18 18:18:55 +0100125 partitions {
126 compatible = "fixed-partitions";
127 #address-cells = <1>;
128 #size-cells = <1>;
Michael Walle815364d2019-12-10 00:43:50 +0100129
Michael Walleaa494332021-03-18 18:18:55 +0100130 partition@0 {
131 reg = <0x000000 0x010000>;
132 label = "rcw";
133 read-only;
134 };
Michael Walle815364d2019-12-10 00:43:50 +0100135
Michael Walleaa494332021-03-18 18:18:55 +0100136 partition@10000 {
Michael Walleb3535532021-03-18 18:18:56 +0100137 reg = <0x010000 0x1d0000>;
Michael Walleaa494332021-03-18 18:18:55 +0100138 label = "failsafe bootloader";
139 read-only;
140 };
Michael Walle815364d2019-12-10 00:43:50 +0100141
Michael Walleaa494332021-03-18 18:18:55 +0100142 partition@200000 {
143 reg = <0x200000 0x010000>;
144 label = "configuration store";
145 };
Michael Walle815364d2019-12-10 00:43:50 +0100146
Michael Walleaa494332021-03-18 18:18:55 +0100147 partition@210000 {
148 reg = <0x210000 0x1d0000>;
149 label = "bootloader";
150 };
151
152 partition@3e0000 {
153 reg = <0x3e0000 0x020000>;
154 label = "bootloader environment";
155 };
Michael Walle815364d2019-12-10 00:43:50 +0100156 };
157 };
158};
159
160&gpio1 {
161 gpio-line-names =
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "TDO", "TCK",
165 "", "", "", "", "", "", "", "";
166};
167
168&gpio2 {
169 gpio-line-names =
170 "", "", "", "", "", "", "TMS", "TDI",
171 "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "";
174};
175
176&i2c0 {
177 status = "okay";
178
Michael Walle51c8eaa2021-03-23 16:07:57 +0100179 rtc: rtc@32 {
Michael Walle815364d2019-12-10 00:43:50 +0100180 compatible = "microcrystal,rv8803";
181 reg = <0x32>;
182 };
183
Michael Wallec86e4202020-09-14 23:43:37 +0200184 sl28cpld@4a {
185 compatible = "kontron,sl28cpld";
186 reg = <0x4a>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189
190 watchdog@4 {
191 compatible = "kontron,sl28cpld-wdt";
192 reg = <0x4>;
193 kontron,assert-wdt-timeout-pin;
194 };
195
196 hwmon@b {
197 compatible = "kontron,sl28cpld-fan";
198 reg = <0xb>;
199 };
200
201 sl28cpld_pwm0: pwm@c {
202 compatible = "kontron,sl28cpld-pwm";
203 reg = <0xc>;
204 #pwm-cells = <2>;
205 };
206
207 sl28cpld_pwm1: pwm@e {
208 compatible = "kontron,sl28cpld-pwm";
209 reg = <0xe>;
210 #pwm-cells = <2>;
211 };
212
213 sl28cpld_gpio0: gpio@10 {
214 compatible = "kontron,sl28cpld-gpio";
215 reg = <0x10>;
216 interrupts-extended = <&gpio2 6
217 IRQ_TYPE_EDGE_FALLING>;
218
219 gpio-controller;
220 #gpio-cells = <2>;
221 gpio-line-names =
222 "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",
223 "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",
224 "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",
225 "GPIO6_TACHIN", "GPIO7";
226
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 };
230
231 sl28cpld_gpio1: gpio@15 {
232 compatible = "kontron,sl28cpld-gpio";
233 reg = <0x15>;
234 interrupts-extended = <&gpio2 6
235 IRQ_TYPE_EDGE_FALLING>;
236
237 gpio-controller;
238 #gpio-cells = <2>;
239 gpio-line-names =
240 "GPIO8", "GPIO9", "GPIO10", "GPIO11",
241 "", "", "", "";
242
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 };
246
247 sl28cpld_gpio2: gpio@1a {
248 compatible = "kontron,sl28cpld-gpo";
249 reg = <0x1a>;
250
251 gpio-controller;
252 #gpio-cells = <2>;
253 gpio-line-names =
254 "LCD0 voltage enable",
255 "LCD0 backlight enable",
256 "eMMC reset", "LVDS bridge reset",
257 "LVDS bridge power-down",
258 "SDIO power enable",
259 "", "";
260 };
261
262 sl28cpld_gpio3: gpio@1b {
263 compatible = "kontron,sl28cpld-gpi";
264 reg = <0x1b>;
265
266 gpio-controller;
267 #gpio-cells = <2>;
268 gpio-line-names =
269 "Power button", "Force recovery", "Sleep",
270 "Battery low", "Lid state", "Charging",
271 "Charger present", "";
272 };
273
274 sl28cpld_intc: interrupt-controller@1c {
275 compatible = "kontron,sl28cpld-intc";
276 reg = <0x1c>;
277 interrupts-extended = <&gpio2 6
278 IRQ_TYPE_EDGE_FALLING>;
279
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283 };
284
Michael Walle815364d2019-12-10 00:43:50 +0100285 eeprom@50 {
286 compatible = "atmel,24c32";
287 reg = <0x50>;
288 pagesize = <32>;
289 };
290};
291
292&i2c3 {
293 status = "okay";
294};
295
296&i2c4 {
297 status = "okay";
Michael Wallef05cd1c22020-03-11 08:49:27 +0100298
299 eeprom@50 {
300 compatible = "atmel,24c32";
301 reg = <0x50>;
302 pagesize = <32>;
303 };
Michael Walle815364d2019-12-10 00:43:50 +0100304};
Michael Wallea0a44422020-05-05 17:00:37 +0200305
306&lpuart1 {
307 status = "okay";
308};
Michael Walle70293be2021-08-31 15:40:11 +0200309
310&usb0 {
311 status = "okay";
312};
313
314&usb1 {
315 status = "okay";
316};