Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
Mauro Carvalho Chehab | c0c6e08 | 2017-05-14 12:03:39 -0300 | [diff] [blame] | 10 | * Detailed information is available in Documentation/core-api/genericirq.rst |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
Jiang Liu | f8264e3 | 2014-11-06 22:20:14 +0800 | [diff] [blame] | 18 | #include <linux/irqdomain.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 19 | |
Steven Rostedt | f069686 | 2012-01-25 20:18:55 -0500 | [diff] [blame] | 20 | #include <trace/events/irq.h> |
| 21 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 22 | #include "internals.h" |
| 23 | |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 24 | static irqreturn_t bad_chained_irq(int irq, void *dev_id) |
| 25 | { |
| 26 | WARN_ONCE(1, "Chained irq %d should not call an action\n", irq); |
| 27 | return IRQ_NONE; |
| 28 | } |
| 29 | |
| 30 | /* |
| 31 | * Chained handlers should never call action on their IRQ. This default |
| 32 | * action will emit warning if such thing happens. |
| 33 | */ |
| 34 | struct irqaction chained_action = { |
| 35 | .handler = bad_chained_irq, |
| 36 | }; |
| 37 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 38 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 39 | * irq_set_chip - set the irq chip for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 40 | * @irq: irq number |
| 41 | * @chip: pointer to irq chip description structure |
| 42 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 43 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 44 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 45 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 46 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 47 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 48 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 49 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | |
| 51 | if (!chip) |
| 52 | chip = &no_irq_chip; |
| 53 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 54 | desc->irq_data.chip = chip; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 55 | irq_put_desc_unlock(desc, flags); |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 56 | /* |
| 57 | * For !CONFIG_SPARSE_IRQ make the irq show up in |
Thomas Gleixner | f63b6a0 | 2014-05-07 15:44:21 +0000 | [diff] [blame] | 58 | * allocated_irqs. |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 59 | */ |
Thomas Gleixner | f63b6a0 | 2014-05-07 15:44:21 +0000 | [diff] [blame] | 60 | irq_mark_irq(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 61 | return 0; |
| 62 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 63 | EXPORT_SYMBOL(irq_set_chip); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 64 | |
| 65 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 66 | * irq_set_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 67 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 68 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 69 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 70 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 72 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 73 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 74 | int ret = 0; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 75 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 76 | if (!desc) |
| 77 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 78 | |
Jiang Liu | a1ff541 | 2015-06-23 19:47:29 +0200 | [diff] [blame] | 79 | ret = __irq_set_trigger(desc, type); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 80 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 81 | return ret; |
| 82 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 83 | EXPORT_SYMBOL(irq_set_irq_type); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 84 | |
| 85 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 86 | * irq_set_handler_data - set irq handler data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 87 | * @irq: Interrupt number |
| 88 | * @data: Pointer to interrupt specific data |
| 89 | * |
| 90 | * Set the hardware irq controller data for an irq |
| 91 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 92 | int irq_set_handler_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 93 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 94 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 95 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 96 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 97 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 98 | return -EINVAL; |
Jiang Liu | af7080e | 2015-06-01 16:05:21 +0800 | [diff] [blame] | 99 | desc->irq_common_data.handler_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 100 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 101 | return 0; |
| 102 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 103 | EXPORT_SYMBOL(irq_set_handler_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 104 | |
| 105 | /** |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 106 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
| 107 | * @irq_base: Interrupt number base |
| 108 | * @irq_offset: Interrupt number offset |
| 109 | * @entry: Pointer to MSI descriptor data |
| 110 | * |
| 111 | * Set the MSI descriptor entry for an irq at offset |
| 112 | */ |
| 113 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
| 114 | struct msi_desc *entry) |
| 115 | { |
| 116 | unsigned long flags; |
| 117 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
| 118 | |
| 119 | if (!desc) |
| 120 | return -EINVAL; |
Jiang Liu | b237721 | 2015-06-01 16:05:43 +0800 | [diff] [blame] | 121 | desc->irq_common_data.msi_desc = entry; |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 122 | if (entry && !irq_offset) |
| 123 | entry->irq = irq_base; |
| 124 | irq_put_desc_unlock(desc, flags); |
| 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 129 | * irq_set_msi_desc - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 130 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 131 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 132 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 133 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 134 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 135 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 136 | { |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 137 | return irq_set_msi_desc_off(irq, 0, entry); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 141 | * irq_set_chip_data - set irq chip data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 142 | * @irq: Interrupt number |
| 143 | * @data: Pointer to chip specific data |
| 144 | * |
| 145 | * Set the hardware irq chip data for an irq |
| 146 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 147 | int irq_set_chip_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 148 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 149 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 150 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 151 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 152 | if (!desc) |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 153 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 154 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 155 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 156 | return 0; |
| 157 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 158 | EXPORT_SYMBOL(irq_set_chip_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 159 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 160 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 161 | { |
| 162 | struct irq_desc *desc = irq_to_desc(irq); |
| 163 | |
| 164 | return desc ? &desc->irq_data : NULL; |
| 165 | } |
| 166 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 167 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 168 | static void irq_state_clr_disabled(struct irq_desc *desc) |
| 169 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 170 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 171 | } |
| 172 | |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 173 | static void irq_state_clr_masked(struct irq_desc *desc) |
| 174 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 175 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 176 | } |
| 177 | |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 178 | static void irq_state_clr_started(struct irq_desc *desc) |
| 179 | { |
| 180 | irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED); |
| 181 | } |
| 182 | |
| 183 | static void irq_state_set_started(struct irq_desc *desc) |
| 184 | { |
| 185 | irqd_set(&desc->irq_data, IRQD_IRQ_STARTED); |
| 186 | } |
| 187 | |
Thomas Gleixner | 761ea38 | 2017-06-20 01:37:50 +0200 | [diff] [blame] | 188 | enum { |
| 189 | IRQ_STARTUP_NORMAL, |
| 190 | IRQ_STARTUP_MANAGED, |
| 191 | IRQ_STARTUP_ABORT, |
| 192 | }; |
| 193 | |
| 194 | #ifdef CONFIG_SMP |
| 195 | static int |
| 196 | __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force) |
| 197 | { |
| 198 | struct irq_data *d = irq_desc_get_irq_data(desc); |
| 199 | |
| 200 | if (!irqd_affinity_is_managed(d)) |
| 201 | return IRQ_STARTUP_NORMAL; |
| 202 | |
| 203 | irqd_clr_managed_shutdown(d); |
| 204 | |
| 205 | if (cpumask_any_and(aff, cpu_online_mask) > nr_cpu_ids) { |
| 206 | /* |
| 207 | * Catch code which fiddles with enable_irq() on a managed |
| 208 | * and potentially shutdown IRQ. Chained interrupt |
| 209 | * installment or irq auto probing should not happen on |
| 210 | * managed irqs either. Emit a warning, break the affinity |
| 211 | * and start it up as a normal interrupt. |
| 212 | */ |
| 213 | if (WARN_ON_ONCE(force)) |
| 214 | return IRQ_STARTUP_NORMAL; |
| 215 | /* |
| 216 | * The interrupt was requested, but there is no online CPU |
| 217 | * in it's affinity mask. Put it into managed shutdown |
| 218 | * state and let the cpu hotplug mechanism start it up once |
| 219 | * a CPU in the mask becomes available. |
| 220 | */ |
| 221 | irqd_set_managed_shutdown(d); |
| 222 | return IRQ_STARTUP_ABORT; |
| 223 | } |
| 224 | return IRQ_STARTUP_MANAGED; |
| 225 | } |
| 226 | #else |
Geert Uytterhoeven | 2372a51 | 2017-07-04 12:06:01 +0200 | [diff] [blame] | 227 | static __always_inline int |
Thomas Gleixner | 761ea38 | 2017-06-20 01:37:50 +0200 | [diff] [blame] | 228 | __irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force) |
| 229 | { |
| 230 | return IRQ_STARTUP_NORMAL; |
| 231 | } |
| 232 | #endif |
| 233 | |
Thomas Gleixner | 708d174 | 2017-06-20 01:37:48 +0200 | [diff] [blame] | 234 | static int __irq_startup(struct irq_desc *desc) |
| 235 | { |
| 236 | struct irq_data *d = irq_desc_get_irq_data(desc); |
| 237 | int ret = 0; |
| 238 | |
| 239 | irq_domain_activate_irq(d); |
| 240 | if (d->chip->irq_startup) { |
| 241 | ret = d->chip->irq_startup(d); |
| 242 | irq_state_clr_disabled(desc); |
| 243 | irq_state_clr_masked(desc); |
| 244 | } else { |
| 245 | irq_enable(desc); |
| 246 | } |
| 247 | irq_state_set_started(desc); |
| 248 | return ret; |
| 249 | } |
| 250 | |
Thomas Gleixner | 4cde9c6 | 2017-06-20 01:37:49 +0200 | [diff] [blame] | 251 | int irq_startup(struct irq_desc *desc, bool resend, bool force) |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 252 | { |
Thomas Gleixner | 761ea38 | 2017-06-20 01:37:50 +0200 | [diff] [blame] | 253 | struct irq_data *d = irq_desc_get_irq_data(desc); |
| 254 | struct cpumask *aff = irq_data_get_affinity_mask(d); |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 255 | int ret = 0; |
| 256 | |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 257 | desc->depth = 0; |
| 258 | |
Thomas Gleixner | 761ea38 | 2017-06-20 01:37:50 +0200 | [diff] [blame] | 259 | if (irqd_is_started(d)) { |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 260 | irq_enable(desc); |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 261 | } else { |
Thomas Gleixner | 761ea38 | 2017-06-20 01:37:50 +0200 | [diff] [blame] | 262 | switch (__irq_startup_managed(desc, aff, force)) { |
| 263 | case IRQ_STARTUP_NORMAL: |
| 264 | ret = __irq_startup(desc); |
| 265 | irq_setup_affinity(desc); |
| 266 | break; |
| 267 | case IRQ_STARTUP_MANAGED: |
| 268 | ret = __irq_startup(desc); |
| 269 | irq_set_affinity_locked(d, aff, false); |
| 270 | break; |
| 271 | case IRQ_STARTUP_ABORT: |
| 272 | return 0; |
| 273 | } |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 274 | } |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 275 | if (resend) |
Jiang Liu | 0798abe | 2015-06-04 12:13:27 +0800 | [diff] [blame] | 276 | check_irq_resend(desc); |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 277 | |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 278 | return ret; |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 279 | } |
| 280 | |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 281 | static void __irq_disable(struct irq_desc *desc, bool mask); |
| 282 | |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 283 | void irq_shutdown(struct irq_desc *desc) |
| 284 | { |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 285 | if (irqd_is_started(&desc->irq_data)) { |
| 286 | desc->depth = 1; |
| 287 | if (desc->irq_data.chip->irq_shutdown) { |
| 288 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); |
| 289 | irq_state_set_disabled(desc); |
| 290 | irq_state_set_masked(desc); |
| 291 | } else { |
| 292 | __irq_disable(desc, true); |
| 293 | } |
| 294 | irq_state_clr_started(desc); |
| 295 | } |
| 296 | /* |
| 297 | * This must be called even if the interrupt was never started up, |
| 298 | * because the activation can happen before the interrupt is |
| 299 | * available for request/startup. It has it's own state tracking so |
| 300 | * it's safe to call it unconditionally. |
| 301 | */ |
Jiang Liu | f8264e3 | 2014-11-06 22:20:14 +0800 | [diff] [blame] | 302 | irq_domain_deactivate_irq(&desc->irq_data); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 303 | } |
| 304 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 305 | void irq_enable(struct irq_desc *desc) |
| 306 | { |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 307 | if (!irqd_irq_disabled(&desc->irq_data)) { |
| 308 | unmask_irq(desc); |
| 309 | } else { |
| 310 | irq_state_clr_disabled(desc); |
| 311 | if (desc->irq_data.chip->irq_enable) { |
| 312 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 313 | irq_state_clr_masked(desc); |
| 314 | } else { |
| 315 | unmask_irq(desc); |
| 316 | } |
| 317 | } |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 318 | } |
| 319 | |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 320 | static void __irq_disable(struct irq_desc *desc, bool mask) |
| 321 | { |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 322 | if (irqd_irq_disabled(&desc->irq_data)) { |
| 323 | if (mask) |
| 324 | mask_irq(desc); |
| 325 | } else { |
| 326 | irq_state_set_disabled(desc); |
| 327 | if (desc->irq_data.chip->irq_disable) { |
| 328 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 329 | irq_state_set_masked(desc); |
| 330 | } else if (mask) { |
| 331 | mask_irq(desc); |
| 332 | } |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 333 | } |
| 334 | } |
| 335 | |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 336 | /** |
Xie XiuQi | f788e7b | 2013-10-18 09:12:04 +0800 | [diff] [blame] | 337 | * irq_disable - Mark interrupt disabled |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 338 | * @desc: irq descriptor which should be disabled |
| 339 | * |
| 340 | * If the chip does not implement the irq_disable callback, we |
| 341 | * use a lazy disable approach. That means we mark the interrupt |
| 342 | * disabled, but leave the hardware unmasked. That's an |
| 343 | * optimization because we avoid the hardware access for the |
| 344 | * common case where no interrupt happens after we marked it |
| 345 | * disabled. If an interrupt happens, then the interrupt flow |
| 346 | * handler masks the line at the hardware level and marks it |
| 347 | * pending. |
Thomas Gleixner | e984977 | 2015-10-09 23:28:58 +0200 | [diff] [blame] | 348 | * |
| 349 | * If the interrupt chip does not implement the irq_disable callback, |
| 350 | * a driver can disable the lazy approach for a particular irq line by |
| 351 | * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can |
| 352 | * be used for devices which cannot disable the interrupt at the |
| 353 | * device level under certain circumstances and have to use |
| 354 | * disable_irq[_nosync] instead. |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 355 | */ |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 356 | void irq_disable(struct irq_desc *desc) |
| 357 | { |
Thomas Gleixner | 201d7f4 | 2017-05-31 11:58:32 +0200 | [diff] [blame] | 358 | __irq_disable(desc, irq_settings_disable_unlazy(desc)); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 359 | } |
| 360 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 361 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
| 362 | { |
| 363 | if (desc->irq_data.chip->irq_enable) |
| 364 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 365 | else |
| 366 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
| 367 | cpumask_set_cpu(cpu, desc->percpu_enabled); |
| 368 | } |
| 369 | |
| 370 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) |
| 371 | { |
| 372 | if (desc->irq_data.chip->irq_disable) |
| 373 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 374 | else |
| 375 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
| 376 | cpumask_clear_cpu(cpu, desc->percpu_enabled); |
| 377 | } |
| 378 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 379 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 380 | { |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 381 | if (desc->irq_data.chip->irq_mask_ack) { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 382 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 383 | irq_state_set_masked(desc); |
| 384 | } else { |
| 385 | mask_irq(desc); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 386 | if (desc->irq_data.chip->irq_ack) |
| 387 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 388 | } |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 389 | } |
| 390 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 391 | void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 392 | { |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 393 | if (irqd_irq_masked(&desc->irq_data)) |
| 394 | return; |
| 395 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 396 | if (desc->irq_data.chip->irq_mask) { |
| 397 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 398 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 399 | } |
| 400 | } |
| 401 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 402 | void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 403 | { |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 404 | if (!irqd_irq_masked(&desc->irq_data)) |
| 405 | return; |
| 406 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 407 | if (desc->irq_data.chip->irq_unmask) { |
| 408 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 409 | irq_state_clr_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 410 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 411 | } |
| 412 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 413 | void unmask_threaded_irq(struct irq_desc *desc) |
| 414 | { |
| 415 | struct irq_chip *chip = desc->irq_data.chip; |
| 416 | |
| 417 | if (chip->flags & IRQCHIP_EOI_THREADED) |
| 418 | chip->irq_eoi(&desc->irq_data); |
| 419 | |
Jeffy Chen | bf22ff45 | 2017-06-26 19:33:34 +0800 | [diff] [blame] | 420 | unmask_irq(desc); |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 421 | } |
| 422 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 423 | /* |
| 424 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 425 | * @irq: the interrupt number |
| 426 | * |
| 427 | * Handle interrupts which are nested into a threaded interrupt |
| 428 | * handler. The handler function is called inside the calling |
| 429 | * threads context. |
| 430 | */ |
| 431 | void handle_nested_irq(unsigned int irq) |
| 432 | { |
| 433 | struct irq_desc *desc = irq_to_desc(irq); |
| 434 | struct irqaction *action; |
| 435 | irqreturn_t action_ret; |
| 436 | |
| 437 | might_sleep(); |
| 438 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 439 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 440 | |
Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 441 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 442 | |
| 443 | action = desc->action; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 444 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
| 445 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 446 | goto out_unlock; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 447 | } |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 448 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 449 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 450 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 451 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 452 | |
Charles Keepax | 45e5202 | 2017-03-07 16:28:18 +0000 | [diff] [blame] | 453 | action_ret = IRQ_NONE; |
| 454 | for_each_action_of_desc(desc, action) |
| 455 | action_ret |= action->thread_fn(action->irq, action->dev_id); |
| 456 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 457 | if (!noirqdebug) |
Jiang Liu | 0dcdbc9 | 2015-06-04 12:13:28 +0800 | [diff] [blame] | 458 | note_interrupt(desc, action_ret); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 459 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 460 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 461 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 462 | |
| 463 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 464 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 465 | } |
| 466 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 467 | |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 468 | static bool irq_check_poll(struct irq_desc *desc) |
| 469 | { |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 470 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 471 | return false; |
| 472 | return irq_wait_for_poll(desc); |
| 473 | } |
| 474 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 475 | static bool irq_may_run(struct irq_desc *desc) |
| 476 | { |
Thomas Gleixner | 9ce7a25 | 2014-08-29 14:00:16 +0200 | [diff] [blame] | 477 | unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; |
| 478 | |
| 479 | /* |
| 480 | * If the interrupt is not in progress and is not an armed |
| 481 | * wakeup interrupt, proceed. |
| 482 | */ |
| 483 | if (!irqd_has_set(&desc->irq_data, mask)) |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 484 | return true; |
Thomas Gleixner | 9ce7a25 | 2014-08-29 14:00:16 +0200 | [diff] [blame] | 485 | |
| 486 | /* |
| 487 | * If the interrupt is an armed wakeup source, mark it pending |
| 488 | * and suspended, disable it and notify the pm core about the |
| 489 | * event. |
| 490 | */ |
| 491 | if (irq_pm_check_wakeup(desc)) |
| 492 | return false; |
| 493 | |
| 494 | /* |
| 495 | * Handle a potential concurrent poll on a different core. |
| 496 | */ |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 497 | return irq_check_poll(desc); |
| 498 | } |
| 499 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 500 | /** |
| 501 | * handle_simple_irq - Simple and software-decoded IRQs. |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 502 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 503 | * |
| 504 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 505 | * handler or come from hardware, where no interrupt hardware control |
| 506 | * is necessary. |
| 507 | * |
| 508 | * Note: The caller is expected to handle the ack, clear, mask and |
| 509 | * unmask issues if necessary. |
| 510 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 511 | void handle_simple_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 512 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 513 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 514 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 515 | if (!irq_may_run(desc)) |
| 516 | goto out_unlock; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 517 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 518 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 519 | |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 520 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 521 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 522 | goto out_unlock; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 523 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 524 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 525 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 526 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 527 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 528 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 529 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 530 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 531 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | |
Keith Busch | edd14cf | 2016-06-17 16:00:20 -0600 | [diff] [blame] | 533 | /** |
| 534 | * handle_untracked_irq - Simple and software-decoded IRQs. |
| 535 | * @desc: the interrupt description structure for this irq |
| 536 | * |
| 537 | * Untracked interrupts are sent from a demultiplexing interrupt |
| 538 | * handler when the demultiplexer does not know which device it its |
| 539 | * multiplexed irq domain generated the interrupt. IRQ's handled |
| 540 | * through here are not subjected to stats tracking, randomness, or |
| 541 | * spurious interrupt detection. |
| 542 | * |
| 543 | * Note: Like handle_simple_irq, the caller is expected to handle |
| 544 | * the ack, clear, mask and unmask issues if necessary. |
| 545 | */ |
| 546 | void handle_untracked_irq(struct irq_desc *desc) |
| 547 | { |
| 548 | unsigned int flags = 0; |
| 549 | |
| 550 | raw_spin_lock(&desc->lock); |
| 551 | |
| 552 | if (!irq_may_run(desc)) |
| 553 | goto out_unlock; |
| 554 | |
| 555 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
| 556 | |
| 557 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 558 | desc->istate |= IRQS_PENDING; |
| 559 | goto out_unlock; |
| 560 | } |
| 561 | |
| 562 | desc->istate &= ~IRQS_PENDING; |
| 563 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
| 564 | raw_spin_unlock(&desc->lock); |
| 565 | |
| 566 | __handle_irq_event_percpu(desc, &flags); |
| 567 | |
| 568 | raw_spin_lock(&desc->lock); |
| 569 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
| 570 | |
| 571 | out_unlock: |
| 572 | raw_spin_unlock(&desc->lock); |
| 573 | } |
| 574 | EXPORT_SYMBOL_GPL(handle_untracked_irq); |
| 575 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 576 | /* |
| 577 | * Called unconditionally from handle_level_irq() and only for oneshot |
| 578 | * interrupts from handle_fasteoi_irq() |
| 579 | */ |
| 580 | static void cond_unmask_irq(struct irq_desc *desc) |
| 581 | { |
| 582 | /* |
| 583 | * We need to unmask in the following cases: |
| 584 | * - Standard level irq (IRQF_ONESHOT is not set) |
| 585 | * - Oneshot irq which did not wake the thread (caused by a |
| 586 | * spurious interrupt or a primary handler handling it |
| 587 | * completely). |
| 588 | */ |
| 589 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 590 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) |
| 591 | unmask_irq(desc); |
| 592 | } |
| 593 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 594 | /** |
| 595 | * handle_level_irq - Level type irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 596 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 597 | * |
| 598 | * Level type interrupts are active as long as the hardware line has |
| 599 | * the active level. This may require to mask the interrupt and unmask |
| 600 | * it after the associated handler has acknowledged the device, so the |
| 601 | * interrupt line is back to inactive. |
| 602 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 603 | void handle_level_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 604 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 605 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 606 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 607 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 608 | if (!irq_may_run(desc)) |
| 609 | goto out_unlock; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 610 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 611 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 612 | |
| 613 | /* |
| 614 | * If its disabled or no action available |
| 615 | * keep it masked and get out of here |
| 616 | */ |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 617 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 618 | desc->istate |= IRQS_PENDING; |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 619 | goto out_unlock; |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 620 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 621 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 622 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 623 | handle_irq_event(desc); |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 624 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 625 | cond_unmask_irq(desc); |
| 626 | |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 627 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 628 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 629 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 630 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 631 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 632 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 633 | static inline void preflow_handler(struct irq_desc *desc) |
| 634 | { |
| 635 | if (desc->preflow_handler) |
| 636 | desc->preflow_handler(&desc->irq_data); |
| 637 | } |
| 638 | #else |
| 639 | static inline void preflow_handler(struct irq_desc *desc) { } |
| 640 | #endif |
| 641 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 642 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
| 643 | { |
| 644 | if (!(desc->istate & IRQS_ONESHOT)) { |
| 645 | chip->irq_eoi(&desc->irq_data); |
| 646 | return; |
| 647 | } |
| 648 | /* |
| 649 | * We need to unmask in the following cases: |
| 650 | * - Oneshot irq which did not wake the thread (caused by a |
| 651 | * spurious interrupt or a primary handler handling it |
| 652 | * completely). |
| 653 | */ |
| 654 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 655 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { |
| 656 | chip->irq_eoi(&desc->irq_data); |
| 657 | unmask_irq(desc); |
| 658 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { |
| 659 | chip->irq_eoi(&desc->irq_data); |
| 660 | } |
| 661 | } |
| 662 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 663 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 664 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 665 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 666 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 667 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 668 | * call when the interrupt has been serviced. This enables support |
| 669 | * for modern forms of interrupt handlers, which handle the flow |
| 670 | * details in hardware, transparently. |
| 671 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 672 | void handle_fasteoi_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 673 | { |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 674 | struct irq_chip *chip = desc->irq_data.chip; |
| 675 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 676 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 677 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 678 | if (!irq_may_run(desc)) |
| 679 | goto out; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 680 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 681 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 682 | |
| 683 | /* |
| 684 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 685 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 686 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 687 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 688 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 689 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 690 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 691 | } |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 692 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 693 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 694 | if (desc->istate & IRQS_ONESHOT) |
| 695 | mask_irq(desc); |
| 696 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 697 | preflow_handler(desc); |
Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 698 | handle_irq_event(desc); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 699 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 700 | cond_unmask_eoi_irq(desc, chip); |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 701 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 702 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 703 | return; |
| 704 | out: |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 705 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
| 706 | chip->irq_eoi(&desc->irq_data); |
| 707 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 708 | } |
Vincent Stehlé | 7cad45e | 2014-08-22 01:31:20 +0200 | [diff] [blame] | 709 | EXPORT_SYMBOL_GPL(handle_fasteoi_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 710 | |
| 711 | /** |
| 712 | * handle_edge_irq - edge type IRQ handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 713 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 714 | * |
| 715 | * Interrupt occures on the falling and/or rising edge of a hardware |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 716 | * signal. The occurrence is latched into the irq controller hardware |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 717 | * and must be acked in order to be reenabled. After the ack another |
| 718 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 719 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 720 | * might be necessary to disable (mask) the interrupt depending on the |
| 721 | * controller hardware. This requires to reenable the interrupt inside |
| 722 | * of the loop which handles the interrupts which have arrived while |
| 723 | * the handler was running. If all pending interrupts are handled, the |
| 724 | * loop is left. |
| 725 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 726 | void handle_edge_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 727 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 728 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 729 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 730 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 731 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 732 | if (!irq_may_run(desc)) { |
| 733 | desc->istate |= IRQS_PENDING; |
| 734 | mask_ack_irq(desc); |
| 735 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 736 | } |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 737 | |
| 738 | /* |
| 739 | * If its disabled or no action available then mask it and get |
| 740 | * out of here. |
| 741 | */ |
| 742 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
| 743 | desc->istate |= IRQS_PENDING; |
| 744 | mask_ack_irq(desc); |
| 745 | goto out_unlock; |
| 746 | } |
| 747 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 748 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 749 | |
| 750 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 751 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 752 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 753 | do { |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 754 | if (unlikely(!desc->action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 755 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 756 | goto out_unlock; |
| 757 | } |
| 758 | |
| 759 | /* |
| 760 | * When another irq arrived while we were handling |
| 761 | * one, we could have masked the irq. |
| 762 | * Renable it, if it was not disabled in meantime. |
| 763 | */ |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 764 | if (unlikely(desc->istate & IRQS_PENDING)) { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 765 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 766 | irqd_irq_masked(&desc->irq_data)) |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 767 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 768 | } |
| 769 | |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 770 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 771 | |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 772 | } while ((desc->istate & IRQS_PENDING) && |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 773 | !irqd_irq_disabled(&desc->irq_data)); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 774 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 775 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 776 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 777 | } |
Jiri Kosina | 3911ff3 | 2012-05-13 12:13:15 +0200 | [diff] [blame] | 778 | EXPORT_SYMBOL(handle_edge_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 779 | |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 780 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
| 781 | /** |
| 782 | * handle_edge_eoi_irq - edge eoi type IRQ handler |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 783 | * @desc: the interrupt description structure for this irq |
| 784 | * |
| 785 | * Similar as the above handle_edge_irq, but using eoi and w/o the |
| 786 | * mask/unmask logic. |
| 787 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 788 | void handle_edge_eoi_irq(struct irq_desc *desc) |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 789 | { |
| 790 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 791 | |
| 792 | raw_spin_lock(&desc->lock); |
| 793 | |
| 794 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 795 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 796 | if (!irq_may_run(desc)) { |
| 797 | desc->istate |= IRQS_PENDING; |
| 798 | goto out_eoi; |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 799 | } |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 800 | |
| 801 | /* |
| 802 | * If its disabled or no action available then mask it and get |
| 803 | * out of here. |
| 804 | */ |
| 805 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
| 806 | desc->istate |= IRQS_PENDING; |
| 807 | goto out_eoi; |
| 808 | } |
| 809 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 810 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 811 | |
| 812 | do { |
| 813 | if (unlikely(!desc->action)) |
| 814 | goto out_eoi; |
| 815 | |
| 816 | handle_irq_event(desc); |
| 817 | |
| 818 | } while ((desc->istate & IRQS_PENDING) && |
| 819 | !irqd_irq_disabled(&desc->irq_data)); |
| 820 | |
Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 821 | out_eoi: |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 822 | chip->irq_eoi(&desc->irq_data); |
| 823 | raw_spin_unlock(&desc->lock); |
| 824 | } |
| 825 | #endif |
| 826 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 827 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 828 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 829 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 830 | * |
| 831 | * Per CPU interrupts on SMP machines without locking requirements |
| 832 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 833 | void handle_percpu_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 834 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 835 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 836 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 837 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 838 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 839 | if (chip->irq_ack) |
| 840 | chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 841 | |
Huang Shijie | 71f6434 | 2015-09-02 10:24:55 +0800 | [diff] [blame] | 842 | handle_irq_event_percpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 843 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 844 | if (chip->irq_eoi) |
| 845 | chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 846 | } |
| 847 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 848 | /** |
| 849 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 850 | * @desc: the interrupt description structure for this irq |
| 851 | * |
| 852 | * Per CPU interrupts on SMP machines without locking requirements. Same as |
| 853 | * handle_percpu_irq() above but with the following extras: |
| 854 | * |
| 855 | * action->percpu_dev_id is a pointer to percpu variables which |
| 856 | * contain the real device id for the cpu on which this handler is |
| 857 | * called |
| 858 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 859 | void handle_percpu_devid_irq(struct irq_desc *desc) |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 860 | { |
| 861 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 862 | struct irqaction *action = desc->action; |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 863 | unsigned int irq = irq_desc_get_irq(desc); |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 864 | irqreturn_t res; |
| 865 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 866 | kstat_incr_irqs_this_cpu(desc); |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 867 | |
| 868 | if (chip->irq_ack) |
| 869 | chip->irq_ack(&desc->irq_data); |
| 870 | |
Thomas Gleixner | fc590c2 | 2016-09-02 14:45:19 +0200 | [diff] [blame] | 871 | if (likely(action)) { |
| 872 | trace_irq_handler_entry(irq, action); |
| 873 | res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id)); |
| 874 | trace_irq_handler_exit(irq, action, res); |
| 875 | } else { |
| 876 | unsigned int cpu = smp_processor_id(); |
| 877 | bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); |
| 878 | |
| 879 | if (enabled) |
| 880 | irq_percpu_disable(desc, cpu); |
| 881 | |
| 882 | pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n", |
| 883 | enabled ? " and unmasked" : "", irq, cpu); |
| 884 | } |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 885 | |
| 886 | if (chip->irq_eoi) |
| 887 | chip->irq_eoi(&desc->irq_data); |
| 888 | } |
| 889 | |
Wei Yongjun | b8129a1 | 2016-09-25 15:36:39 +0000 | [diff] [blame] | 890 | static void |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 891 | __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle, |
| 892 | int is_chained, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 893 | { |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 894 | if (!handle) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 895 | handle = handle_bad_irq; |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 896 | } else { |
Marc Zyngier | f86eff2 | 2014-11-15 10:49:13 +0000 | [diff] [blame] | 897 | struct irq_data *irq_data = &desc->irq_data; |
| 898 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 899 | /* |
| 900 | * With hierarchical domains we might run into a |
| 901 | * situation where the outermost chip is not yet set |
| 902 | * up, but the inner chips are there. Instead of |
| 903 | * bailing we install the handler, but obviously we |
| 904 | * cannot enable/startup the interrupt at this point. |
| 905 | */ |
| 906 | while (irq_data) { |
| 907 | if (irq_data->chip != &no_irq_chip) |
| 908 | break; |
| 909 | /* |
| 910 | * Bail out if the outer chip is not set up |
| 911 | * and the interrrupt supposed to be started |
| 912 | * right away. |
| 913 | */ |
| 914 | if (WARN_ON(is_chained)) |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 915 | return; |
Marc Zyngier | f86eff2 | 2014-11-15 10:49:13 +0000 | [diff] [blame] | 916 | /* Try the parent */ |
| 917 | irq_data = irq_data->parent_data; |
| 918 | } |
| 919 | #endif |
| 920 | if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip)) |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 921 | return; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 922 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 923 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 924 | /* Uninstall? */ |
| 925 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 926 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 927 | mask_ack_irq(desc); |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 928 | irq_state_set_disabled(desc); |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 929 | if (is_chained) |
| 930 | desc->action = NULL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 931 | desc->depth = 1; |
| 932 | } |
| 933 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 934 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 935 | |
| 936 | if (handle != handle_bad_irq && is_chained) { |
Marc Zyngier | 1984e07 | 2016-09-19 09:49:27 +0100 | [diff] [blame] | 937 | unsigned int type = irqd_get_trigger_type(&desc->irq_data); |
| 938 | |
Marc Zyngier | 1e12c4a | 2016-08-11 14:19:42 +0100 | [diff] [blame] | 939 | /* |
| 940 | * We're about to start this interrupt immediately, |
| 941 | * hence the need to set the trigger configuration. |
| 942 | * But the .set_type callback may have overridden the |
| 943 | * flow handler, ignoring that we're dealing with a |
| 944 | * chained interrupt. Reset it immediately because we |
| 945 | * do know better. |
| 946 | */ |
Marc Zyngier | 1984e07 | 2016-09-19 09:49:27 +0100 | [diff] [blame] | 947 | if (type != IRQ_TYPE_NONE) { |
| 948 | __irq_set_trigger(desc, type); |
| 949 | desc->handle_irq = handle; |
| 950 | } |
Marc Zyngier | 1e12c4a | 2016-08-11 14:19:42 +0100 | [diff] [blame] | 951 | |
Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 952 | irq_settings_set_noprobe(desc); |
| 953 | irq_settings_set_norequest(desc); |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 954 | irq_settings_set_nothread(desc); |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 955 | desc->action = &chained_action; |
Thomas Gleixner | 4cde9c6 | 2017-06-20 01:37:49 +0200 | [diff] [blame] | 956 | irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 957 | } |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | void |
| 961 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 962 | const char *name) |
| 963 | { |
| 964 | unsigned long flags; |
| 965 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
| 966 | |
| 967 | if (!desc) |
| 968 | return; |
| 969 | |
| 970 | __irq_do_set_handler(desc, handle, is_chained, name); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 971 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 972 | } |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 973 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 974 | |
| 975 | void |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 976 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, |
| 977 | void *data) |
| 978 | { |
| 979 | unsigned long flags; |
| 980 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
| 981 | |
| 982 | if (!desc) |
| 983 | return; |
| 984 | |
Jiang Liu | af7080e | 2015-06-01 16:05:21 +0800 | [diff] [blame] | 985 | desc->irq_common_data.handler_data = data; |
Thomas Gleixner | 2c4569ca | 2017-05-11 13:54:11 +0200 | [diff] [blame] | 986 | __irq_do_set_handler(desc, handle, 1, NULL); |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 987 | |
| 988 | irq_put_desc_busunlock(desc, flags); |
| 989 | } |
| 990 | EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data); |
| 991 | |
| 992 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 993 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 994 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 995 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 996 | irq_set_chip(irq, chip); |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 997 | __irq_set_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 998 | } |
Kuninori Morimoto | b3ae66f | 2012-07-30 22:39:06 -0700 | [diff] [blame] | 999 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1000 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 1001 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1002 | { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1003 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 1004 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1005 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 1006 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1007 | return; |
Thomas Gleixner | 04c848d | 2017-05-31 11:58:33 +0200 | [diff] [blame] | 1008 | |
| 1009 | /* |
| 1010 | * Warn when a driver sets the no autoenable flag on an already |
| 1011 | * active interrupt. |
| 1012 | */ |
| 1013 | WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN)); |
| 1014 | |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 1015 | irq_settings_clr_and_set(desc, clr, set); |
| 1016 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 1017 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 1018 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 1019 | if (irq_settings_has_no_balance_set(desc)) |
| 1020 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); |
| 1021 | if (irq_settings_is_per_cpu(desc)) |
| 1022 | irqd_set(&desc->irq_data, IRQD_PER_CPU); |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 1023 | if (irq_settings_can_move_pcntxt(desc)) |
| 1024 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); |
Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 1025 | if (irq_settings_is_level(desc)) |
| 1026 | irqd_set(&desc->irq_data, IRQD_LEVEL); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 1027 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 1028 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
| 1029 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 1030 | irq_put_desc_unlock(desc, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 1031 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 1032 | EXPORT_SYMBOL_GPL(irq_modify_status); |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 1033 | |
| 1034 | /** |
| 1035 | * irq_cpu_online - Invoke all irq_cpu_online functions. |
| 1036 | * |
| 1037 | * Iterate through all irqs and invoke the chip.irq_cpu_online() |
| 1038 | * for each. |
| 1039 | */ |
| 1040 | void irq_cpu_online(void) |
| 1041 | { |
| 1042 | struct irq_desc *desc; |
| 1043 | struct irq_chip *chip; |
| 1044 | unsigned long flags; |
| 1045 | unsigned int irq; |
| 1046 | |
| 1047 | for_each_active_irq(irq) { |
| 1048 | desc = irq_to_desc(irq); |
| 1049 | if (!desc) |
| 1050 | continue; |
| 1051 | |
| 1052 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 1053 | |
| 1054 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 1055 | if (chip && chip->irq_cpu_online && |
| 1056 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 1057 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 1058 | chip->irq_cpu_online(&desc->irq_data); |
| 1059 | |
| 1060 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 1061 | } |
| 1062 | } |
| 1063 | |
| 1064 | /** |
| 1065 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. |
| 1066 | * |
| 1067 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() |
| 1068 | * for each. |
| 1069 | */ |
| 1070 | void irq_cpu_offline(void) |
| 1071 | { |
| 1072 | struct irq_desc *desc; |
| 1073 | struct irq_chip *chip; |
| 1074 | unsigned long flags; |
| 1075 | unsigned int irq; |
| 1076 | |
| 1077 | for_each_active_irq(irq) { |
| 1078 | desc = irq_to_desc(irq); |
| 1079 | if (!desc) |
| 1080 | continue; |
| 1081 | |
| 1082 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 1083 | |
| 1084 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 1085 | if (chip && chip->irq_cpu_offline && |
| 1086 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 1087 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 1088 | chip->irq_cpu_offline(&desc->irq_data); |
| 1089 | |
| 1090 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 1091 | } |
| 1092 | } |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1093 | |
| 1094 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 1095 | /** |
Stefan Agner | 3cfeffc | 2015-05-16 11:44:14 +0200 | [diff] [blame] | 1096 | * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if |
| 1097 | * NULL) |
| 1098 | * @data: Pointer to interrupt specific data |
| 1099 | */ |
| 1100 | void irq_chip_enable_parent(struct irq_data *data) |
| 1101 | { |
| 1102 | data = data->parent_data; |
| 1103 | if (data->chip->irq_enable) |
| 1104 | data->chip->irq_enable(data); |
| 1105 | else |
| 1106 | data->chip->irq_unmask(data); |
| 1107 | } |
| 1108 | |
| 1109 | /** |
| 1110 | * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if |
| 1111 | * NULL) |
| 1112 | * @data: Pointer to interrupt specific data |
| 1113 | */ |
| 1114 | void irq_chip_disable_parent(struct irq_data *data) |
| 1115 | { |
| 1116 | data = data->parent_data; |
| 1117 | if (data->chip->irq_disable) |
| 1118 | data->chip->irq_disable(data); |
| 1119 | else |
| 1120 | data->chip->irq_mask(data); |
| 1121 | } |
| 1122 | |
| 1123 | /** |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1124 | * irq_chip_ack_parent - Acknowledge the parent interrupt |
| 1125 | * @data: Pointer to interrupt specific data |
| 1126 | */ |
| 1127 | void irq_chip_ack_parent(struct irq_data *data) |
| 1128 | { |
| 1129 | data = data->parent_data; |
| 1130 | data->chip->irq_ack(data); |
| 1131 | } |
Jake Oshins | a4289dc | 2015-12-10 17:52:59 +0000 | [diff] [blame] | 1132 | EXPORT_SYMBOL_GPL(irq_chip_ack_parent); |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1133 | |
| 1134 | /** |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1135 | * irq_chip_mask_parent - Mask the parent interrupt |
| 1136 | * @data: Pointer to interrupt specific data |
| 1137 | */ |
| 1138 | void irq_chip_mask_parent(struct irq_data *data) |
| 1139 | { |
| 1140 | data = data->parent_data; |
| 1141 | data->chip->irq_mask(data); |
| 1142 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1143 | EXPORT_SYMBOL_GPL(irq_chip_mask_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1144 | |
| 1145 | /** |
| 1146 | * irq_chip_unmask_parent - Unmask the parent interrupt |
| 1147 | * @data: Pointer to interrupt specific data |
| 1148 | */ |
| 1149 | void irq_chip_unmask_parent(struct irq_data *data) |
| 1150 | { |
| 1151 | data = data->parent_data; |
| 1152 | data->chip->irq_unmask(data); |
| 1153 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1154 | EXPORT_SYMBOL_GPL(irq_chip_unmask_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1155 | |
| 1156 | /** |
| 1157 | * irq_chip_eoi_parent - Invoke EOI on the parent interrupt |
| 1158 | * @data: Pointer to interrupt specific data |
| 1159 | */ |
| 1160 | void irq_chip_eoi_parent(struct irq_data *data) |
| 1161 | { |
| 1162 | data = data->parent_data; |
| 1163 | data->chip->irq_eoi(data); |
| 1164 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1165 | EXPORT_SYMBOL_GPL(irq_chip_eoi_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1166 | |
| 1167 | /** |
| 1168 | * irq_chip_set_affinity_parent - Set affinity on the parent interrupt |
| 1169 | * @data: Pointer to interrupt specific data |
| 1170 | * @dest: The affinity mask to set |
| 1171 | * @force: Flag to enforce setting (disable online checks) |
| 1172 | * |
| 1173 | * Conditinal, as the underlying parent chip might not implement it. |
| 1174 | */ |
| 1175 | int irq_chip_set_affinity_parent(struct irq_data *data, |
| 1176 | const struct cpumask *dest, bool force) |
| 1177 | { |
| 1178 | data = data->parent_data; |
| 1179 | if (data->chip->irq_set_affinity) |
| 1180 | return data->chip->irq_set_affinity(data, dest, force); |
| 1181 | |
| 1182 | return -ENOSYS; |
| 1183 | } |
| 1184 | |
| 1185 | /** |
Grygorii Strashko | b7560de | 2015-08-14 15:20:26 +0300 | [diff] [blame] | 1186 | * irq_chip_set_type_parent - Set IRQ type on the parent interrupt |
| 1187 | * @data: Pointer to interrupt specific data |
| 1188 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
| 1189 | * |
| 1190 | * Conditional, as the underlying parent chip might not implement it. |
| 1191 | */ |
| 1192 | int irq_chip_set_type_parent(struct irq_data *data, unsigned int type) |
| 1193 | { |
| 1194 | data = data->parent_data; |
| 1195 | |
| 1196 | if (data->chip->irq_set_type) |
| 1197 | return data->chip->irq_set_type(data, type); |
| 1198 | |
| 1199 | return -ENOSYS; |
| 1200 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1201 | EXPORT_SYMBOL_GPL(irq_chip_set_type_parent); |
Grygorii Strashko | b7560de | 2015-08-14 15:20:26 +0300 | [diff] [blame] | 1202 | |
| 1203 | /** |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1204 | * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware |
| 1205 | * @data: Pointer to interrupt specific data |
| 1206 | * |
| 1207 | * Iterate through the domain hierarchy of the interrupt and check |
| 1208 | * whether a hw retrigger function exists. If yes, invoke it. |
| 1209 | */ |
| 1210 | int irq_chip_retrigger_hierarchy(struct irq_data *data) |
| 1211 | { |
| 1212 | for (data = data->parent_data; data; data = data->parent_data) |
| 1213 | if (data->chip && data->chip->irq_retrigger) |
| 1214 | return data->chip->irq_retrigger(data); |
| 1215 | |
Grygorii Strashko | 6d4affe | 2015-08-14 15:20:25 +0300 | [diff] [blame] | 1216 | return 0; |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1217 | } |
Marc Zyngier | 08b55e2 | 2015-03-11 15:43:43 +0000 | [diff] [blame] | 1218 | |
| 1219 | /** |
Jiang Liu | 0a4377d | 2015-05-19 17:07:14 +0800 | [diff] [blame] | 1220 | * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt |
| 1221 | * @data: Pointer to interrupt specific data |
Masanari Iida | 8505a81 | 2015-07-29 19:09:36 +0900 | [diff] [blame] | 1222 | * @vcpu_info: The vcpu affinity information |
Jiang Liu | 0a4377d | 2015-05-19 17:07:14 +0800 | [diff] [blame] | 1223 | */ |
| 1224 | int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info) |
| 1225 | { |
| 1226 | data = data->parent_data; |
| 1227 | if (data->chip->irq_set_vcpu_affinity) |
| 1228 | return data->chip->irq_set_vcpu_affinity(data, vcpu_info); |
| 1229 | |
| 1230 | return -ENOSYS; |
| 1231 | } |
| 1232 | |
| 1233 | /** |
Marc Zyngier | 08b55e2 | 2015-03-11 15:43:43 +0000 | [diff] [blame] | 1234 | * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt |
| 1235 | * @data: Pointer to interrupt specific data |
| 1236 | * @on: Whether to set or reset the wake-up capability of this irq |
| 1237 | * |
| 1238 | * Conditional, as the underlying parent chip might not implement it. |
| 1239 | */ |
| 1240 | int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on) |
| 1241 | { |
| 1242 | data = data->parent_data; |
| 1243 | if (data->chip->irq_set_wake) |
| 1244 | return data->chip->irq_set_wake(data, on); |
| 1245 | |
| 1246 | return -ENOSYS; |
| 1247 | } |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1248 | #endif |
Jiang Liu | 515085e | 2014-11-06 22:20:17 +0800 | [diff] [blame] | 1249 | |
| 1250 | /** |
| 1251 | * irq_chip_compose_msi_msg - Componse msi message for a irq chip |
| 1252 | * @data: Pointer to interrupt specific data |
| 1253 | * @msg: Pointer to the MSI message |
| 1254 | * |
| 1255 | * For hierarchical domains we find the first chip in the hierarchy |
| 1256 | * which implements the irq_compose_msi_msg callback. For non |
| 1257 | * hierarchical we use the top level chip. |
| 1258 | */ |
| 1259 | int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
| 1260 | { |
| 1261 | struct irq_data *pos = NULL; |
| 1262 | |
| 1263 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 1264 | for (; data; data = data->parent_data) |
| 1265 | #endif |
| 1266 | if (data->chip && data->chip->irq_compose_msi_msg) |
| 1267 | pos = data; |
| 1268 | if (!pos) |
| 1269 | return -ENOSYS; |
| 1270 | |
| 1271 | pos->chip->irq_compose_msi_msg(pos, msg); |
| 1272 | |
| 1273 | return 0; |
| 1274 | } |
Jon Hunter | be45beb | 2016-06-07 16:12:29 +0100 | [diff] [blame] | 1275 | |
| 1276 | /** |
| 1277 | * irq_chip_pm_get - Enable power for an IRQ chip |
| 1278 | * @data: Pointer to interrupt specific data |
| 1279 | * |
| 1280 | * Enable the power to the IRQ chip referenced by the interrupt data |
| 1281 | * structure. |
| 1282 | */ |
| 1283 | int irq_chip_pm_get(struct irq_data *data) |
| 1284 | { |
| 1285 | int retval; |
| 1286 | |
| 1287 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) { |
| 1288 | retval = pm_runtime_get_sync(data->chip->parent_device); |
| 1289 | if (retval < 0) { |
| 1290 | pm_runtime_put_noidle(data->chip->parent_device); |
| 1291 | return retval; |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | return 0; |
| 1296 | } |
| 1297 | |
| 1298 | /** |
| 1299 | * irq_chip_pm_put - Disable power for an IRQ chip |
| 1300 | * @data: Pointer to interrupt specific data |
| 1301 | * |
| 1302 | * Disable the power to the IRQ chip referenced by the interrupt data |
| 1303 | * structure, belongs. Note that power will only be disabled, once this |
| 1304 | * function has been called for all IRQs that have called irq_chip_pm_get(). |
| 1305 | */ |
| 1306 | int irq_chip_pm_put(struct irq_data *data) |
| 1307 | { |
| 1308 | int retval = 0; |
| 1309 | |
| 1310 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) |
| 1311 | retval = pm_runtime_put(data->chip->parent_device); |
| 1312 | |
| 1313 | return (retval < 0) ? retval : 0; |
| 1314 | } |