Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 22 | * irq_set_chip - set the irq chip for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 23 | * @irq: irq number |
| 24 | * @chip: pointer to irq chip description structure |
| 25 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 27 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 28 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 29 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 31 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 | |
| 34 | if (!chip) |
| 35 | chip = &no_irq_chip; |
| 36 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 37 | irq_chip_set_defaults(chip); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 38 | desc->irq_data.chip = chip; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 39 | irq_put_desc_unlock(desc, flags); |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 40 | /* |
| 41 | * For !CONFIG_SPARSE_IRQ make the irq show up in |
| 42 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is |
| 43 | * already marked, and this call is harmless. |
| 44 | */ |
| 45 | irq_reserve_irq(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 46 | return 0; |
| 47 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 48 | EXPORT_SYMBOL(irq_set_chip); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 49 | |
| 50 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 51 | * irq_set_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 52 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 53 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 54 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 55 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 56 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 57 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 58 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
| 59 | int ret = 0; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 60 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 61 | if (!desc) |
| 62 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 63 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 64 | type &= IRQ_TYPE_SENSE_MASK; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 65 | if (type != IRQ_TYPE_NONE) |
| 66 | ret = __irq_set_trigger(desc, irq, type); |
| 67 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 68 | return ret; |
| 69 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 70 | EXPORT_SYMBOL(irq_set_irq_type); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 | |
| 72 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 73 | * irq_set_handler_data - set irq handler data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 74 | * @irq: Interrupt number |
| 75 | * @data: Pointer to interrupt specific data |
| 76 | * |
| 77 | * Set the hardware irq controller data for an irq |
| 78 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 79 | int irq_set_handler_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 80 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 81 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 82 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 83 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 84 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 86 | desc->irq_data.handler_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 87 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 88 | return 0; |
| 89 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 90 | EXPORT_SYMBOL(irq_set_handler_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 91 | |
| 92 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 93 | * irq_set_msi_desc - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 94 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 95 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 96 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 97 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 98 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 99 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 100 | { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 101 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 102 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 103 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 104 | if (!desc) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 105 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 106 | desc->irq_data.msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 107 | if (entry) |
| 108 | entry->irq = irq; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 109 | irq_put_desc_unlock(desc, flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 114 | * irq_set_chip_data - set irq chip data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 115 | * @irq: Interrupt number |
| 116 | * @data: Pointer to chip specific data |
| 117 | * |
| 118 | * Set the hardware irq chip data for an irq |
| 119 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 120 | int irq_set_chip_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 121 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 122 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 123 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 124 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 125 | if (!desc) |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 126 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 127 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 128 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 129 | return 0; |
| 130 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 131 | EXPORT_SYMBOL(irq_set_chip_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 132 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 133 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 134 | { |
| 135 | struct irq_desc *desc = irq_to_desc(irq); |
| 136 | |
| 137 | return desc ? &desc->irq_data : NULL; |
| 138 | } |
| 139 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 140 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 141 | static void irq_state_clr_disabled(struct irq_desc *desc) |
| 142 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 143 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 144 | irq_compat_clr_disabled(desc); |
| 145 | } |
| 146 | |
| 147 | static void irq_state_set_disabled(struct irq_desc *desc) |
| 148 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 149 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 150 | irq_compat_set_disabled(desc); |
| 151 | } |
| 152 | |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 153 | static void irq_state_clr_masked(struct irq_desc *desc) |
| 154 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 155 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 156 | irq_compat_clr_masked(desc); |
| 157 | } |
| 158 | |
| 159 | static void irq_state_set_masked(struct irq_desc *desc) |
| 160 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 161 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 162 | irq_compat_set_masked(desc); |
| 163 | } |
| 164 | |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 165 | int irq_startup(struct irq_desc *desc) |
| 166 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 167 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 168 | desc->depth = 0; |
| 169 | |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 170 | if (desc->irq_data.chip->irq_startup) { |
| 171 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 172 | irq_state_clr_masked(desc); |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 173 | return ret; |
| 174 | } |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 175 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 176 | irq_enable(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | void irq_shutdown(struct irq_desc *desc) |
| 181 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 182 | irq_state_set_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 183 | desc->depth = 1; |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 184 | if (desc->irq_data.chip->irq_shutdown) |
| 185 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); |
| 186 | if (desc->irq_data.chip->irq_disable) |
| 187 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 188 | else |
| 189 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 190 | irq_state_set_masked(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 193 | void irq_enable(struct irq_desc *desc) |
| 194 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 195 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 196 | if (desc->irq_data.chip->irq_enable) |
| 197 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 198 | else |
| 199 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 200 | irq_state_clr_masked(desc); |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | void irq_disable(struct irq_desc *desc) |
| 204 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 205 | irq_state_set_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 206 | if (desc->irq_data.chip->irq_disable) { |
| 207 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 208 | irq_state_set_masked(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 209 | } |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 210 | } |
| 211 | |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 212 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 213 | /* Temporary migration helpers */ |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 214 | static void compat_irq_mask(struct irq_data *data) |
| 215 | { |
| 216 | data->chip->mask(data->irq); |
| 217 | } |
| 218 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 219 | static void compat_irq_unmask(struct irq_data *data) |
| 220 | { |
| 221 | data->chip->unmask(data->irq); |
| 222 | } |
| 223 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 224 | static void compat_irq_ack(struct irq_data *data) |
| 225 | { |
| 226 | data->chip->ack(data->irq); |
| 227 | } |
| 228 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 229 | static void compat_irq_mask_ack(struct irq_data *data) |
| 230 | { |
| 231 | data->chip->mask_ack(data->irq); |
| 232 | } |
| 233 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 234 | static void compat_irq_eoi(struct irq_data *data) |
| 235 | { |
| 236 | data->chip->eoi(data->irq); |
| 237 | } |
| 238 | |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 239 | static void compat_irq_enable(struct irq_data *data) |
| 240 | { |
| 241 | data->chip->enable(data->irq); |
| 242 | } |
| 243 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 244 | static void compat_irq_disable(struct irq_data *data) |
| 245 | { |
| 246 | data->chip->disable(data->irq); |
| 247 | } |
| 248 | |
| 249 | static void compat_irq_shutdown(struct irq_data *data) |
| 250 | { |
| 251 | data->chip->shutdown(data->irq); |
| 252 | } |
| 253 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 254 | static unsigned int compat_irq_startup(struct irq_data *data) |
| 255 | { |
| 256 | return data->chip->startup(data->irq); |
| 257 | } |
| 258 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 259 | static int compat_irq_set_affinity(struct irq_data *data, |
| 260 | const struct cpumask *dest, bool force) |
| 261 | { |
| 262 | return data->chip->set_affinity(data->irq, dest); |
| 263 | } |
| 264 | |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 265 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
| 266 | { |
| 267 | return data->chip->set_type(data->irq, type); |
| 268 | } |
| 269 | |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 270 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
| 271 | { |
| 272 | return data->chip->set_wake(data->irq, on); |
| 273 | } |
| 274 | |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 275 | static int compat_irq_retrigger(struct irq_data *data) |
| 276 | { |
| 277 | return data->chip->retrigger(data->irq); |
| 278 | } |
| 279 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 280 | static void compat_bus_lock(struct irq_data *data) |
| 281 | { |
| 282 | data->chip->bus_lock(data->irq); |
| 283 | } |
| 284 | |
| 285 | static void compat_bus_sync_unlock(struct irq_data *data) |
| 286 | { |
| 287 | data->chip->bus_sync_unlock(data->irq); |
| 288 | } |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 289 | #endif |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 290 | |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 291 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 292 | * Fixup enable/disable function pointers |
| 293 | */ |
| 294 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 295 | { |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 296 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 297 | if (chip->enable) |
| 298 | chip->irq_enable = compat_irq_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 299 | if (chip->disable) |
| 300 | chip->irq_disable = compat_irq_disable; |
| 301 | if (chip->shutdown) |
| 302 | chip->irq_shutdown = compat_irq_shutdown; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 303 | if (chip->startup) |
| 304 | chip->irq_startup = compat_irq_startup; |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 305 | if (!chip->end) |
| 306 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 307 | if (chip->bus_lock) |
| 308 | chip->irq_bus_lock = compat_bus_lock; |
| 309 | if (chip->bus_sync_unlock) |
| 310 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 311 | if (chip->mask) |
| 312 | chip->irq_mask = compat_irq_mask; |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 313 | if (chip->unmask) |
| 314 | chip->irq_unmask = compat_irq_unmask; |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 315 | if (chip->ack) |
| 316 | chip->irq_ack = compat_irq_ack; |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 317 | if (chip->mask_ack) |
| 318 | chip->irq_mask_ack = compat_irq_mask_ack; |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 319 | if (chip->eoi) |
| 320 | chip->irq_eoi = compat_irq_eoi; |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 321 | if (chip->set_affinity) |
| 322 | chip->irq_set_affinity = compat_irq_set_affinity; |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 323 | if (chip->set_type) |
| 324 | chip->irq_set_type = compat_irq_set_type; |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 325 | if (chip->set_wake) |
| 326 | chip->irq_set_wake = compat_irq_set_wake; |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 327 | if (chip->retrigger) |
| 328 | chip->irq_retrigger = compat_irq_retrigger; |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 329 | #endif |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 330 | } |
| 331 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 332 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 333 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 334 | if (desc->irq_data.chip->irq_mask_ack) |
| 335 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 336 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 337 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 338 | if (desc->irq_data.chip->irq_ack) |
| 339 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 340 | } |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 341 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 342 | } |
| 343 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 344 | void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 345 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 346 | if (desc->irq_data.chip->irq_mask) { |
| 347 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 348 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 349 | } |
| 350 | } |
| 351 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 352 | void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 353 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 354 | if (desc->irq_data.chip->irq_unmask) { |
| 355 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 356 | irq_state_clr_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 357 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 358 | } |
| 359 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 360 | /* |
| 361 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 362 | * @irq: the interrupt number |
| 363 | * |
| 364 | * Handle interrupts which are nested into a threaded interrupt |
| 365 | * handler. The handler function is called inside the calling |
| 366 | * threads context. |
| 367 | */ |
| 368 | void handle_nested_irq(unsigned int irq) |
| 369 | { |
| 370 | struct irq_desc *desc = irq_to_desc(irq); |
| 371 | struct irqaction *action; |
| 372 | irqreturn_t action_ret; |
| 373 | |
| 374 | might_sleep(); |
| 375 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 376 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 377 | |
| 378 | kstat_incr_irqs_this_cpu(irq, desc); |
| 379 | |
| 380 | action = desc->action; |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 381 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 382 | goto out_unlock; |
| 383 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 384 | irq_compat_set_progress(desc); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 385 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 386 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 387 | |
| 388 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 389 | if (!noirqdebug) |
| 390 | note_interrupt(irq, desc, action_ret); |
| 391 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 392 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 393 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 394 | irq_compat_clr_progress(desc); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 395 | |
| 396 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 397 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 398 | } |
| 399 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 400 | |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 401 | static bool irq_check_poll(struct irq_desc *desc) |
| 402 | { |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 403 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 404 | return false; |
| 405 | return irq_wait_for_poll(desc); |
| 406 | } |
| 407 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 408 | /** |
| 409 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 410 | * @irq: the interrupt number |
| 411 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 412 | * |
| 413 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 414 | * handler or come from hardware, where no interrupt hardware control |
| 415 | * is necessary. |
| 416 | * |
| 417 | * Note: The caller is expected to handle the ack, clear, mask and |
| 418 | * unmask issues if necessary. |
| 419 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 420 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 421 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 422 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 423 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 424 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 425 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 426 | if (!irq_check_poll(desc)) |
| 427 | goto out_unlock; |
| 428 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 429 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 430 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 431 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 432 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 433 | goto out_unlock; |
| 434 | |
Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 435 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 436 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 437 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 438 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | /** |
| 442 | * handle_level_irq - Level type irq handler |
| 443 | * @irq: the interrupt number |
| 444 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 445 | * |
| 446 | * Level type interrupts are active as long as the hardware line has |
| 447 | * the active level. This may require to mask the interrupt and unmask |
| 448 | * it after the associated handler has acknowledged the device, so the |
| 449 | * interrupt line is back to inactive. |
| 450 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 451 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 452 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 453 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 454 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 455 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 456 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 457 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 458 | if (!irq_check_poll(desc)) |
| 459 | goto out_unlock; |
| 460 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 461 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 462 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 463 | |
| 464 | /* |
| 465 | * If its disabled or no action available |
| 466 | * keep it masked and get out of here |
| 467 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 468 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 469 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 470 | |
Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 471 | handle_irq_event(desc); |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 472 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 473 | if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT)) |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 474 | unmask_irq(desc); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 475 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 476 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 477 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 478 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 479 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 480 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 481 | static inline void preflow_handler(struct irq_desc *desc) |
| 482 | { |
| 483 | if (desc->preflow_handler) |
| 484 | desc->preflow_handler(&desc->irq_data); |
| 485 | } |
| 486 | #else |
| 487 | static inline void preflow_handler(struct irq_desc *desc) { } |
| 488 | #endif |
| 489 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 490 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 491 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 492 | * @irq: the interrupt number |
| 493 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 494 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 495 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 496 | * call when the interrupt has been serviced. This enables support |
| 497 | * for modern forms of interrupt handlers, which handle the flow |
| 498 | * details in hardware, transparently. |
| 499 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 500 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 501 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 502 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 503 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 504 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 505 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 506 | if (!irq_check_poll(desc)) |
| 507 | goto out; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 508 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 509 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 510 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 511 | |
| 512 | /* |
| 513 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 514 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 515 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 516 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 517 | irq_compat_set_pending(desc); |
| 518 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 519 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 520 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 521 | } |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 522 | |
| 523 | if (desc->istate & IRQS_ONESHOT) |
| 524 | mask_irq(desc); |
| 525 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 526 | preflow_handler(desc); |
Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 527 | handle_irq_event(desc); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 528 | |
| 529 | out_eoi: |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 530 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 531 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 532 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 533 | return; |
| 534 | out: |
| 535 | if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
| 536 | goto out_eoi; |
| 537 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 538 | } |
| 539 | |
| 540 | /** |
| 541 | * handle_edge_irq - edge type IRQ handler |
| 542 | * @irq: the interrupt number |
| 543 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | * |
| 545 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 546 | * signal. The occurence is latched into the irq controller hardware |
| 547 | * and must be acked in order to be reenabled. After the ack another |
| 548 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 549 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 550 | * might be necessary to disable (mask) the interrupt depending on the |
| 551 | * controller hardware. This requires to reenable the interrupt inside |
| 552 | * of the loop which handles the interrupts which have arrived while |
| 553 | * the handler was running. If all pending interrupts are handled, the |
| 554 | * loop is left. |
| 555 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 556 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 557 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 558 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 559 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 560 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 561 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 562 | /* |
| 563 | * If we're currently running this IRQ, or its disabled, |
| 564 | * we shouldn't process the IRQ. Mark it pending, handle |
| 565 | * the necessary masking and go out |
| 566 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 567 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || |
| 568 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 569 | if (!irq_check_poll(desc)) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 570 | irq_compat_set_pending(desc); |
| 571 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 572 | mask_ack_irq(desc); |
| 573 | goto out_unlock; |
| 574 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 575 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 576 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 577 | |
| 578 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 579 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 580 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 581 | do { |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 582 | if (unlikely(!desc->action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 583 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | goto out_unlock; |
| 585 | } |
| 586 | |
| 587 | /* |
| 588 | * When another irq arrived while we were handling |
| 589 | * one, we could have masked the irq. |
| 590 | * Renable it, if it was not disabled in meantime. |
| 591 | */ |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 592 | if (unlikely(desc->istate & IRQS_PENDING)) { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 593 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 594 | irqd_irq_masked(&desc->irq_data)) |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 595 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 596 | } |
| 597 | |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 598 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 599 | |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 600 | } while ((desc->istate & IRQS_PENDING) && |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 601 | !irqd_irq_disabled(&desc->irq_data)); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 602 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 604 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 605 | } |
| 606 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 607 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 608 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 609 | * @irq: the interrupt number |
| 610 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 611 | * |
| 612 | * Per CPU interrupts on SMP machines without locking requirements |
| 613 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 614 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 615 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 616 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 617 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 618 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 619 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 620 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 621 | if (chip->irq_ack) |
| 622 | chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 623 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 624 | handle_irq_event_percpu(desc, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 625 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 626 | if (chip->irq_eoi) |
| 627 | chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 630 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 631 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 632 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 633 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 634 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 635 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 636 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 637 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 638 | return; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 639 | |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 640 | if (!handle) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 641 | handle = handle_bad_irq; |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 642 | } else { |
| 643 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 644 | goto out; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 645 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 646 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 647 | /* Uninstall? */ |
| 648 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 649 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 650 | mask_ack_irq(desc); |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 651 | irq_state_set_disabled(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 652 | desc->depth = 1; |
| 653 | } |
| 654 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 655 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 656 | |
| 657 | if (handle != handle_bad_irq && is_chained) { |
Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 658 | irq_settings_set_noprobe(desc); |
| 659 | irq_settings_set_norequest(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 660 | irq_startup(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 661 | } |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 662 | out: |
| 663 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 664 | } |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 665 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 666 | |
| 667 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 668 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 669 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 670 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 671 | irq_set_chip(irq, chip); |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 672 | __irq_set_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 673 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 674 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 675 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 676 | { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 677 | unsigned long flags; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 678 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 679 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 680 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 681 | return; |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 682 | irq_settings_clr_and_set(desc, clr, set); |
| 683 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 684 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 685 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 686 | if (irq_settings_has_no_balance_set(desc)) |
| 687 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); |
| 688 | if (irq_settings_is_per_cpu(desc)) |
| 689 | irqd_set(&desc->irq_data, IRQD_PER_CPU); |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 690 | if (irq_settings_can_move_pcntxt(desc)) |
| 691 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 692 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 693 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
| 694 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 695 | irq_put_desc_unlock(desc, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 696 | } |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 697 | |
| 698 | /** |
| 699 | * irq_cpu_online - Invoke all irq_cpu_online functions. |
| 700 | * |
| 701 | * Iterate through all irqs and invoke the chip.irq_cpu_online() |
| 702 | * for each. |
| 703 | */ |
| 704 | void irq_cpu_online(void) |
| 705 | { |
| 706 | struct irq_desc *desc; |
| 707 | struct irq_chip *chip; |
| 708 | unsigned long flags; |
| 709 | unsigned int irq; |
| 710 | |
| 711 | for_each_active_irq(irq) { |
| 712 | desc = irq_to_desc(irq); |
| 713 | if (!desc) |
| 714 | continue; |
| 715 | |
| 716 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 717 | |
| 718 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 719 | if (chip && chip->irq_cpu_online && |
| 720 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 721 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 722 | chip->irq_cpu_online(&desc->irq_data); |
| 723 | |
| 724 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 725 | } |
| 726 | } |
| 727 | |
| 728 | /** |
| 729 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. |
| 730 | * |
| 731 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() |
| 732 | * for each. |
| 733 | */ |
| 734 | void irq_cpu_offline(void) |
| 735 | { |
| 736 | struct irq_desc *desc; |
| 737 | struct irq_chip *chip; |
| 738 | unsigned long flags; |
| 739 | unsigned int irq; |
| 740 | |
| 741 | for_each_active_irq(irq) { |
| 742 | desc = irq_to_desc(irq); |
| 743 | if (!desc) |
| 744 | continue; |
| 745 | |
| 746 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 747 | |
| 748 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 749 | if (chip && chip->irq_cpu_offline && |
| 750 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame^] | 751 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 752 | chip->irq_cpu_offline(&desc->irq_data); |
| 753 | |
| 754 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 755 | } |
| 756 | } |