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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Robert Nelson2876cc42016-12-27 11:58:34 -06002/*
Alexander A. Klimov75f66812020-07-08 11:34:51 +02003 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Robert Nelson2876cc42016-12-27 11:58:34 -06004 */
5
6#include <dt-bindings/display/tda998x.h>
Hans Verkuil605cdd22018-09-24 13:01:46 +02007#include <dt-bindings/interrupt-controller/irq.h>
Robert Nelson2876cc42016-12-27 11:58:34 -06008
9&ldo3_reg {
10 regulator-min-microvolt = <1800000>;
11 regulator-max-microvolt = <1800000>;
12 regulator-always-on;
13};
14
15&mmc1 {
16 vmmc-supply = <&vmmcsd_fixed>;
17};
18
19&mmc2 {
20 vmmc-supply = <&vmmcsd_fixed>;
21 pinctrl-names = "default";
22 pinctrl-0 = <&emmc_pins>;
23 bus-width = <8>;
24 status = "okay";
25};
26
27&am33xx_pinmux {
28 nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
29 pinctrl-single,pins = <
Christina Quast399c6b92019-04-08 10:01:52 -070030 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
31 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
32 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
33 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
34 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
35 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
36 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
37 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
38 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
39 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
40 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
41 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
42 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
43 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
44 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
45 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
46 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
47 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
Robert Nelson2876cc42016-12-27 11:58:34 -060051 >;
52 };
53
54 nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
55 pinctrl-single,pins = <
Christina Quast399c6b92019-04-08 10:01:52 -070056 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
Robert Nelson2876cc42016-12-27 11:58:34 -060057 >;
58 };
59
60 mcasp0_pins: mcasp0_pins {
61 pinctrl-single,pins = <
Christina Quast399c6b92019-04-08 10:01:52 -070062 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
63 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
64 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
65 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
66 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
Robert Nelson2876cc42016-12-27 11:58:34 -060067 >;
68 };
69};
70
71&lcdc {
72 status = "okay";
73
74 /* If you want to get 24 bit RGB and 16 BGR mode instead of
75 * current 16 bit RGB and 24 BGR modes, set the propety
76 * below to "crossed" and uncomment the video-ports -property
77 * in tda19988 node.
78 */
79 blue-and-red-wiring = "straight";
80
81 port {
82 lcdc_0: endpoint@0 {
83 remote-endpoint = <&hdmi_0>;
84 };
85 };
86};
87
88&i2c0 {
Rob Herringcc893872018-09-13 13:12:25 -050089 tda19988: tda19988@70 {
Robert Nelson2876cc42016-12-27 11:58:34 -060090 compatible = "nxp,tda998x";
91 reg = <0x70>;
Hans Verkuil605cdd22018-09-24 13:01:46 +020092 nxp,calib-gpios = <&gpio1 25 0>;
93 interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
Robert Nelson2876cc42016-12-27 11:58:34 -060094
95 pinctrl-names = "default", "off";
96 pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
97 pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
98
99 /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
100 /* video-ports = <0x234501>; */
101
102 #sound-dai-cells = <0>;
103 audio-ports = < TDA998x_I2S 0x03>;
104
105 ports {
106 port@0 {
107 hdmi_0: endpoint@0 {
108 remote-endpoint = <&lcdc_0>;
109 };
110 };
111 };
112 };
113};
114
115&rtc {
116 system-power-controller;
117};
118
119&mcasp0 {
120 #sound-dai-cells = <0>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&mcasp0_pins>;
123 status = "okay";
124 op-mode = <0>; /* MCASP_IIS_MODE */
125 tdm-slots = <2>;
126 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
127 0 0 1 0
128 >;
129 tx-num-evt = <32>;
130 rx-num-evt = <32>;
131};
132
133/ {
Matwey V. Kornilov5abd45e2020-01-06 16:09:08 +0300134 memory@80000000 {
135 device_type = "memory";
136 reg = <0x80000000 0x20000000>; /* 512 MB */
137 };
138
Robert Nelson2876cc42016-12-27 11:58:34 -0600139 clk_mcasp0_fixed: clk_mcasp0_fixed {
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <24576000>;
143 };
144
145 clk_mcasp0: clk_mcasp0 {
146 #clock-cells = <0>;
147 compatible = "gpio-gate-clock";
148 clocks = <&clk_mcasp0_fixed>;
149 enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
150 };
151
152 sound {
153 compatible = "simple-audio-card";
154 simple-audio-card,name = "TI BeagleBone Black";
155 simple-audio-card,format = "i2s";
156 simple-audio-card,bitclock-master = <&dailink0_master>;
157 simple-audio-card,frame-master = <&dailink0_master>;
158
159 dailink0_master: simple-audio-card,cpu {
160 sound-dai = <&mcasp0>;
161 clocks = <&clk_mcasp0>;
162 };
163
164 simple-audio-card,codec {
165 sound-dai = <&tda19988>;
166 };
167 };
168};