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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Arnd Bergmannb9d7c5d2013-03-05 12:04:37 +01002/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * S3C2410 Internal RTC register definition
Linus Torvalds1da177e2005-04-16 15:20:36 -07007*/
8
9#ifndef __ASM_ARCH_REGS_RTC_H
10#define __ASM_ARCH_REGS_RTC_H __FILE__
11
Ben Dooks9a654512006-08-27 01:23:22 -070012#define S3C2410_RTCREG(x) (x)
Atul Dahiya002d31e2010-07-20 16:02:51 +053013#define S3C2410_INTP S3C2410_RTCREG(0x30)
14#define S3C2410_INTP_ALM (1 << 1)
15#define S3C2410_INTP_TIC (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
Heiko Stuebnera51da042011-12-24 10:52:10 +090017#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
18#define S3C2410_RTCCON_RTCEN (1 << 0)
19#define S3C2410_RTCCON_CNTSEL (1 << 2)
20#define S3C2410_RTCCON_CLKRST (1 << 3)
Heiko Stuebner25c1a242011-12-24 10:52:19 +090021#define S3C2443_RTCCON_TICSEL (1 << 4)
Heiko Stuebnera51da042011-12-24 10:52:10 +090022#define S3C64XX_RTCCON_TICEN (1 << 8)
Maurus Cuelenaere9f4123b2010-05-24 14:33:43 -070023
Heiko Stuebnera51da042011-12-24 10:52:10 +090024#define S3C2410_TICNT S3C2410_RTCREG(0x44)
25#define S3C2410_TICNT_ENABLE (1 << 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Heiko Stuebner25c1a242011-12-24 10:52:19 +090027/* S3C2443: tick count is 15 bit wide
28 * TICNT[6:0] contains upper 7 bits
29 * TICNT1[7:0] contains lower 8 bits
30 */
31#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8)
32#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C)
33#define S3C2443_TICNT1_PART(x) (x & 0xff)
34
35/* S3C2416: tick count is 32 bit wide
36 * TICNT[6:0] contains bits [14:8]
37 * TICNT1[7:0] contains lower 8 bits
38 * TICNT2[16:0] contains upper 17 bits
39 */
40#define S3C2416_TICNT2 S3C2410_RTCREG(0x48)
41#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15)
42
Heiko Stuebnera51da042011-12-24 10:52:10 +090043#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
44#define S3C2410_RTCALM_ALMEN (1 << 6)
45#define S3C2410_RTCALM_YEAREN (1 << 5)
46#define S3C2410_RTCALM_MONEN (1 << 4)
47#define S3C2410_RTCALM_DAYEN (1 << 3)
48#define S3C2410_RTCALM_HOUREN (1 << 2)
49#define S3C2410_RTCALM_MINEN (1 << 1)
50#define S3C2410_RTCALM_SECEN (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Heiko Stuebnera51da042011-12-24 10:52:10 +090052#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
53#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
54#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Heiko Stuebnera51da042011-12-24 10:52:10 +090056#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
57#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
58#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Heiko Stuebnera51da042011-12-24 10:52:10 +090060#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
61#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
62#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
63#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
64#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
65#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
67#endif /* __ASM_ARCH_REGS_RTC_H */