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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 5c40d493e2e63d2979610aed75df7e3744b87921 / . / arch / mips / boot / dts / brcm / bcm7435.dtsi
blob: cce752b270553e29b00b2185e61e4b2ad2ca3283 [file] [log] [blame]
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7435";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <163125000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips5200";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips5200";
20 device_type = "cpu";
21 reg = <1>;
22 };
23
24 cpu@2 {
25 compatible = "brcm,bmips5200";
26 device_type = "cpu";
27 reg = <2>;
28 };
29
30 cpu@3 {
31 compatible = "brcm,bmips5200";
32 device_type = "cpu";
33 reg = <3>;
34 };
35 };
36
37 aliases {
38 uart0 = &uart0;
39 };
40
41 cpu_intc: cpu_intc {
42 #address-cells = <0>;
43 compatible = "mti,cpu-interrupt-controller";
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 clocks {
50 uart_clk: uart_clk {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <81000000>;
54 };
55 };
56
57 rdb {
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 compatible = "simple-bus";
62 ranges = <0 0x10000000 0x01000000>;
63
64 periph_intc: periph_intc@41b500 {
65 compatible = "brcm,bcm7038-l1-intc";
Florian Fainellia5b143e2016-02-03 18:14:51 -0800[diff] [blame]66 reg = <0x41b500 0x40>, <0x41b600 0x40>,
67 <0x41b700 0x40>, <0x41b800 0x40>;
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]68
69 interrupt-controller;
70 #interrupt-cells = <1>;
71
72 interrupt-parent = <&cpu_intc>;
Florian Fainellia5b143e2016-02-03 18:14:51 -0800[diff] [blame]73 interrupts = <2>, <3>, <2>, <3>;
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]74 };
75
76 sun_l2_intc: sun_l2_intc@403000 {
77 compatible = "brcm,l2-intc";
78 reg = <0x403000 0x30>;
79 interrupt-controller;
80 #interrupt-cells = <1>;
81 interrupt-parent = <&periph_intc>;
82 interrupts = <52>;
83 };
84
85 gisb-arb@400000 {
Florian Fainelli6870e702016-01-31 14:52:05 -0800[diff] [blame]86 compatible = "brcm,bcm7435-gisb-arb";
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]87 reg = <0x400000 0xdc>;
88 native-endian;
89 interrupt-parent = <&sun_l2_intc>;
90 interrupts = <0>, <2>;
91 brcm,gisb-arb-master-mask = <0xf77f>;
92 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
93 "pcie_0", "bsp_0",
94 "rdc_0", "raaga_0",
95 "avd_1", "jtag_0",
96 "svd_0", "vice_0",
97 "vice_1", "raaga_1",
98 "scpu";
99 };
100
101 upg_irq0_intc: upg_irq0_intc@406780 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x406780 0x8>;
104
Jaedon Shin5c40d492016-04-06 15:01:08 +0900[diff] [blame^]105 brcm,int-map-mask = <0x44>, <0x7000000>;
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]106 brcm,int-fwd-mask = <0x70000>;
107
108 interrupt-controller;
109 #interrupt-cells = <1>;
110
111 interrupt-parent = <&periph_intc>;
Jaedon Shin5c40d492016-04-06 15:01:08 +0900[diff] [blame^]112 interrupts = <60>, <58>;
113 interrupt-names = "upg_main", "upg_bsc";
114 };
115
116 upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
117 compatible = "brcm,bcm7120-l2-intc";
118 reg = <0x409480 0x8>;
119
120 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
121 brcm,int-fwd-mask = <0>;
122 brcm,irq-can-wake;
123
124 interrupt-controller;
125 #interrupt-cells = <1>;
126
127 interrupt-parent = <&periph_intc>;
128 interrupts = <61>, <59>, <64>;
129 interrupt-names = "upg_main_aon", "upg_bsc_aon",
130 "upg_spi";
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]131 };
132
133 sun_top_ctrl: syscon@404000 {
134 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
135 reg = <0x404000 0x51c>;
Mark Brown25d64632016-01-26 18:08:06 +0000[diff] [blame]136 native-endian;
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]137 };
138
139 reboot {
140 compatible = "brcm,brcmstb-reboot";
141 syscon = <&sun_top_ctrl 0x304 0x308>;
142 };
143
144 uart0: serial@406b00 {
145 compatible = "ns16550a";
146 reg = <0x406b00 0x20>;
147 reg-io-width = <0x4>;
148 reg-shift = <0x2>;
149 interrupt-parent = <&periph_intc>;
150 interrupts = <66>;
151 clocks = <&uart_clk>;
152 status = "disabled";
153 };
154
Jaedon Shin5c40d492016-04-06 15:01:08 +0900[diff] [blame^]155 uart1: serial@406b40 {
156 compatible = "ns16550a";
157 reg = <0x406b40 0x20>;
158 reg-io-width = <0x4>;
159 reg-shift = <0x2>;
160 interrupt-parent = <&periph_intc>;
161 interrupts = <67>;
162 clocks = <&uart_clk>;
163 status = "disabled";
164 };
165
166 uart2: serial@406b80 {
167 compatible = "ns16550a";
168 reg = <0x406b80 0x20>;
169 reg-io-width = <0x4>;
170 reg-shift = <0x2>;
171 interrupt-parent = <&periph_intc>;
172 interrupts = <68>;
173 clocks = <&uart_clk>;
174 status = "disabled";
175 };
176
177 bsca: i2c@406300 {
178 clock-frequency = <390000>;
179 compatible = "brcm,brcmstb-i2c";
180 interrupt-parent = <&upg_irq0_intc>;
181 reg = <0x406300 0x58>;
182 interrupts = <26>;
183 interrupt-names = "upg_bsca";
184 status = "disabled";
185 };
186
187 bscb: i2c@409400 {
188 clock-frequency = <390000>;
189 compatible = "brcm,brcmstb-i2c";
190 interrupt-parent = <&upg_aon_irq0_intc>;
191 reg = <0x409400 0x58>;
192 interrupts = <28>;
193 interrupt-names = "upg_bscb";
194 status = "disabled";
195 };
196
197 bscc: i2c@406200 {
198 clock-frequency = <390000>;
199 compatible = "brcm,brcmstb-i2c";
200 interrupt-parent = <&upg_irq0_intc>;
201 reg = <0x406200 0x58>;
202 interrupts = <24>;
203 interrupt-names = "upg_bscc";
204 status = "disabled";
205 };
206
207 bscd: i2c@406280 {
208 clock-frequency = <390000>;
209 compatible = "brcm,brcmstb-i2c";
210 interrupt-parent = <&upg_irq0_intc>;
211 reg = <0x406280 0x58>;
212 interrupts = <25>;
213 interrupt-names = "upg_bscd";
214 status = "disabled";
215 };
216
217 bsce: i2c@409180 {
218 clock-frequency = <390000>;
219 compatible = "brcm,brcmstb-i2c";
220 interrupt-parent = <&upg_aon_irq0_intc>;
221 reg = <0x409180 0x58>;
222 interrupts = <27>;
223 interrupt-names = "upg_bsce";
224 status = "disabled";
225 };
226
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]227 enet0: ethernet@b80000 {
228 phy-mode = "internal";
229 phy-handle = <&phy1>;
230 mac-address = [ 00 10 18 36 23 1a ];
231 compatible = "brcm,genet-v3";
232 #address-cells = <0x1>;
233 #size-cells = <0x1>;
234 reg = <0xb80000 0x11c88>;
235 interrupts = <17>, <18>;
236 interrupt-parent = <&periph_intc>;
237 status = "disabled";
238
239 mdio@e14 {
240 compatible = "brcm,genet-mdio-v3";
241 #address-cells = <0x1>;
242 #size-cells = <0x0>;
243 reg = <0xe14 0x8>;
244
245 phy1: ethernet-phy@1 {
246 max-speed = <100>;
247 reg = <0x1>;
248 compatible = "brcm,40nm-ephy",
249 "ethernet-phy-ieee802.3-c22";
250 };
251 };
252 };
253
254 ehci0: usb@480300 {
255 compatible = "brcm,bcm7435-ehci", "generic-ehci";
256 reg = <0x480300 0x100>;
257 native-endian;
258 interrupt-parent = <&periph_intc>;
259 interrupts = <70>;
260 status = "disabled";
261 };
262
263 ohci0: usb@480400 {
264 compatible = "brcm,bcm7435-ohci", "generic-ohci";
265 reg = <0x480400 0x100>;
266 native-endian;
267 no-big-frame-no;
268 interrupt-parent = <&periph_intc>;
269 interrupts = <72>;
270 status = "disabled";
271 };
272
273 ehci1: usb@480500 {
274 compatible = "brcm,bcm7435-ehci", "generic-ehci";
275 reg = <0x480500 0x100>;
276 native-endian;
277 interrupt-parent = <&periph_intc>;
278 interrupts = <71>;
279 status = "disabled";
280 };
281
282 ohci1: usb@480600 {
283 compatible = "brcm,bcm7435-ohci", "generic-ohci";
284 reg = <0x480600 0x100>;
285 native-endian;
286 no-big-frame-no;
287 interrupt-parent = <&periph_intc>;
288 interrupts = <73>;
289 status = "disabled";
290 };
291
292 ehci2: usb@490300 {
293 compatible = "brcm,bcm7435-ehci", "generic-ehci";
294 reg = <0x490300 0x100>;
295 native-endian;
296 interrupt-parent = <&periph_intc>;
297 interrupts = <75>;
298 status = "disabled";
299 };
300
301 ohci2: usb@490400 {
302 compatible = "brcm,bcm7435-ohci", "generic-ohci";
303 reg = <0x490400 0x100>;
304 native-endian;
305 no-big-frame-no;
306 interrupt-parent = <&periph_intc>;
307 interrupts = <77>;
308 status = "disabled";
309 };
310
311 ehci3: usb@490500 {
312 compatible = "brcm,bcm7435-ehci", "generic-ehci";
313 reg = <0x490500 0x100>;
314 native-endian;
315 interrupt-parent = <&periph_intc>;
316 interrupts = <76>;
317 status = "disabled";
318 };
319
320 ohci3: usb@490600 {
321 compatible = "brcm,bcm7435-ohci", "generic-ohci";
322 reg = <0x490600 0x100>;
323 native-endian;
324 no-big-frame-no;
325 interrupt-parent = <&periph_intc>;
326 interrupts = <78>;
327 status = "disabled";
328 };
Jaedon Shin5c40d492016-04-06 15:01:08 +0900[diff] [blame^]329
330 sata: sata@181000 {
331 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
332 reg-names = "ahci", "top-ctrl";
333 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
334 interrupt-parent = <&periph_intc>;
335 interrupts = <45>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339
340 sata0: sata-port@0 {
341 reg = <0>;
342 phys = <&sata_phy0>;
343 };
344
345 sata1: sata-port@1 {
346 reg = <1>;
347 phys = <&sata_phy1>;
348 };
349 };
350
351 sata_phy: sata-phy@180100 {
352 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
353 reg = <0x180100 0x0eff>;
354 reg-names = "phy";
355 #address-cells = <1>;
356 #size-cells = <0>;
357 status = "disabled";
358
359 sata_phy0: sata-phy@0 {
360 reg = <0>;
361 #phy-cells = <0>;
362 };
363
364 sata_phy1: sata-phy@1 {
365 reg = <1>;
366 #phy-cells = <0>;
367 };
368 };
Florian Fainellie4c7d002015-05-04 18:10:56 -0700[diff] [blame]369 };
370};