blob: a167b839eccb98f10afd3570c57ca7be19cf4185 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Tomi Valkeinen559d6702009-11-03 11:23:50 +02002/*
Peter Ujfalusi62d9e442016-05-31 11:43:12 +03003 * Copyright (C) 2016 Texas Instruments, Inc.
Tomi Valkeinen559d6702009-11-03 11:23:50 +02004 */
5
Peter Ujfalusi62d9e442016-05-31 11:43:12 +03006#ifndef __OMAPFB_DSS_H
7#define __OMAPFB_DSS_H
Tomi Valkeinen559d6702009-11-03 11:23:50 +02008
9#include <linux/list.h>
10#include <linux/kobject.h>
11#include <linux/device.h>
Tomi Valkeinen348be692012-11-07 18:17:35 +020012#include <linux/interrupt.h>
Peter Ujfalusi62d9e442016-05-31 11:43:12 +030013#include <linux/platform_data/omapdss.h>
Tomi Valkeinen559d6702009-11-03 11:23:50 +020014
Tomi Valkeinen6fcd4852013-05-10 13:02:32 +030015#include <video/videomode.h>
16
Tomi Valkeinen559d6702009-11-03 11:23:50 +020017#define DISPC_IRQ_FRAMEDONE (1 << 0)
18#define DISPC_IRQ_VSYNC (1 << 1)
19#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
20#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
21#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
22#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
23#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
24#define DISPC_IRQ_GFX_END_WIN (1 << 7)
25#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
26#define DISPC_IRQ_OCP_ERR (1 << 9)
27#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
28#define DISPC_IRQ_VID1_END_WIN (1 << 11)
29#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
30#define DISPC_IRQ_VID2_END_WIN (1 << 13)
31#define DISPC_IRQ_SYNC_LOST (1 << 14)
32#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
33#define DISPC_IRQ_WAKEUP (1 << 16)
Sumit Semwal2a205f32010-12-02 11:27:12 +000034#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
35#define DISPC_IRQ_VSYNC2 (1 << 18)
Archit Tanejab8c095b2011-09-13 18:20:33 +053036#define DISPC_IRQ_VID3_END_WIN (1 << 19)
37#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
Sumit Semwal2a205f32010-12-02 11:27:12 +000038#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
39#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
Tomi Valkeinen7f6f3c42011-08-31 13:39:03 +030040#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
41#define DISPC_IRQ_FRAMEDONETV (1 << 24)
42#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
Tomi Valkeinen5bcbab12015-11-04 17:10:40 +020043#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
Chandrabhanu Mahapatra14d33d32012-08-27 14:23:19 +053044#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
45#define DISPC_IRQ_VSYNC3 (1 << 28)
46#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
47#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
Tomi Valkeinen559d6702009-11-03 11:23:50 +020048
49struct omap_dss_device;
50struct omap_overlay_manager;
Tomi Valkeinena97a9632012-10-24 13:52:40 +030051struct dss_lcd_mgr_config;
Ricardo Neri9c0b8422012-03-06 18:20:37 -060052struct snd_aes_iec958;
53struct snd_cea_861_aud_if;
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +030054struct hdmi_avi_infoframe;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020055
56enum omap_display_type {
57 OMAP_DISPLAY_TYPE_NONE = 0,
58 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
59 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
60 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
61 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
62 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
Mythri P Kb1196012011-03-08 17:15:54 +053063 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
Tomi Valkeinenbc24b8b2013-05-13 13:40:33 +030064 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020065};
66
67enum omap_plane {
68 OMAP_DSS_GFX = 0,
69 OMAP_DSS_VIDEO1 = 1,
Archit Tanejab8c095b2011-09-13 18:20:33 +053070 OMAP_DSS_VIDEO2 = 2,
71 OMAP_DSS_VIDEO3 = 3,
Tomi Valkeinen66a0f9e2012-08-22 16:57:02 +030072 OMAP_DSS_WB = 4,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020073};
74
75enum omap_channel {
76 OMAP_DSS_CHANNEL_LCD = 0,
77 OMAP_DSS_CHANNEL_DIGIT = 1,
Sumit Semwal8613b002010-12-02 11:27:09 +000078 OMAP_DSS_CHANNEL_LCD2 = 2,
Chandrabhanu Mahapatraff6331e2012-06-19 15:08:16 +053079 OMAP_DSS_CHANNEL_LCD3 = 3,
Tomi Valkeinen249ad8a2015-11-04 17:10:45 +020080 OMAP_DSS_CHANNEL_WB = 4,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020081};
82
83enum omap_color_mode {
84 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
85 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
86 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
87 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
88 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
89 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
90 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
91 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
92 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
93 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
94 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
95 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
96 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
97 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
Amber Jainf20e4222011-05-19 19:47:50 +053098 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
99 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
100 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
101 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
102 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200103};
104
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200105enum omap_dss_load_mode {
106 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
107 OMAP_DSS_LOAD_CLUT_ONLY = 1,
108 OMAP_DSS_LOAD_FRAME_ONLY = 2,
109 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
110};
111
112enum omap_dss_trans_key_type {
113 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
114 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
115};
116
117enum omap_rfbi_te_mode {
118 OMAP_DSS_RFBI_TE_MODE_1 = 1,
119 OMAP_DSS_RFBI_TE_MODE_2 = 2,
120};
121
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530122enum omap_dss_signal_level {
Tomi Valkeinen7ad582b2014-10-02 17:58:50 +0000123 OMAPDSS_SIG_ACTIVE_LOW,
124 OMAPDSS_SIG_ACTIVE_HIGH,
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530125};
126
127enum omap_dss_signal_edge {
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530128 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
Tomi Valkeinen7ad582b2014-10-02 17:58:50 +0000129 OMAPDSS_DRIVE_SIG_RISING_EDGE,
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530130};
131
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200132enum omap_dss_venc_type {
133 OMAP_DSS_VENC_TYPE_COMPOSITE,
134 OMAP_DSS_VENC_TYPE_SVIDEO,
135};
136
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530137enum omap_dss_dsi_pixel_format {
138 OMAP_DSS_DSI_FMT_RGB888,
139 OMAP_DSS_DSI_FMT_RGB666,
140 OMAP_DSS_DSI_FMT_RGB666_PACKED,
141 OMAP_DSS_DSI_FMT_RGB565,
142};
143
Archit Taneja7e951ee2011-07-22 12:45:04 +0530144enum omap_dss_dsi_mode {
145 OMAP_DSS_DSI_CMD_MODE = 0,
146 OMAP_DSS_DSI_VIDEO_MODE,
147};
148
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200149enum omap_display_caps {
150 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
151 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
152};
153
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200154enum omap_dss_display_state {
155 OMAP_DSS_DISPLAY_DISABLED = 0,
156 OMAP_DSS_DISPLAY_ACTIVE,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200157};
158
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200159enum omap_dss_rotation_type {
Chandrabhanu Mahapatra65e006f2012-05-11 19:19:55 +0530160 OMAP_DSS_ROT_DMA = 1 << 0,
161 OMAP_DSS_ROT_VRFB = 1 << 1,
162 OMAP_DSS_ROT_TILER = 1 << 2,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200163};
164
165/* clockwise rotation angle */
166enum omap_dss_rotation_angle {
167 OMAP_DSS_ROT_0 = 0,
168 OMAP_DSS_ROT_90 = 1,
169 OMAP_DSS_ROT_180 = 2,
170 OMAP_DSS_ROT_270 = 3,
171};
172
173enum omap_overlay_caps {
174 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300175 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
176 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
Archit Taneja11354dd2011-09-26 11:47:29 +0530177 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
Archit Tanejad79db852012-09-22 12:30:17 +0530178 OMAP_DSS_OVL_CAP_POS = 1 << 4,
179 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200180};
181
Archit Taneja484dc402012-09-07 17:38:00 +0530182enum omap_dss_output_id {
183 OMAP_DSS_OUTPUT_DPI = 1 << 0,
184 OMAP_DSS_OUTPUT_DBI = 1 << 1,
185 OMAP_DSS_OUTPUT_SDI = 1 << 2,
186 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
187 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
188 OMAP_DSS_OUTPUT_VENC = 1 << 5,
189 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
190};
191
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200192/* RFBI */
193
194struct rfbi_timings {
195 int cs_on_time;
196 int cs_off_time;
197 int we_on_time;
198 int we_off_time;
199 int re_on_time;
200 int re_off_time;
201 int we_cycle_time;
202 int re_cycle_time;
203 int cs_pulse_width;
204 int access_time;
205
206 int clk_div;
207
208 u32 tim[5]; /* set by rfbi_convert_timings() */
209
210 int converted;
211};
212
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200213/* DSI */
Archit Taneja8af6ff02011-09-05 16:48:27 +0530214
Tomi Valkeinen478d7df2013-03-05 16:29:36 +0200215enum omap_dss_dsi_trans_mode {
216 /* Sync Pulses: both sync start and end packets sent */
217 OMAP_DSS_DSI_PULSE_MODE,
218 /* Sync Events: only sync start packets sent */
219 OMAP_DSS_DSI_EVENT_MODE,
220 /* Burst: only sync start packets sent, pixels are time compressed */
221 OMAP_DSS_DSI_BURST_MODE,
222};
223
Archit Taneja6b8493752012-08-13 22:12:24 +0530224struct omap_dss_dsi_videomode_timings {
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200225 unsigned long hsclk;
226
227 unsigned ndl;
228 unsigned bitspp;
229
230 /* pixels */
231 u16 hact;
232 /* lines */
233 u16 vact;
234
Archit Taneja8af6ff02011-09-05 16:48:27 +0530235 /* DSI video mode blanking data */
236 /* Unit: byte clock cycles */
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200237 u16 hss;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530238 u16 hsa;
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200239 u16 hse;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530240 u16 hfp;
241 u16 hbp;
242 /* Unit: line clocks */
243 u16 vsa;
244 u16 vfp;
245 u16 vbp;
246
247 /* DSI blanking modes */
248 int blanking_mode;
249 int hsa_blanking_mode;
250 int hbp_blanking_mode;
251 int hfp_blanking_mode;
252
Tomi Valkeinen478d7df2013-03-05 16:29:36 +0200253 enum omap_dss_dsi_trans_mode trans_mode;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530254
255 bool ddr_clk_always_on;
256 int window_sync;
257};
258
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200259struct omap_dss_dsi_config {
260 enum omap_dss_dsi_mode mode;
261 enum omap_dss_dsi_pixel_format pixel_format;
262 const struct omap_video_timings *timings;
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200263
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200264 unsigned long hs_clk_min, hs_clk_max;
265 unsigned long lp_clk_min, lp_clk_max;
266
267 bool ddr_clk_always_on;
268 enum omap_dss_dsi_trans_mode trans_mode;
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200269};
270
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200271struct omap_video_timings {
272 /* Unit: pixels */
273 u16 x_res;
274 /* Unit: pixels */
275 u16 y_res;
Tomi Valkeinend8d789412013-04-10 14:12:14 +0300276 /* Unit: Hz */
277 u32 pixelclock;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200278 /* Unit: pixel clocks */
279 u16 hsw; /* Horizontal synchronization pulse width */
280 /* Unit: pixel clocks */
281 u16 hfp; /* Horizontal front porch */
282 /* Unit: pixel clocks */
283 u16 hbp; /* Horizontal back porch */
284 /* Unit: line clocks */
285 u16 vsw; /* Vertical synchronization pulse width */
286 /* Unit: line clocks */
287 u16 vfp; /* Vertical front porch */
288 /* Unit: line clocks */
289 u16 vbp; /* Vertical back porch */
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530290
291 /* Vsync logic level */
292 enum omap_dss_signal_level vsync_level;
293 /* Hsync logic level */
294 enum omap_dss_signal_level hsync_level;
Archit Taneja23c8f882012-06-28 11:15:51 +0530295 /* Interlaced or Progressive timings */
296 bool interlace;
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530297 /* Pixel clock edge to drive LCD data */
298 enum omap_dss_signal_edge data_pclk_edge;
299 /* Data enable logic level */
300 enum omap_dss_signal_level de_level;
301 /* Pixel clock edges to drive HSYNC and VSYNC signals */
302 enum omap_dss_signal_edge sync_pclk_edge;
Tomi Valkeinen3a38ed532016-01-13 18:41:31 +0200303
304 bool double_pixel;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200305};
306
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200307/* Hardcoded timings for tv modes. Venc only uses these to
308 * identify the mode, and does not actually use the configs
309 * itself. However, the configs should be something that
310 * a normal monitor can also show */
Tobias Klauser5a1819e2010-05-20 17:12:52 +0200311extern const struct omap_video_timings omap_dss_pal_timings;
312extern const struct omap_video_timings omap_dss_ntsc_timings;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200313
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300314struct omap_dss_cpr_coefs {
315 s16 rr, rg, rb;
316 s16 gr, gg, gb;
317 s16 br, bg, bb;
318};
319
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200320struct omap_overlay_info {
Arnd Bergmann24f13a62014-04-24 13:28:18 +0100321 dma_addr_t paddr;
322 dma_addr_t p_uv_addr; /* for NV12 format */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200323 u16 screen_width;
324 u16 width;
325 u16 height;
326 enum omap_color_mode color_mode;
327 u8 rotation;
328 enum omap_dss_rotation_type rotation_type;
329 bool mirror;
330
331 u16 pos_x;
332 u16 pos_y;
333 u16 out_width; /* if 0, out_width == width */
334 u16 out_height; /* if 0, out_height == height */
335 u8 global_alpha;
Rajkumar Nfd28a392010-11-04 12:28:42 +0100336 u8 pre_mult_alpha;
Archit Taneja54128702011-09-08 11:29:17 +0530337 u8 zorder;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200338};
339
340struct omap_overlay {
341 struct kobject kobj;
342 struct list_head list;
343
344 /* static fields */
345 const char *name;
Tomi Valkeinen4a9e78a2011-08-15 11:22:21 +0300346 enum omap_plane id;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200347 enum omap_color_mode supported_modes;
348 enum omap_overlay_caps caps;
349
350 /* dynamic fields */
351 struct omap_overlay_manager *manager;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200352
Tomi Valkeinen9d11c322011-11-18 12:38:38 +0200353 /*
354 * The following functions do not block:
355 *
356 * is_enabled
357 * set_overlay_info
358 * get_overlay_info
359 *
360 * The rest of the functions may block and cannot be called from
361 * interrupt context
362 */
363
Tomi Valkeinenaaa874a2011-11-15 16:37:53 +0200364 int (*enable)(struct omap_overlay *ovl);
365 int (*disable)(struct omap_overlay *ovl);
366 bool (*is_enabled)(struct omap_overlay *ovl);
367
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200368 int (*set_manager)(struct omap_overlay *ovl,
369 struct omap_overlay_manager *mgr);
370 int (*unset_manager)(struct omap_overlay *ovl);
371
372 int (*set_overlay_info)(struct omap_overlay *ovl,
373 struct omap_overlay_info *info);
374 void (*get_overlay_info)(struct omap_overlay *ovl,
375 struct omap_overlay_info *info);
376
377 int (*wait_for_go)(struct omap_overlay *ovl);
Archit Taneja794bc4e2012-09-07 17:44:51 +0530378
379 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200380};
381
382struct omap_overlay_manager_info {
383 u32 default_color;
384
385 enum omap_dss_trans_key_type trans_key_type;
386 u32 trans_key;
387 bool trans_enabled;
388
Archit Taneja11354dd2011-09-26 11:47:29 +0530389 bool partial_alpha_enabled;
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300390
391 bool cpr_enable;
392 struct omap_dss_cpr_coefs cpr_coefs;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200393};
394
395struct omap_overlay_manager {
396 struct kobject kobj;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200397
398 /* static fields */
399 const char *name;
Tomi Valkeinen4a9e78a2011-08-15 11:22:21 +0300400 enum omap_channel id;
Tomi Valkeinen07e327c2011-11-05 10:59:59 +0200401 struct list_head overlays;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200402 enum omap_display_type supported_displays;
Archit Taneja97f01b32012-09-26 16:42:39 +0530403 enum omap_dss_output_id supported_outputs;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200404
405 /* dynamic fields */
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300406 struct omap_dss_device *output;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200407
Tomi Valkeinen9d11c322011-11-18 12:38:38 +0200408 /*
409 * The following functions do not block:
410 *
411 * set_manager_info
412 * get_manager_info
413 * apply
414 *
415 * The rest of the functions may block and cannot be called from
416 * interrupt context
417 */
418
Archit Taneja97f01b32012-09-26 16:42:39 +0530419 int (*set_output)(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300420 struct omap_dss_device *output);
Archit Taneja97f01b32012-09-26 16:42:39 +0530421 int (*unset_output)(struct omap_overlay_manager *mgr);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200422
423 int (*set_manager_info)(struct omap_overlay_manager *mgr,
424 struct omap_overlay_manager_info *info);
425 void (*get_manager_info)(struct omap_overlay_manager *mgr,
426 struct omap_overlay_manager_info *info);
427
428 int (*apply)(struct omap_overlay_manager *mgr);
429 int (*wait_for_go)(struct omap_overlay_manager *mgr);
Tomi Valkeinen3f71cbe2010-01-08 17:06:04 +0200430 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
Archit Taneja794bc4e2012-09-07 17:44:51 +0530431
432 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200433};
434
Tomi Valkeinene4a9e942012-03-28 15:58:56 +0300435/* 22 pins means 1 clk lane and 10 data lanes */
436#define OMAP_DSS_MAX_DSI_PINS 22
437
438struct omap_dsi_pin_config {
439 int num_pins;
440 /*
441 * pin numbers in the following order:
442 * clk+, clk-
443 * data1+, data1-
444 * data2+, data2-
445 * ...
446 */
447 int pins[OMAP_DSS_MAX_DSI_PINS];
448};
449
Archit Taneja749feff2012-08-31 12:32:52 +0530450struct omap_dss_writeback_info {
451 u32 paddr;
452 u32 p_uv_addr;
453 u16 buf_width;
454 u16 width;
455 u16 height;
456 enum omap_color_mode color_mode;
457 u8 rotation;
458 enum omap_dss_rotation_type rotation_type;
459 bool mirror;
460 u8 pre_mult_alpha;
461};
462
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300463struct omapdss_dpi_ops {
464 int (*connect)(struct omap_dss_device *dssdev,
465 struct omap_dss_device *dst);
466 void (*disconnect)(struct omap_dss_device *dssdev,
467 struct omap_dss_device *dst);
468
469 int (*enable)(struct omap_dss_device *dssdev);
470 void (*disable)(struct omap_dss_device *dssdev);
471
472 int (*check_timings)(struct omap_dss_device *dssdev,
473 struct omap_video_timings *timings);
474 void (*set_timings)(struct omap_dss_device *dssdev,
475 struct omap_video_timings *timings);
476 void (*get_timings)(struct omap_dss_device *dssdev,
477 struct omap_video_timings *timings);
478
479 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
480};
481
Tomi Valkeinenb1082df2013-05-24 13:19:14 +0300482struct omapdss_sdi_ops {
483 int (*connect)(struct omap_dss_device *dssdev,
484 struct omap_dss_device *dst);
485 void (*disconnect)(struct omap_dss_device *dssdev,
486 struct omap_dss_device *dst);
487
488 int (*enable)(struct omap_dss_device *dssdev);
489 void (*disable)(struct omap_dss_device *dssdev);
490
491 int (*check_timings)(struct omap_dss_device *dssdev,
492 struct omap_video_timings *timings);
493 void (*set_timings)(struct omap_dss_device *dssdev,
494 struct omap_video_timings *timings);
495 void (*get_timings)(struct omap_dss_device *dssdev,
496 struct omap_video_timings *timings);
497
498 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
499};
500
Tomi Valkeinen7700c2d2013-05-24 13:19:30 +0300501struct omapdss_dvi_ops {
502 int (*connect)(struct omap_dss_device *dssdev,
503 struct omap_dss_device *dst);
504 void (*disconnect)(struct omap_dss_device *dssdev,
505 struct omap_dss_device *dst);
506
507 int (*enable)(struct omap_dss_device *dssdev);
508 void (*disable)(struct omap_dss_device *dssdev);
509
510 int (*check_timings)(struct omap_dss_device *dssdev,
511 struct omap_video_timings *timings);
512 void (*set_timings)(struct omap_dss_device *dssdev,
513 struct omap_video_timings *timings);
514 void (*get_timings)(struct omap_dss_device *dssdev,
515 struct omap_video_timings *timings);
516};
517
Tomi Valkeinenfb8efa42013-05-24 13:19:50 +0300518struct omapdss_atv_ops {
519 int (*connect)(struct omap_dss_device *dssdev,
520 struct omap_dss_device *dst);
521 void (*disconnect)(struct omap_dss_device *dssdev,
522 struct omap_dss_device *dst);
523
524 int (*enable)(struct omap_dss_device *dssdev);
525 void (*disable)(struct omap_dss_device *dssdev);
526
527 int (*check_timings)(struct omap_dss_device *dssdev,
528 struct omap_video_timings *timings);
529 void (*set_timings)(struct omap_dss_device *dssdev,
530 struct omap_video_timings *timings);
531 void (*get_timings)(struct omap_dss_device *dssdev,
532 struct omap_video_timings *timings);
533
534 void (*set_type)(struct omap_dss_device *dssdev,
535 enum omap_dss_venc_type type);
536 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
537 bool invert_polarity);
538
539 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
540 u32 (*get_wss)(struct omap_dss_device *dssdev);
541};
542
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300543struct omapdss_hdmi_ops {
544 int (*connect)(struct omap_dss_device *dssdev,
545 struct omap_dss_device *dst);
546 void (*disconnect)(struct omap_dss_device *dssdev,
547 struct omap_dss_device *dst);
548
549 int (*enable)(struct omap_dss_device *dssdev);
550 void (*disable)(struct omap_dss_device *dssdev);
551
552 int (*check_timings)(struct omap_dss_device *dssdev,
553 struct omap_video_timings *timings);
554 void (*set_timings)(struct omap_dss_device *dssdev,
555 struct omap_video_timings *timings);
556 void (*get_timings)(struct omap_dss_device *dssdev,
557 struct omap_video_timings *timings);
558
559 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
560 bool (*detect)(struct omap_dss_device *dssdev);
561
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +0300562 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
563 int (*set_infoframe)(struct omap_dss_device *dssdev,
564 const struct hdmi_avi_infoframe *avi);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300565};
566
Tomi Valkeinendeb16df2013-05-24 13:20:27 +0300567struct omapdss_dsi_ops {
568 int (*connect)(struct omap_dss_device *dssdev,
569 struct omap_dss_device *dst);
570 void (*disconnect)(struct omap_dss_device *dssdev,
571 struct omap_dss_device *dst);
572
573 int (*enable)(struct omap_dss_device *dssdev);
574 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
575 bool enter_ulps);
576
577 /* bus configuration */
578 int (*set_config)(struct omap_dss_device *dssdev,
579 const struct omap_dss_dsi_config *cfg);
580 int (*configure_pins)(struct omap_dss_device *dssdev,
581 const struct omap_dsi_pin_config *pin_cfg);
582
583 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
584 bool enable);
585 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
586
587 int (*update)(struct omap_dss_device *dssdev, int channel,
588 void (*callback)(int, void *), void *data);
589
590 void (*bus_lock)(struct omap_dss_device *dssdev);
591 void (*bus_unlock)(struct omap_dss_device *dssdev);
592
593 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
594 void (*disable_video_output)(struct omap_dss_device *dssdev,
595 int channel);
596
597 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
598 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
599 int vc_id);
600 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
601
602 /* data transfer */
603 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
604 u8 *data, int len);
605 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
606 u8 *data, int len);
607 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
608 u8 *data, int len);
609
610 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
611 u8 *data, int len);
612 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
613 u8 *data, int len);
614 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
615 u8 *reqdata, int reqlen,
616 u8 *data, int len);
617
618 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
619
620 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
621 int channel, u16 plen);
622};
623
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200624struct omap_dss_device {
Tomi Valkeinena38bb792015-02-25 10:23:58 +0200625 struct kobject kobj;
Tomi Valkeinenecc8b372013-02-14 14:17:28 +0200626 struct device *dev;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200627
Tomi Valkeinen4f3e44e2013-05-03 11:35:43 +0300628 struct module *owner;
629
Tomi Valkeinen2e7e3dc2012-11-16 15:45:26 +0200630 struct list_head panel_list;
631
632 /* alias in the form of "display%d" */
633 char alias[16];
634
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200635 enum omap_display_type type;
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300636 enum omap_display_type output_type;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200637
638 union {
639 struct {
640 u8 data_lines;
641 } dpi;
642
643 struct {
644 u8 channel;
645 u8 data_lines;
646 } rfbi;
647
648 struct {
649 u8 datapairs;
650 } sdi;
651
652 struct {
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530653 int module;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200654 } dsi;
655
656 struct {
657 enum omap_dss_venc_type type;
658 bool invert_polarity;
659 } venc;
660 } phy;
661
662 struct {
663 struct omap_video_timings timings;
664
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530665 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
Archit Taneja7e951ee2011-07-22 12:45:04 +0530666 enum omap_dss_dsi_mode dsi_mode;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200667 } panel;
668
669 struct {
670 u8 pixel_size;
671 struct rfbi_timings rfbi_timings;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200672 } ctrl;
673
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200674 const char *name;
675
676 /* used to match device to driver */
677 const char *driver_name;
678
679 void *data;
680
681 struct omap_dss_driver *driver;
682
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300683 union {
684 const struct omapdss_dpi_ops *dpi;
Tomi Valkeinenb1082df2013-05-24 13:19:14 +0300685 const struct omapdss_sdi_ops *sdi;
Tomi Valkeinen7700c2d2013-05-24 13:19:30 +0300686 const struct omapdss_dvi_ops *dvi;
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300687 const struct omapdss_hdmi_ops *hdmi;
Tomi Valkeinenfb8efa42013-05-24 13:19:50 +0300688 const struct omapdss_atv_ops *atv;
Tomi Valkeinendeb16df2013-05-24 13:20:27 +0300689 const struct omapdss_dsi_ops *dsi;
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300690 } ops;
691
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200692 /* helper variable for driver suspend/resume */
693 bool activate_after_resume;
694
695 enum omap_display_caps caps;
696
Tomi Valkeinena73fdc62013-07-24 13:01:34 +0300697 struct omap_dss_device *src;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200698
699 enum omap_dss_display_state state;
700
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300701 /* OMAP DSS output specific fields */
702
703 struct list_head list;
704
705 /* DISPC channel for this output */
706 enum omap_channel dispc_channel;
Tomi Valkeinen49239502015-11-05 09:34:31 +0200707 bool dispc_channel_connected;
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300708
709 /* output instance */
710 enum omap_dss_output_id id;
711
Archit Tanejaef691ff2014-04-22 17:43:48 +0530712 /* the port number in the DT node */
713 int port_num;
714
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300715 /* dynamic fields */
716 struct omap_overlay_manager *manager;
717
Tomi Valkeinen9560dc102013-07-24 13:06:54 +0300718 struct omap_dss_device *dst;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200719};
720
721struct omap_dss_driver {
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200722 int (*probe)(struct omap_dss_device *);
723 void (*remove)(struct omap_dss_device *);
724
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300725 int (*connect)(struct omap_dss_device *dssdev);
726 void (*disconnect)(struct omap_dss_device *dssdev);
727
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200728 int (*enable)(struct omap_dss_device *display);
729 void (*disable)(struct omap_dss_device *display);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200730 int (*run_test)(struct omap_dss_device *display, int test);
731
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200732 int (*update)(struct omap_dss_device *dssdev,
733 u16 x, u16 y, u16 w, u16 h);
734 int (*sync)(struct omap_dss_device *dssdev);
735
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200736 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
Tomi Valkeinen225b6502010-01-11 15:11:01 +0200737 int (*get_te)(struct omap_dss_device *dssdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200738
739 u8 (*get_rotate)(struct omap_dss_device *dssdev);
740 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
741
742 bool (*get_mirror)(struct omap_dss_device *dssdev);
743 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
744
745 int (*memory_read)(struct omap_dss_device *dssdev,
746 void *buf, size_t size,
747 u16 x, u16 y, u16 w, u16 h);
Tomi Valkeinen96adcec2010-01-11 13:54:33 +0200748
749 void (*get_resolution)(struct omap_dss_device *dssdev,
750 u16 *xres, u16 *yres);
Jani Nikula7a0987b2010-06-16 15:26:36 +0300751 void (*get_dimensions)(struct omap_dss_device *dssdev,
752 u32 *width, u32 *height);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200753 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
Tomi Valkeinen36511312010-01-19 15:53:16 +0200754
Tomi Valkeinen69b20482010-01-20 12:11:25 +0200755 int (*check_timings)(struct omap_dss_device *dssdev,
756 struct omap_video_timings *timings);
757 void (*set_timings)(struct omap_dss_device *dssdev,
758 struct omap_video_timings *timings);
759 void (*get_timings)(struct omap_dss_device *dssdev,
760 struct omap_video_timings *timings);
761
Tomi Valkeinen36511312010-01-19 15:53:16 +0200762 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
763 u32 (*get_wss)(struct omap_dss_device *dssdev);
Tomi Valkeinen3d5e0ef2011-08-25 17:10:41 +0300764
765 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
Tomi Valkeinendf4769c2011-08-29 17:26:01 +0300766 bool (*detect)(struct omap_dss_device *dssdev);
Ricardo Neri9c0b8422012-03-06 18:20:37 -0600767
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +0300768 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
769 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
770 const struct hdmi_avi_infoframe *avi);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200771};
772
Mauro Carvalho Chehab771f7be2018-04-20 13:42:51 -0400773#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
774
775typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
776
Mauro Carvalho Chehabf10379a2018-05-04 16:49:32 -0400777#if IS_ENABLED(CONFIG_FB_OMAP2)
Mauro Carvalho Chehab771f7be2018-04-20 13:42:51 -0400778
Tomi Valkeinenb2c7d542012-10-18 13:46:29 +0300779enum omapdss_version omapdss_get_version(void);
Tomi Valkeinen591a0ac2013-05-23 12:07:50 +0300780bool omapdss_is_initialized(void);
Tomi Valkeinenb2c7d542012-10-18 13:46:29 +0300781
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200782int omap_dss_register_driver(struct omap_dss_driver *);
783void omap_dss_unregister_driver(struct omap_dss_driver *);
784
Tomi Valkeinen2e7e3dc2012-11-16 15:45:26 +0200785int omapdss_register_display(struct omap_dss_device *dssdev);
786void omapdss_unregister_display(struct omap_dss_device *dssdev);
787
Tomi Valkeinend35317a2013-05-03 11:40:54 +0300788struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200789void omap_dss_put_device(struct omap_dss_device *dssdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200790struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
791struct omap_dss_device *omap_dss_find_device(void *data,
792 int (*match)(struct omap_dss_device *dssdev, void *data));
Tomi Valkeinen2bbcce52012-10-29 12:40:46 +0200793const char *omapdss_get_default_display_name(void);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200794
Tomi Valkeinen6fcd4852013-05-10 13:02:32 +0300795void videomode_to_omap_video_timings(const struct videomode *vm,
796 struct omap_video_timings *ovt);
797void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
798 struct videomode *vm);
799
Tomi Valkeineneda34272012-11-07 16:26:11 +0200800int dss_feat_get_num_mgrs(void);
801int dss_feat_get_num_ovls(void);
Tomi Valkeineneda34272012-11-07 16:26:11 +0200802enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
803
804
805
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200806int omap_dss_get_num_overlay_managers(void);
807struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
808
809int omap_dss_get_num_overlays(void);
810struct omap_overlay *omap_dss_get_overlay(int num);
811
Tomi Valkeinen5d47dbc2013-04-24 13:32:51 +0300812int omapdss_register_output(struct omap_dss_device *output);
813void omapdss_unregister_output(struct omap_dss_device *output);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300814struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
815struct omap_dss_device *omap_dss_find_output(const char *name);
Archit Tanejaef691ff2014-04-22 17:43:48 +0530816struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300817int omapdss_output_set_device(struct omap_dss_device *out,
Archit Taneja6d71b922012-08-29 13:30:15 +0530818 struct omap_dss_device *dssdev);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300819int omapdss_output_unset_device(struct omap_dss_device *out);
Archit Taneja484dc402012-09-07 17:38:00 +0530820
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300821struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
Tomi Valkeinenbe8e8e12013-04-23 15:35:35 +0300822struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
823
Tomi Valkeinen96adcec2010-01-11 13:54:33 +0200824void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
825 u16 *xres, u16 *yres);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200826int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
Grazvydas Ignotas4b6430f2012-03-15 20:00:23 +0200827void omapdss_default_get_timings(struct omap_dss_device *dssdev,
828 struct omap_video_timings *timings);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200829
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200830int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
831int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
832
Tomi Valkeinen8dd24912012-10-10 10:26:45 +0300833int omapdss_compat_init(void);
834void omapdss_compat_uninit(void);
835
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300836static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
837{
Tomi Valkeinena73fdc62013-07-24 13:01:34 +0300838 return dssdev->src;
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300839}
840
841static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
842{
843 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
844}
845
Tomi Valkeinen4e7470d2013-12-03 16:57:40 +0200846struct device_node *
847omapdss_of_get_next_port(const struct device_node *parent,
848 struct device_node *prev);
849
850struct device_node *
851omapdss_of_get_next_endpoint(const struct device_node *parent,
852 struct device_node *prev);
853
854struct device_node *
855omapdss_of_get_first_endpoint(const struct device_node *parent);
856
857struct omap_dss_device *
858omapdss_of_find_source_for_first_ep(struct device_node *node);
Mauro Carvalho Chehab771f7be2018-04-20 13:42:51 -0400859#else
860
861static inline enum omapdss_version omapdss_get_version(void)
862{ return OMAPDSS_VER_UNKNOWN; };
863
864static inline bool omapdss_is_initialized(void)
865{ return false; };
866
867static inline int omap_dispc_register_isr(omap_dispc_isr_t isr,
868 void *arg, u32 mask)
869{ return 0; };
870
871static inline int omap_dispc_unregister_isr(omap_dispc_isr_t isr,
872 void *arg, u32 mask)
873{ return 0; };
874
875static inline struct omap_dss_device
876*omap_dss_get_device(struct omap_dss_device *dssdev)
877{ return NULL; };
878
879static inline struct omap_dss_device
880*omap_dss_get_next_device(struct omap_dss_device *from)
881{return NULL; };
882
883static inline void omap_dss_put_device(struct omap_dss_device *dssdev) {};
884
885static inline int omapdss_compat_init(void)
886{ return 0; };
887
888static inline void omapdss_compat_uninit(void) {};
889
890static inline int omap_dss_get_num_overlay_managers(void)
891{ return 0; };
892
893static inline struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
894{ return NULL; };
895
896static inline int omap_dss_get_num_overlays(void)
897{ return 0; };
898
899static inline struct omap_overlay *omap_dss_get_overlay(int num)
900{ return NULL; };
901
902
903#endif /* FB_OMAP2 */
904
Tomi Valkeinen4e7470d2013-12-03 16:57:40 +0200905
Peter Ujfalusi62d9e442016-05-31 11:43:12 +0300906#endif /* __OMAPFB_DSS_H */