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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 4f7799d96e6621ce584df60739e1480a6fd89f0a / . / drivers / irqchip / Kconfig
blob: d564d21245c5c3aa7ccafc39dc0964170e1de6e0 [file] [log] [blame]
Randy Dunlapc94fb632017-10-16 11:04:33 -0700[diff] [blame]1menu "IRQ chip support"
2
Thomas Petazzonif6e916b2012-11-20 23:00:52 +0100[diff] [blame]3config IRQCHIP
4 def_bool y
5 depends on OF_IRQ
6
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]7config ARM_GIC
8 bool
9 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +0800[diff] [blame]10 select IRQ_DOMAIN_HIERARCHY
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]11 select GENERIC_IRQ_MULTI_HANDLER
Marc Zyngier0c9e4982017-08-18 09:39:16 +0100[diff] [blame]12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]13
Jon Hunter9c8eddd2016-06-07 16:12:34 +0100[diff] [blame]14config ARM_GIC_PM
15 bool
16 depends on PM
17 select ARM_GIC
18 select PM_CLK
19
Linus Walleija27d21e2015-12-18 10:44:53 +0100[diff] [blame]20config ARM_GIC_MAX_NR
21 int
22 default 2 if ARCH_REALVIEW
23 default 1
24
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +0000[diff] [blame]25config ARM_GIC_V2M
26 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]27 depends on PCI
28 select ARM_GIC
29 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +0000[diff] [blame]30
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]31config GIC_NON_BANKED
32 bool
33
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]34config ARM_GIC_V3
35 bool
36 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]37 select GENERIC_IRQ_MULTI_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +0000[diff] [blame]38 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +0100[diff] [blame]39 select PARTITION_PERCPU
Marc Zyngier956ae912017-08-18 09:39:17 +0100[diff] [blame]40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]41
Marc Zyngier19812722014-11-24 14:35:19 +0000[diff] [blame]42config ARM_GIC_V3_ITS
43 bool
Marc Zyngier29f41132017-11-13 17:25:59 +0000[diff] [blame]44 select GENERIC_MSI_IRQ_DOMAIN
45 default ARM_GIC_V3
46
47config ARM_GIC_V3_ITS_PCI
48 bool
49 depends on ARM_GIC_V3_ITS
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]50 depends on PCI
51 depends on PCI_MSI
Marc Zyngier29f41132017-11-13 17:25:59 +0000[diff] [blame]52 default ARM_GIC_V3_ITS
Uwe Kleine-König292ec082013-06-26 09:18:48 +0200[diff] [blame]53
Bogdan Purcareata7afe0312018-02-05 08:07:43 -0600[diff] [blame]54config ARM_GIC_V3_ITS_FSL_MC
55 bool
56 depends on ARM_GIC_V3_ITS
57 depends on FSL_MC_BUS
58 default ARM_GIC_V3_ITS
59
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]60config ARM_NVIC
61 bool
62 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +0200[diff] [blame]63 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]64 select GENERIC_IRQ_CHIP
65
66config ARM_VIC
67 bool
68 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]69 select GENERIC_IRQ_MULTI_HANDLER
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]70
71config ARM_VIC_NR
72 int
73 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]74 default 2
75 depends on ARM_VIC
76 help
77 The maximum number of VICs available in the system, for
78 power management.
79
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]80config ARMADA_370_XP_IRQ
81 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]82 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]83 select PCI_MSI if PCI
Marc Zyngiere31793a2017-08-18 09:39:19 +0100[diff] [blame]84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]85
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]86config ALPINE_MSI
87 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]88 depends on PCI
89 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]90 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]91
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]92config ATMEL_AIC_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]96 select GENERIC_IRQ_MULTI_HANDLER
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]97 select SPARSE_IRQ
98
99config ATMEL_AIC5_IRQ
100 bool
101 select GENERIC_IRQ_CHIP
102 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]103 select GENERIC_IRQ_MULTI_HANDLER
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]104 select SPARSE_IRQ
105
Ralf Baechle0509cfd2015-07-08 14:46:08 +0200[diff] [blame]106config I8259
107 bool
108 select IRQ_DOMAIN
109
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000[diff] [blame]110config BCM6345_L1_IRQ
111 bool
112 select GENERIC_IRQ_CHIP
113 select IRQ_DOMAIN
Marc Zyngierd0ed5e82017-08-18 09:39:20 +0100[diff] [blame]114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000[diff] [blame]115
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800[diff] [blame]116config BCM7038_L1_IRQ
117 bool
118 select GENERIC_IRQ_CHIP
119 select IRQ_DOMAIN
Marc Zyngierb8d98842017-08-18 09:39:21 +0100[diff] [blame]120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800[diff] [blame]121
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800[diff] [blame]122config BCM7120_L2_IRQ
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]127config BRCMSTB_L2_IRQ
128 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]132config DW_APB_ICTL
133 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800[diff] [blame]134 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]135 select IRQ_DOMAIN
136
Linus Walleij6ee532e2017-03-18 17:53:24 +0100[diff] [blame]137config FARADAY_FTINTC010
138 bool
139 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]140 select GENERIC_IRQ_MULTI_HANDLER
Linus Walleij6ee532e2017-03-18 17:53:24 +0100[diff] [blame]141 select SPARSE_IRQ
142
MaJun9a7c4ab2016-03-23 17:06:33 +0800[diff] [blame]143config HISILICON_IRQ_MBIGEN
144 bool
145 select ARM_GIC_V3
146 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800[diff] [blame]147
James Hoganb6ef9162013-04-22 15:43:50 +0100[diff] [blame]148config IMGPDC_IRQ
149 bool
150 select GENERIC_IRQ_CHIP
151 select IRQ_DOMAIN
152
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200[diff] [blame]153config IRQ_MIPS_CPU
154 bool
155 select GENERIC_IRQ_CHIP
Paul Burton3838a542017-03-30 12:06:11 -0700[diff] [blame]156 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200[diff] [blame]157 select IRQ_DOMAIN
Paul Burton3838a542017-03-30 12:06:11 -0700[diff] [blame]158 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
Marc Zyngier18416e42017-08-18 09:39:24 +0100[diff] [blame]159 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200[diff] [blame]160
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400[diff] [blame]161config CLPS711X_IRQCHIP
162 bool
163 depends on ARCH_CLPS711X
164 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]165 select GENERIC_IRQ_MULTI_HANDLER
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400[diff] [blame]166 select SPARSE_IRQ
167 default y
168
Stafford Horne9b544702017-10-30 21:38:35 +0900[diff] [blame]169config OMPIC
170 bool
171
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300[diff] [blame]172config OR1K_PIC
173 bool
174 select IRQ_DOMAIN
175
Felipe Balbi85980662014-09-15 16:15:02 -0500[diff] [blame]176config OMAP_IRQCHIP
177 bool
178 select GENERIC_IRQ_CHIP
179 select IRQ_DOMAIN
180
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200[diff] [blame]181config ORION_IRQCHIP
182 bool
183 select IRQ_DOMAIN
Palmer Dabbelt4f7799d2018-06-22 10:01:26 -0700[diff] [blame^]184 select GENERIC_IRQ_MULTI_HANDLER
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200[diff] [blame]185
Cristian Birsanaaa86662016-01-13 18:15:35 -0700[diff] [blame]186config PIC32_EVIC
187 bool
188 select GENERIC_IRQ_CHIP
189 select IRQ_DOMAIN
190
Rich Felker981b58f2016-08-04 04:30:37 +0000[diff] [blame]191config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000[diff] [blame]192 bool "J-Core integrated AIC" if COMPILE_TEST
193 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000[diff] [blame]194 select IRQ_DOMAIN
195 help
196 Support for the J-Core integrated AIC.
197
Magnus Damm44358042013-02-18 23:28:34 +0900[diff] [blame]198config RENESAS_INTC_IRQPIN
199 bool
200 select IRQ_DOMAIN
201
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]202config RENESAS_IRQC
203 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900[diff] [blame]204 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]205 select IRQ_DOMAIN
206
Lee Jones07088482015-02-18 15:13:58 +0000[diff] [blame]207config ST_IRQCHIP
208 bool
209 select REGMAP
210 select MFD_SYSCON
211 help
212 Enables SysCfg Controlled IRQs on STi based platforms.
213
Mans Rullgard4bba6682016-01-20 18:07:17 +0000[diff] [blame]214config TANGO_IRQ
215 bool
216 select IRQ_DOMAIN
217 select GENERIC_IRQ_CHIP
218
Christian Ruppertb06eb012013-06-25 18:29:57 +0200[diff] [blame]219config TB10X_IRQC
220 bool
221 select IRQ_DOMAIN
222 select GENERIC_IRQ_CHIP
223
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]224config TS4800_IRQ
225 tristate "TS-4800 IRQ controller"
226 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100[diff] [blame]227 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100[diff] [blame]228 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]229 help
230 Support for the TS-4800 FPGA IRQ controller
231
Linus Walleij2389d502012-10-31 22:04:31 +0100[diff] [blame]232config VERSATILE_FPGA_IRQ
233 bool
234 select IRQ_DOMAIN
235
236config VERSATILE_FPGA_IRQ_NR
237 int
238 default 4
239 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400[diff] [blame]240
241config XTENSA_MX
242 bool
243 select IRQ_DOMAIN
Marc Zyngier50091212017-08-18 09:39:25 +0100[diff] [blame]244 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]245
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000[diff] [blame]246config XILINX_INTC
247 bool
248 select IRQ_DOMAIN
249
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]250config IRQ_CROSSBAR
251 bool
252 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900[diff] [blame]253 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]254 The primary irqchip invokes the crossbar's callback which inturn allocates
255 a free irq and configures the IP. Thus the peripheral interrupts are
256 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300[diff] [blame]257
258config KEYSTONE_IRQ
259 tristate "Keystone 2 IRQ controller IP"
260 depends on ARCH_KEYSTONE
261 help
262 Support for Texas Instruments Keystone 2 IRQ controller IP which
263 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700[diff] [blame]264
265config MIPS_GIC
266 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000[diff] [blame]267 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000[diff] [blame]268 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700[diff] [blame]269 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]270
Paul Burton44e08e72015-05-24 16:11:31 +0100[diff] [blame]271config INGENIC_IRQ
272 bool
273 depends on MACH_INGENIC
274 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]275
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]276config RENESAS_H8300H_INTC
277 bool
278 select IRQ_DOMAIN
279
280config RENESAS_H8S_INTC
281 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]282 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500[diff] [blame]283
284config IMX_GPCV2
285 bool
286 select IRQ_DOMAIN
287 help
288 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200[diff] [blame]289
290config IRQ_MXS
291 def_bool y if MACH_ASM9260 || ARCH_MXS
292 select IRQ_DOMAIN
293 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100[diff] [blame]294
Alexandre Belloni19d99162018-03-22 16:15:24 +0100[diff] [blame]295config MSCC_OCELOT_IRQ
296 bool
297 select IRQ_DOMAIN
298 select GENERIC_IRQ_CHIP
299
Thomas Petazzonia68a63c2017-06-21 15:29:14 +0200[diff] [blame]300config MVEBU_GICP
301 bool
302
Thomas Petazzonie0de91a2017-06-21 15:29:15 +0200[diff] [blame]303config MVEBU_ICU
304 bool
305
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100[diff] [blame]306config MVEBU_ODMI
307 bool
Arnd Bergmannfa23b9d2017-03-14 13:54:12 +0100[diff] [blame]308 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100[diff] [blame]309
Thomas Petazzonia1098932016-08-05 16:55:19 +0200[diff] [blame]310config MVEBU_PIC
311 bool
312
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800[diff] [blame]313config LS_SCFG_MSI
314 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
315 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800[diff] [blame]316
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100[diff] [blame]317config PARTITION_PERCPU
318 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700[diff] [blame]319
Noam Camus44df427c2015-10-29 00:26:22 +0200[diff] [blame]320config EZNPS_GIC
321 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200[diff] [blame]322 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200[diff] [blame]323 select IRQ_DOMAIN
324 help
325 Support the EZchip NPS400 global interrupt controller
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200[diff] [blame]326
327config STM32_EXTI
328 bool
329 select IRQ_DOMAIN
Ludovic Barre0e7d7802017-11-06 18:03:31 +0100[diff] [blame]330 select GENERIC_IRQ_CHIP
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500[diff] [blame]331
332config QCOM_IRQ_COMBINER
333 bool "QCOM IRQ combiner support"
334 depends on ARCH_QCOM && ACPI
335 select IRQ_DOMAIN
336 select IRQ_DOMAIN_HIERARCHY
337 help
338 Say yes here to add support for the IRQ combiner devices embedded
339 in Qualcomm Technologies chips.
Masahiro Yamada5ed34d3a2017-08-23 10:31:47 +0900[diff] [blame]340
341config IRQ_UNIPHIER_AIDET
342 bool "UniPhier AIDET support" if COMPILE_TEST
343 depends on ARCH_UNIPHIER || COMPILE_TEST
344 default ARCH_UNIPHIER
345 select IRQ_DOMAIN_HIERARCHY
346 help
347 Support for the UniPhier AIDET (ARM Interrupt Detector).
Randy Dunlapc94fb632017-10-16 11:04:33 -0700[diff] [blame]348
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200[diff] [blame]349config MESON_IRQ_GPIO
350 bool "Meson GPIO Interrupt Multiplexer"
Thomas Gleixnerd9ee91c2017-10-20 11:15:36 +0200[diff] [blame]351 depends on ARCH_MESON
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200[diff] [blame]352 select IRQ_DOMAIN
353 select IRQ_DOMAIN_HIERARCHY
354 help
355 Support Meson SoC Family GPIO Interrupt Multiplexer
356
Miodrag Dinic4235ff52017-12-29 16:41:46 +0100[diff] [blame]357config GOLDFISH_PIC
358 bool "Goldfish programmable interrupt controller"
359 depends on MIPS && (GOLDFISH || COMPILE_TEST)
360 select IRQ_DOMAIN
361 help
362 Say yes here to enable Goldfish interrupt controller driver used
363 for Goldfish based virtual platforms.
364
Archana Sathyakumarf55c73a2018-02-28 10:27:29 -0700[diff] [blame]365config QCOM_PDC
366 bool "QCOM PDC"
367 depends on ARCH_QCOM
368 select IRQ_DOMAIN
369 select IRQ_DOMAIN_HIERARCHY
370 help
371 Power Domain Controller driver to manage and configure wakeup
372 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
373
Randy Dunlapc94fb632017-10-16 11:04:33 -0700[diff] [blame]374endmenu