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Randy Dunlapc94fb632017-10-16 11:04:33 -07001menu "IRQ chip support"
2
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01003config IRQCHIP
4 def_bool y
5 depends on OF_IRQ
6
Rob Herring81243e42012-11-20 21:21:40 -06007config ARM_GIC
8 bool
9 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +080010 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -060011 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -070012 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Marc Zyngier0c9e4982017-08-18 09:39:16 +010013 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Rob Herring81243e42012-11-20 21:21:40 -060014
Jon Hunter9c8eddd2016-06-07 16:12:34 +010015config ARM_GIC_PM
16 bool
17 depends on PM
18 select ARM_GIC
19 select PM_CLK
20
Linus Walleija27d21e2015-12-18 10:44:53 +010021config ARM_GIC_MAX_NR
22 int
23 default 2 if ARCH_REALVIEW
24 default 1
25
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000026config ARM_GIC_V2M
27 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050028 depends on PCI
29 select ARM_GIC
30 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000031
Rob Herring81243e42012-11-20 21:21:40 -060032config GIC_NON_BANKED
33 bool
34
Marc Zyngier021f6532014-06-30 16:01:31 +010035config ARM_GIC_V3
36 bool
37 select IRQ_DOMAIN
38 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -070039 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000040 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010041 select PARTITION_PERCPU
Marc Zyngier956ae912017-08-18 09:39:17 +010042 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Marc Zyngier021f6532014-06-30 16:01:31 +010043
Marc Zyngier19812722014-11-24 14:35:19 +000044config ARM_GIC_V3_ITS
45 bool
Marc Zyngier29f41132017-11-13 17:25:59 +000046 select GENERIC_MSI_IRQ_DOMAIN
47 default ARM_GIC_V3
48
49config ARM_GIC_V3_ITS_PCI
50 bool
51 depends on ARM_GIC_V3_ITS
Arnd Bergmann3ee803642016-06-15 15:47:33 -050052 depends on PCI
53 depends on PCI_MSI
Marc Zyngier29f41132017-11-13 17:25:59 +000054 default ARM_GIC_V3_ITS
Uwe Kleine-König292ec082013-06-26 09:18:48 +020055
Bogdan Purcareata7afe0312018-02-05 08:07:43 -060056config ARM_GIC_V3_ITS_FSL_MC
57 bool
58 depends on ARM_GIC_V3_ITS
59 depends on FSL_MC_BUS
60 default ARM_GIC_V3_ITS
61
Rob Herring44430ec2012-10-27 17:25:26 -050062config ARM_NVIC
63 bool
64 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020065 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050066 select GENERIC_IRQ_CHIP
67
68config ARM_VIC
69 bool
70 select IRQ_DOMAIN
71 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -070072 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Rob Herring44430ec2012-10-27 17:25:26 -050073
74config ARM_VIC_NR
75 int
76 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050077 default 2
78 depends on ARM_VIC
79 help
80 The maximum number of VICs available in the system, for
81 power management.
82
Thomas Petazzonifed6d332016-02-10 15:46:56 +010083config ARMADA_370_XP_IRQ
84 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010085 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee803642016-06-15 15:47:33 -050086 select PCI_MSI if PCI
Marc Zyngiere31793a2017-08-18 09:39:19 +010087 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Thomas Petazzonifed6d332016-02-10 15:46:56 +010088
Antoine Tenarte6b78f22016-02-19 16:22:44 +010089config ALPINE_MSI
90 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050091 depends on PCI
92 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +010093 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +010094
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020095config ATMEL_AIC_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
99 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -0700100 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200101 select SPARSE_IRQ
102
103config ATMEL_AIC5_IRQ
104 bool
105 select GENERIC_IRQ_CHIP
106 select IRQ_DOMAIN
107 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -0700108 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200109 select SPARSE_IRQ
110
Ralf Baechle0509cfd2015-07-08 14:46:08 +0200111config I8259
112 bool
113 select IRQ_DOMAIN
114
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000115config BCM6345_L1_IRQ
116 bool
117 select GENERIC_IRQ_CHIP
118 select IRQ_DOMAIN
Marc Zyngierd0ed5e82017-08-18 09:39:20 +0100119 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000120
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800121config BCM7038_L1_IRQ
122 bool
123 select GENERIC_IRQ_CHIP
124 select IRQ_DOMAIN
Marc Zyngierb8d98842017-08-18 09:39:21 +0100125 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800126
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800127config BCM7120_L2_IRQ
128 bool
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
Florian Fainelli7f646e92014-05-23 17:40:53 -0700132config BRCMSTB_L2_IRQ
133 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700134 select GENERIC_IRQ_CHIP
135 select IRQ_DOMAIN
136
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200137config DW_APB_ICTL
138 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800139 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200140 select IRQ_DOMAIN
141
Linus Walleij6ee532e2017-03-18 17:53:24 +0100142config FARADAY_FTINTC010
143 bool
144 select IRQ_DOMAIN
145 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -0700146 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Linus Walleij6ee532e2017-03-18 17:53:24 +0100147 select SPARSE_IRQ
148
MaJun9a7c4ab2016-03-23 17:06:33 +0800149config HISILICON_IRQ_MBIGEN
150 bool
151 select ARM_GIC_V3
152 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800153
James Hoganb6ef9162013-04-22 15:43:50 +0100154config IMGPDC_IRQ
155 bool
156 select GENERIC_IRQ_CHIP
157 select IRQ_DOMAIN
158
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200159config IRQ_MIPS_CPU
160 bool
161 select GENERIC_IRQ_CHIP
Paul Burton3838a542017-03-30 12:06:11 -0700162 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200163 select IRQ_DOMAIN
Paul Burton3838a542017-03-30 12:06:11 -0700164 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
Marc Zyngier18416e42017-08-18 09:39:24 +0100165 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200166
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400167config CLPS711X_IRQCHIP
168 bool
169 depends on ARCH_CLPS711X
170 select IRQ_DOMAIN
171 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -0700172 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400173 select SPARSE_IRQ
174 default y
175
Stafford Horne9b544702017-10-30 21:38:35 +0900176config OMPIC
177 bool
178
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300179config OR1K_PIC
180 bool
181 select IRQ_DOMAIN
182
Felipe Balbi85980662014-09-15 16:15:02 -0500183config OMAP_IRQCHIP
184 bool
185 select GENERIC_IRQ_CHIP
186 select IRQ_DOMAIN
187
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200188config ORION_IRQCHIP
189 bool
190 select IRQ_DOMAIN
191 select MULTI_IRQ_HANDLER
Palmer Dabbelt08fb5502018-06-22 10:01:22 -0700192 select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200193
Cristian Birsanaaa86662016-01-13 18:15:35 -0700194config PIC32_EVIC
195 bool
196 select GENERIC_IRQ_CHIP
197 select IRQ_DOMAIN
198
Rich Felker981b58f2016-08-04 04:30:37 +0000199config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000200 bool "J-Core integrated AIC" if COMPILE_TEST
201 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000202 select IRQ_DOMAIN
203 help
204 Support for the J-Core integrated AIC.
205
Magnus Damm44358042013-02-18 23:28:34 +0900206config RENESAS_INTC_IRQPIN
207 bool
208 select IRQ_DOMAIN
209
Magnus Dammfbc83b72013-02-27 17:15:01 +0900210config RENESAS_IRQC
211 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900212 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900213 select IRQ_DOMAIN
214
Lee Jones07088482015-02-18 15:13:58 +0000215config ST_IRQCHIP
216 bool
217 select REGMAP
218 select MFD_SYSCON
219 help
220 Enables SysCfg Controlled IRQs on STi based platforms.
221
Mans Rullgard4bba6682016-01-20 18:07:17 +0000222config TANGO_IRQ
223 bool
224 select IRQ_DOMAIN
225 select GENERIC_IRQ_CHIP
226
Christian Ruppertb06eb012013-06-25 18:29:57 +0200227config TB10X_IRQC
228 bool
229 select IRQ_DOMAIN
230 select GENERIC_IRQ_CHIP
231
Damien Riegeld01f8632015-12-21 15:11:23 -0500232config TS4800_IRQ
233 tristate "TS-4800 IRQ controller"
234 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100235 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100236 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500237 help
238 Support for the TS-4800 FPGA IRQ controller
239
Linus Walleij2389d502012-10-31 22:04:31 +0100240config VERSATILE_FPGA_IRQ
241 bool
242 select IRQ_DOMAIN
243
244config VERSATILE_FPGA_IRQ_NR
245 int
246 default 4
247 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400248
249config XTENSA_MX
250 bool
251 select IRQ_DOMAIN
Marc Zyngier50091212017-08-18 09:39:25 +0100252 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Sricharan R96ca8482013-12-03 15:57:23 +0530253
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000254config XILINX_INTC
255 bool
256 select IRQ_DOMAIN
257
Sricharan R96ca8482013-12-03 15:57:23 +0530258config IRQ_CROSSBAR
259 bool
260 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900261 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530262 The primary irqchip invokes the crossbar's callback which inturn allocates
263 a free irq and configures the IP. Thus the peripheral interrupts are
264 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300265
266config KEYSTONE_IRQ
267 tristate "Keystone 2 IRQ controller IP"
268 depends on ARCH_KEYSTONE
269 help
270 Support for Texas Instruments Keystone 2 IRQ controller IP which
271 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700272
273config MIPS_GIC
274 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000275 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000276 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700277 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900278
Paul Burton44e08e72015-05-24 16:11:31 +0100279config INGENIC_IRQ
280 bool
281 depends on MACH_INGENIC
282 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700283
Yoshinori Sato8a764482015-05-10 02:30:47 +0900284config RENESAS_H8300H_INTC
285 bool
286 select IRQ_DOMAIN
287
288config RENESAS_H8S_INTC
289 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700290 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500291
292config IMX_GPCV2
293 bool
294 select IRQ_DOMAIN
295 help
296 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200297
298config IRQ_MXS
299 def_bool y if MACH_ASM9260 || ARCH_MXS
300 select IRQ_DOMAIN
301 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100302
Alexandre Belloni19d99162018-03-22 16:15:24 +0100303config MSCC_OCELOT_IRQ
304 bool
305 select IRQ_DOMAIN
306 select GENERIC_IRQ_CHIP
307
Thomas Petazzonia68a63c2017-06-21 15:29:14 +0200308config MVEBU_GICP
309 bool
310
Thomas Petazzonie0de91a2017-06-21 15:29:15 +0200311config MVEBU_ICU
312 bool
313
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100314config MVEBU_ODMI
315 bool
Arnd Bergmannfa23b9d2017-03-14 13:54:12 +0100316 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100317
Thomas Petazzonia1098932016-08-05 16:55:19 +0200318config MVEBU_PIC
319 bool
320
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800321config LS_SCFG_MSI
322 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
323 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800324
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100325config PARTITION_PERCPU
326 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700327
Noam Camus44df427c2015-10-29 00:26:22 +0200328config EZNPS_GIC
329 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200330 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200331 select IRQ_DOMAIN
332 help
333 Support the EZchip NPS400 global interrupt controller
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200334
335config STM32_EXTI
336 bool
337 select IRQ_DOMAIN
Ludovic Barre0e7d7802017-11-06 18:03:31 +0100338 select GENERIC_IRQ_CHIP
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500339
340config QCOM_IRQ_COMBINER
341 bool "QCOM IRQ combiner support"
342 depends on ARCH_QCOM && ACPI
343 select IRQ_DOMAIN
344 select IRQ_DOMAIN_HIERARCHY
345 help
346 Say yes here to add support for the IRQ combiner devices embedded
347 in Qualcomm Technologies chips.
Masahiro Yamada5ed34d3a2017-08-23 10:31:47 +0900348
349config IRQ_UNIPHIER_AIDET
350 bool "UniPhier AIDET support" if COMPILE_TEST
351 depends on ARCH_UNIPHIER || COMPILE_TEST
352 default ARCH_UNIPHIER
353 select IRQ_DOMAIN_HIERARCHY
354 help
355 Support for the UniPhier AIDET (ARM Interrupt Detector).
Randy Dunlapc94fb632017-10-16 11:04:33 -0700356
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200357config MESON_IRQ_GPIO
358 bool "Meson GPIO Interrupt Multiplexer"
Thomas Gleixnerd9ee91c2017-10-20 11:15:36 +0200359 depends on ARCH_MESON
Jerome Brunet215f4cc2017-09-18 15:46:10 +0200360 select IRQ_DOMAIN
361 select IRQ_DOMAIN_HIERARCHY
362 help
363 Support Meson SoC Family GPIO Interrupt Multiplexer
364
Miodrag Dinic4235ff52017-12-29 16:41:46 +0100365config GOLDFISH_PIC
366 bool "Goldfish programmable interrupt controller"
367 depends on MIPS && (GOLDFISH || COMPILE_TEST)
368 select IRQ_DOMAIN
369 help
370 Say yes here to enable Goldfish interrupt controller driver used
371 for Goldfish based virtual platforms.
372
Archana Sathyakumarf55c73a2018-02-28 10:27:29 -0700373config QCOM_PDC
374 bool "QCOM PDC"
375 depends on ARCH_QCOM
376 select IRQ_DOMAIN
377 select IRQ_DOMAIN_HIERARCHY
378 help
379 Power Domain Controller driver to manage and configure wakeup
380 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
381
Randy Dunlapc94fb632017-10-16 11:04:33 -0700382endmenu