Randy Dunlap | c94fb63 | 2017-10-16 11:04:33 -0700 | [diff] [blame] | 1 | menu "IRQ chip support" |
2 | |||||
Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 3 | config IRQCHIP |
4 | def_bool y | ||||
5 | depends on OF_IRQ | ||||
6 | |||||
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 7 | config ARM_GIC |
8 | bool | ||||
9 | select IRQ_DOMAIN | ||||
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 10 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 11 | select MULTI_IRQ_HANDLER |
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 12 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Marc Zyngier | 0c9e498 | 2017-08-18 09:39:16 +0100 | [diff] [blame] | 13 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 14 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 15 | config ARM_GIC_PM |
16 | bool | ||||
17 | depends on PM | ||||
18 | select ARM_GIC | ||||
19 | select PM_CLK | ||||
20 | |||||
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 21 | config ARM_GIC_MAX_NR |
22 | int | ||||
23 | default 2 if ARCH_REALVIEW | ||||
24 | default 1 | ||||
25 | |||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 26 | config ARM_GIC_V2M |
27 | bool | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 28 | depends on PCI |
29 | select ARM_GIC | ||||
30 | select PCI_MSI | ||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 31 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 32 | config GIC_NON_BANKED |
33 | bool | ||||
34 | |||||
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 35 | config ARM_GIC_V3 |
36 | bool | ||||
37 | select IRQ_DOMAIN | ||||
38 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 39 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 40 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 41 | select PARTITION_PERCPU |
Marc Zyngier | 956ae91 | 2017-08-18 09:39:17 +0100 | [diff] [blame] | 42 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 43 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 44 | config ARM_GIC_V3_ITS |
45 | bool | ||||
Marc Zyngier | 29f4113 | 2017-11-13 17:25:59 +0000 | [diff] [blame] | 46 | select GENERIC_MSI_IRQ_DOMAIN |
47 | default ARM_GIC_V3 | ||||
48 | |||||
49 | config ARM_GIC_V3_ITS_PCI | ||||
50 | bool | ||||
51 | depends on ARM_GIC_V3_ITS | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 52 | depends on PCI |
53 | depends on PCI_MSI | ||||
Marc Zyngier | 29f4113 | 2017-11-13 17:25:59 +0000 | [diff] [blame] | 54 | default ARM_GIC_V3_ITS |
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 55 | |
Bogdan Purcareata | 7afe031 | 2018-02-05 08:07:43 -0600 | [diff] [blame] | 56 | config ARM_GIC_V3_ITS_FSL_MC |
57 | bool | ||||
58 | depends on ARM_GIC_V3_ITS | ||||
59 | depends on FSL_MC_BUS | ||||
60 | default ARM_GIC_V3_ITS | ||||
61 | |||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 62 | config ARM_NVIC |
63 | bool | ||||
64 | select IRQ_DOMAIN | ||||
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 65 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 66 | select GENERIC_IRQ_CHIP |
67 | |||||
68 | config ARM_VIC | ||||
69 | bool | ||||
70 | select IRQ_DOMAIN | ||||
71 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 72 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 73 | |
74 | config ARM_VIC_NR | ||||
75 | int | ||||
76 | default 4 if ARCH_S5PV210 | ||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 77 | default 2 |
78 | depends on ARM_VIC | ||||
79 | help | ||||
80 | The maximum number of VICs available in the system, for | ||||
81 | power management. | ||||
82 | |||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 83 | config ARMADA_370_XP_IRQ |
84 | bool | ||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 85 | select GENERIC_IRQ_CHIP |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 86 | select PCI_MSI if PCI |
Marc Zyngier | e31793a | 2017-08-18 09:39:19 +0100 | [diff] [blame] | 87 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 88 | |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 89 | config ALPINE_MSI |
90 | bool | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 91 | depends on PCI |
92 | select PCI_MSI | ||||
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 93 | select GENERIC_IRQ_CHIP |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 94 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 95 | config ATMEL_AIC_IRQ |
96 | bool | ||||
97 | select GENERIC_IRQ_CHIP | ||||
98 | select IRQ_DOMAIN | ||||
99 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 100 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 101 | select SPARSE_IRQ |
102 | |||||
103 | config ATMEL_AIC5_IRQ | ||||
104 | bool | ||||
105 | select GENERIC_IRQ_CHIP | ||||
106 | select IRQ_DOMAIN | ||||
107 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 108 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 109 | select SPARSE_IRQ |
110 | |||||
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 111 | config I8259 |
112 | bool | ||||
113 | select IRQ_DOMAIN | ||||
114 | |||||
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 115 | config BCM6345_L1_IRQ |
116 | bool | ||||
117 | select GENERIC_IRQ_CHIP | ||||
118 | select IRQ_DOMAIN | ||||
Marc Zyngier | d0ed5e8 | 2017-08-18 09:39:20 +0100 | [diff] [blame] | 119 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 120 | |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 121 | config BCM7038_L1_IRQ |
122 | bool | ||||
123 | select GENERIC_IRQ_CHIP | ||||
124 | select IRQ_DOMAIN | ||||
Marc Zyngier | b8d9884 | 2017-08-18 09:39:21 +0100 | [diff] [blame] | 125 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 126 | |
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 127 | config BCM7120_L2_IRQ |
128 | bool | ||||
129 | select GENERIC_IRQ_CHIP | ||||
130 | select IRQ_DOMAIN | ||||
131 | |||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 132 | config BRCMSTB_L2_IRQ |
133 | bool | ||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 134 | select GENERIC_IRQ_CHIP |
135 | select IRQ_DOMAIN | ||||
136 | |||||
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 137 | config DW_APB_ICTL |
138 | bool | ||||
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 139 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 140 | select IRQ_DOMAIN |
141 | |||||
Linus Walleij | 6ee532e | 2017-03-18 17:53:24 +0100 | [diff] [blame] | 142 | config FARADAY_FTINTC010 |
143 | bool | ||||
144 | select IRQ_DOMAIN | ||||
145 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 146 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Linus Walleij | 6ee532e | 2017-03-18 17:53:24 +0100 | [diff] [blame] | 147 | select SPARSE_IRQ |
148 | |||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 149 | config HISILICON_IRQ_MBIGEN |
150 | bool | ||||
151 | select ARM_GIC_V3 | ||||
152 | select ARM_GIC_V3_ITS | ||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 153 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 154 | config IMGPDC_IRQ |
155 | bool | ||||
156 | select GENERIC_IRQ_CHIP | ||||
157 | select IRQ_DOMAIN | ||||
158 | |||||
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 159 | config IRQ_MIPS_CPU |
160 | bool | ||||
161 | select GENERIC_IRQ_CHIP | ||||
Paul Burton | 3838a54 | 2017-03-30 12:06:11 -0700 | [diff] [blame] | 162 | select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 163 | select IRQ_DOMAIN |
Paul Burton | 3838a54 | 2017-03-30 12:06:11 -0700 | [diff] [blame] | 164 | select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI |
Marc Zyngier | 18416e4 | 2017-08-18 09:39:24 +0100 | [diff] [blame] | 165 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 166 | |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 167 | config CLPS711X_IRQCHIP |
168 | bool | ||||
169 | depends on ARCH_CLPS711X | ||||
170 | select IRQ_DOMAIN | ||||
171 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 172 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 173 | select SPARSE_IRQ |
174 | default y | ||||
175 | |||||
Stafford Horne | 9b54470 | 2017-10-30 21:38:35 +0900 | [diff] [blame] | 176 | config OMPIC |
177 | bool | ||||
178 | |||||
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 179 | config OR1K_PIC |
180 | bool | ||||
181 | select IRQ_DOMAIN | ||||
182 | |||||
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 183 | config OMAP_IRQCHIP |
184 | bool | ||||
185 | select GENERIC_IRQ_CHIP | ||||
186 | select IRQ_DOMAIN | ||||
187 | |||||
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 188 | config ORION_IRQCHIP |
189 | bool | ||||
190 | select IRQ_DOMAIN | ||||
191 | select MULTI_IRQ_HANDLER | ||||
Palmer Dabbelt | 08fb550 | 2018-06-22 10:01:22 -0700 | [diff] [blame] | 192 | select GENERIC_IRQ_MULTI_HANDLER if !MULTI_IRQ_HANDLER |
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 193 | |
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 194 | config PIC32_EVIC |
195 | bool | ||||
196 | select GENERIC_IRQ_CHIP | ||||
197 | select IRQ_DOMAIN | ||||
198 | |||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 199 | config JCORE_AIC |
Rich Felker | 3602ffd | 2016-10-19 17:53:52 +0000 | [diff] [blame] | 200 | bool "J-Core integrated AIC" if COMPILE_TEST |
201 | depends on OF | ||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 202 | select IRQ_DOMAIN |
203 | help | ||||
204 | Support for the J-Core integrated AIC. | ||||
205 | |||||
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 206 | config RENESAS_INTC_IRQPIN |
207 | bool | ||||
208 | select IRQ_DOMAIN | ||||
209 | |||||
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 210 | config RENESAS_IRQC |
211 | bool | ||||
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 212 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 213 | select IRQ_DOMAIN |
214 | |||||
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 215 | config ST_IRQCHIP |
216 | bool | ||||
217 | select REGMAP | ||||
218 | select MFD_SYSCON | ||||
219 | help | ||||
220 | Enables SysCfg Controlled IRQs on STi based platforms. | ||||
221 | |||||
Mans Rullgard | 4bba668 | 2016-01-20 18:07:17 +0000 | [diff] [blame] | 222 | config TANGO_IRQ |
223 | bool | ||||
224 | select IRQ_DOMAIN | ||||
225 | select GENERIC_IRQ_CHIP | ||||
226 | |||||
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 227 | config TB10X_IRQC |
228 | bool | ||||
229 | select IRQ_DOMAIN | ||||
230 | select GENERIC_IRQ_CHIP | ||||
231 | |||||
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 232 | config TS4800_IRQ |
233 | tristate "TS-4800 IRQ controller" | ||||
234 | select IRQ_DOMAIN | ||||
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 235 | depends on HAS_IOMEM |
Jean Delvare | d2b383d | 2016-02-09 11:19:20 +0100 | [diff] [blame] | 236 | depends on SOC_IMX51 || COMPILE_TEST |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 237 | help |
238 | Support for the TS-4800 FPGA IRQ controller | ||||
239 | |||||
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 240 | config VERSATILE_FPGA_IRQ |
241 | bool | ||||
242 | select IRQ_DOMAIN | ||||
243 | |||||
244 | config VERSATILE_FPGA_IRQ_NR | ||||
245 | int | ||||
246 | default 4 | ||||
247 | depends on VERSATILE_FPGA_IRQ | ||||
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 248 | |
249 | config XTENSA_MX | ||||
250 | bool | ||||
251 | select IRQ_DOMAIN | ||||
Marc Zyngier | 5009121 | 2017-08-18 09:39:25 +0100 | [diff] [blame] | 252 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 253 | |
Zubair Lutfullah Kakakhel | 0547dc7 | 2016-11-14 12:13:45 +0000 | [diff] [blame] | 254 | config XILINX_INTC |
255 | bool | ||||
256 | select IRQ_DOMAIN | ||||
257 | |||||
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 258 | config IRQ_CROSSBAR |
259 | bool | ||||
260 | help | ||||
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 261 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 262 | The primary irqchip invokes the crossbar's callback which inturn allocates |
263 | a free irq and configures the IP. Thus the peripheral interrupts are | ||||
264 | routed to one of the free irqchip interrupt lines. | ||||
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 265 | |
266 | config KEYSTONE_IRQ | ||||
267 | tristate "Keystone 2 IRQ controller IP" | ||||
268 | depends on ARCH_KEYSTONE | ||||
269 | help | ||||
270 | Support for Texas Instruments Keystone 2 IRQ controller IP which | ||||
271 | is part of the Keystone 2 IPC mechanism | ||||
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 272 | |
273 | config MIPS_GIC | ||||
274 | bool | ||||
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 275 | select GENERIC_IRQ_IPI |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 276 | select IRQ_DOMAIN_HIERARCHY |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 277 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 278 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 279 | config INGENIC_IRQ |
280 | bool | ||||
281 | depends on MACH_INGENIC | ||||
282 | default y | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 283 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 284 | config RENESAS_H8300H_INTC |
285 | bool | ||||
286 | select IRQ_DOMAIN | ||||
287 | |||||
288 | config RENESAS_H8S_INTC | ||||
289 | bool | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 290 | select IRQ_DOMAIN |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 291 | |
292 | config IMX_GPCV2 | ||||
293 | bool | ||||
294 | select IRQ_DOMAIN | ||||
295 | help | ||||
296 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | ||||
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 297 | |
298 | config IRQ_MXS | ||||
299 | def_bool y if MACH_ASM9260 || ARCH_MXS | ||||
300 | select IRQ_DOMAIN | ||||
301 | select STMP_DEVICE | ||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 302 | |
Alexandre Belloni | 19d9916 | 2018-03-22 16:15:24 +0100 | [diff] [blame] | 303 | config MSCC_OCELOT_IRQ |
304 | bool | ||||
305 | select IRQ_DOMAIN | ||||
306 | select GENERIC_IRQ_CHIP | ||||
307 | |||||
Thomas Petazzoni | a68a63c | 2017-06-21 15:29:14 +0200 | [diff] [blame] | 308 | config MVEBU_GICP |
309 | bool | ||||
310 | |||||
Thomas Petazzoni | e0de91a | 2017-06-21 15:29:15 +0200 | [diff] [blame] | 311 | config MVEBU_ICU |
312 | bool | ||||
313 | |||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 314 | config MVEBU_ODMI |
315 | bool | ||||
Arnd Bergmann | fa23b9d | 2017-03-14 13:54:12 +0100 | [diff] [blame] | 316 | select GENERIC_MSI_IRQ_DOMAIN |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 317 | |
Thomas Petazzoni | a109893 | 2016-08-05 16:55:19 +0200 | [diff] [blame] | 318 | config MVEBU_PIC |
319 | bool | ||||
320 | |||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 321 | config LS_SCFG_MSI |
322 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | ||||
323 | depends on PCI && PCI_MSI | ||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 324 | |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 325 | config PARTITION_PERCPU |
326 | bool | ||||
Linus Torvalds | 0efacbb | 2016-05-19 09:46:18 -0700 | [diff] [blame] | 327 | |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 328 | config EZNPS_GIC |
329 | bool "NPS400 Global Interrupt Manager (GIM)" | ||||
Arnd Bergmann | ffd565e | 2016-05-12 23:03:35 +0200 | [diff] [blame] | 330 | depends on ARC || (COMPILE_TEST && !64BIT) |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 331 | select IRQ_DOMAIN |
332 | help | ||||
333 | Support the EZchip NPS400 global interrupt controller | ||||
Alexandre TORGUE | e0720416 | 2016-09-20 18:00:57 +0200 | [diff] [blame] | 334 | |
335 | config STM32_EXTI | ||||
336 | bool | ||||
337 | select IRQ_DOMAIN | ||||
Ludovic Barre | 0e7d780 | 2017-11-06 18:03:31 +0100 | [diff] [blame] | 338 | select GENERIC_IRQ_CHIP |
Agustin Vega-Frias | f20cc9b | 2017-02-02 18:23:59 -0500 | [diff] [blame] | 339 | |
340 | config QCOM_IRQ_COMBINER | ||||
341 | bool "QCOM IRQ combiner support" | ||||
342 | depends on ARCH_QCOM && ACPI | ||||
343 | select IRQ_DOMAIN | ||||
344 | select IRQ_DOMAIN_HIERARCHY | ||||
345 | help | ||||
346 | Say yes here to add support for the IRQ combiner devices embedded | ||||
347 | in Qualcomm Technologies chips. | ||||
Masahiro Yamada | 5ed34d3a | 2017-08-23 10:31:47 +0900 | [diff] [blame] | 348 | |
349 | config IRQ_UNIPHIER_AIDET | ||||
350 | bool "UniPhier AIDET support" if COMPILE_TEST | ||||
351 | depends on ARCH_UNIPHIER || COMPILE_TEST | ||||
352 | default ARCH_UNIPHIER | ||||
353 | select IRQ_DOMAIN_HIERARCHY | ||||
354 | help | ||||
355 | Support for the UniPhier AIDET (ARM Interrupt Detector). | ||||
Randy Dunlap | c94fb63 | 2017-10-16 11:04:33 -0700 | [diff] [blame] | 356 | |
Jerome Brunet | 215f4cc | 2017-09-18 15:46:10 +0200 | [diff] [blame] | 357 | config MESON_IRQ_GPIO |
358 | bool "Meson GPIO Interrupt Multiplexer" | ||||
Thomas Gleixner | d9ee91c | 2017-10-20 11:15:36 +0200 | [diff] [blame] | 359 | depends on ARCH_MESON |
Jerome Brunet | 215f4cc | 2017-09-18 15:46:10 +0200 | [diff] [blame] | 360 | select IRQ_DOMAIN |
361 | select IRQ_DOMAIN_HIERARCHY | ||||
362 | help | ||||
363 | Support Meson SoC Family GPIO Interrupt Multiplexer | ||||
364 | |||||
Miodrag Dinic | 4235ff5 | 2017-12-29 16:41:46 +0100 | [diff] [blame] | 365 | config GOLDFISH_PIC |
366 | bool "Goldfish programmable interrupt controller" | ||||
367 | depends on MIPS && (GOLDFISH || COMPILE_TEST) | ||||
368 | select IRQ_DOMAIN | ||||
369 | help | ||||
370 | Say yes here to enable Goldfish interrupt controller driver used | ||||
371 | for Goldfish based virtual platforms. | ||||
372 | |||||
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 373 | config QCOM_PDC |
374 | bool "QCOM PDC" | ||||
375 | depends on ARCH_QCOM | ||||
376 | select IRQ_DOMAIN | ||||
377 | select IRQ_DOMAIN_HIERARCHY | ||||
378 | help | ||||
379 | Power Domain Controller driver to manage and configure wakeup | ||||
380 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. | ||||
381 | |||||
Randy Dunlap | c94fb63 | 2017-10-16 11:04:33 -0700 | [diff] [blame] | 382 | endmenu |