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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000028#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000029#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capperc2c93e52014-01-15 14:07:13 +000031#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000032#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
36 */
Catalin Marinas847264fb2013-10-23 16:50:07 +010037#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000038#define VMALLOC_END (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
39
40#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
41
42#define FIRST_USER_ADDRESS 0
43
44#ifndef __ASSEMBLY__
45extern void __pte_error(const char *file, int line, unsigned long val);
46extern void __pmd_error(const char *file, int line, unsigned long val);
47extern void __pgd_error(const char *file, int line, unsigned long val);
48
49#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
50#ifndef CONFIG_ARM64_64K_PAGES
51#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
52#endif
53#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
54
55/*
56 * The pgprot_* and protection_map entries will be fixed up at runtime to
57 * include the cachable and bufferable bits based on memory policy, as well as
58 * any architecture dependent bits like global/ASID and SMP shared mapping
59 * bits.
60 */
61#define _PAGE_DEFAULT PTE_TYPE_PAGE | PTE_AF
62
63extern pgprot_t pgprot_default;
64
Will Deacona6fadf72012-12-18 14:15:15 +000065#define __pgprot_modify(prot,mask,bits) \
66 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000067
Will Deacona6fadf72012-12-18 14:15:15 +000068#define _MOD_PROT(p, b) __pgprot_modify(p, 0, b)
69
Steve Capperc2c93e52014-01-15 14:07:13 +000070#define PAGE_NONE __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_PXN | PTE_UXN)
71#define PAGE_SHARED _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
72#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
73#define PAGE_COPY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
74#define PAGE_COPY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
75#define PAGE_READONLY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
76#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
77#define PAGE_KERNEL _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
78#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000079
Marc Zyngier36311602012-12-07 18:35:41 +000080#define PAGE_HYP _MOD_PROT(pgprot_default, PTE_HYP)
81#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
82
83#define PAGE_S2 __pgprot_modify(pgprot_default, PTE_S2_MEMATTR_MASK, PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
84#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
85
Steve Capperc2c93e52014-01-15 14:07:13 +000086#define __PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
87#define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
88#define __PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
89#define __PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
90#define __PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
91#define __PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
92#define __PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000093
94#endif /* __ASSEMBLY__ */
95
96#define __P000 __PAGE_NONE
97#define __P001 __PAGE_READONLY
98#define __P010 __PAGE_COPY
99#define __P011 __PAGE_COPY
100#define __P100 __PAGE_READONLY_EXEC
101#define __P101 __PAGE_READONLY_EXEC
102#define __P110 __PAGE_COPY_EXEC
103#define __P111 __PAGE_COPY_EXEC
104
105#define __S000 __PAGE_NONE
106#define __S001 __PAGE_READONLY
107#define __S010 __PAGE_SHARED
108#define __S011 __PAGE_SHARED
109#define __S100 __PAGE_READONLY_EXEC
110#define __S101 __PAGE_READONLY_EXEC
111#define __S110 __PAGE_SHARED_EXEC
112#define __S111 __PAGE_SHARED_EXEC
113
114#ifndef __ASSEMBLY__
115/*
116 * ZERO_PAGE is a global shared page that is always zero: used
117 * for zero-mapped memory areas etc..
118 */
119extern struct page *empty_zero_page;
120#define ZERO_PAGE(vaddr) (empty_zero_page)
121
122#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
123
124#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
125
126#define pte_none(pte) (!pte_val(pte))
127#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
128#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Will Deacon9ab6d022013-06-10 19:34:41 +0100129#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000130
131#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
132#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
133#define pte_unmap(pte) do { } while (0)
134#define pte_unmap_nested(pte) do { } while (0)
135
136/*
137 * The following only work if pte_present(). Undefined behaviour otherwise.
138 */
Steve Capper84fe6822014-02-25 11:38:53 +0000139#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
140#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
141#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
142#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
143#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000144#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000145
Will Deacona6fadf72012-12-18 14:15:15 +0000146#define pte_valid_user(pte) \
Will Deacon02522462013-01-09 11:08:10 +0000147 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000148
Steve Capper44b6dfc2014-01-15 14:07:12 +0000149static inline pte_t pte_wrprotect(pte_t pte)
150{
Steve Capperc2c93e52014-01-15 14:07:13 +0000151 pte_val(pte) &= ~PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000152 return pte;
153}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000154
Steve Capper44b6dfc2014-01-15 14:07:12 +0000155static inline pte_t pte_mkwrite(pte_t pte)
156{
Steve Capperc2c93e52014-01-15 14:07:13 +0000157 pte_val(pte) |= PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000158 return pte;
159}
160
161static inline pte_t pte_mkclean(pte_t pte)
162{
163 pte_val(pte) &= ~PTE_DIRTY;
164 return pte;
165}
166
167static inline pte_t pte_mkdirty(pte_t pte)
168{
169 pte_val(pte) |= PTE_DIRTY;
170 return pte;
171}
172
173static inline pte_t pte_mkold(pte_t pte)
174{
175 pte_val(pte) &= ~PTE_AF;
176 return pte;
177}
178
179static inline pte_t pte_mkyoung(pte_t pte)
180{
181 pte_val(pte) |= PTE_AF;
182 return pte;
183}
184
185static inline pte_t pte_mkspecial(pte_t pte)
186{
187 pte_val(pte) |= PTE_SPECIAL;
188 return pte;
189}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000190
191static inline void set_pte(pte_t *ptep, pte_t pte)
192{
193 *ptep = pte;
194}
195
196extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
197
198static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
199 pte_t *ptep, pte_t pte)
200{
Will Deacona6fadf72012-12-18 14:15:15 +0000201 if (pte_valid_user(pte)) {
Catalin Marinas71fdb6bf2014-03-12 16:28:09 +0000202 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000203 __sync_icache_dcache(pte, addr);
Steve Capperc2c93e52014-01-15 14:07:13 +0000204 if (pte_dirty(pte) && pte_write(pte))
205 pte_val(pte) &= ~PTE_RDONLY;
206 else
207 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000208 }
209
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000210 set_pte(ptep, pte);
211}
212
213/*
214 * Huge pte definitions.
215 */
Steve Capper084bd292013-04-10 13:48:00 +0100216#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
217#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
218
219/*
220 * Hugetlb definitions.
221 */
222#define HUGE_MAX_HSTATE 2
223#define HPAGE_SHIFT PMD_SHIFT
224#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
225#define HPAGE_MASK (~(HPAGE_SIZE - 1))
226#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000227
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000228#define __HAVE_ARCH_PTE_SPECIAL
229
Steve Capper9c7e5352014-02-25 10:02:13 +0000230static inline pte_t pmd_pte(pmd_t pmd)
231{
232 return __pte(pmd_val(pmd));
233}
Steve Capperaf074842013-04-19 16:23:57 +0100234
Steve Capper9c7e5352014-02-25 10:02:13 +0000235static inline pmd_t pte_pmd(pte_t pte)
236{
237 return __pmd(pte_val(pte));
238}
Steve Capperaf074842013-04-19 16:23:57 +0100239
240/*
241 * THP definitions.
242 */
Steve Capperaf074842013-04-19 16:23:57 +0100243
244#ifdef CONFIG_TRANSPARENT_HUGEPAGE
245#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
Steve Capper9c7e5352014-02-25 10:02:13 +0000246#define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100247#endif
248
Steve Capper9c7e5352014-02-25 10:02:13 +0000249#define pmd_young(pmd) pte_young(pmd_pte(pmd))
250#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
251#define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd)))
252#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
253#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
254#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
255#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
256#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) &= ~PMD_TYPE_MASK))
Steve Capperaf074842013-04-19 16:23:57 +0100257
Steve Capper9c7e5352014-02-25 10:02:13 +0000258#define __HAVE_ARCH_PMD_WRITE
259#define pmd_write(pmd) pte_write(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100260
261#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
262
263#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
264#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
265#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
266
267#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
268
Steve Capperaf074842013-04-19 16:23:57 +0100269#define set_pmd_at(mm, addr, pmdp, pmd) set_pmd(pmdp, pmd)
270
271static inline int has_transparent_hugepage(void)
272{
273 return 1;
274}
275
276/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000277 * Mark the prot value as uncacheable and unbufferable.
278 */
279#define pgprot_noncached(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000280 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000281#define pgprot_writecombine(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000282 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000283#define __HAVE_PHYS_MEM_ACCESS_PROT
284struct file;
285extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
286 unsigned long size, pgprot_t vma_prot);
287
288#define pmd_none(pmd) (!pmd_val(pmd))
289#define pmd_present(pmd) (pmd_val(pmd))
290
291#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
292
Marc Zyngier36311602012-12-07 18:35:41 +0000293#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
294 PMD_TYPE_TABLE)
295#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
296 PMD_TYPE_SECT)
297
298
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000299static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
300{
301 *pmdp = pmd;
302 dsb();
303}
304
305static inline void pmd_clear(pmd_t *pmdp)
306{
307 set_pmd(pmdp, __pmd(0));
308}
309
310static inline pte_t *pmd_page_vaddr(pmd_t pmd)
311{
312 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
313}
314
315#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
316
317/*
318 * Conversion functions: convert a page and protection to a page entry,
319 * and a page entry and page directory to the page they refer to.
320 */
321#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
322
323#ifndef CONFIG_ARM64_64K_PAGES
324
325#define pud_none(pud) (!pud_val(pud))
326#define pud_bad(pud) (!(pud_val(pud) & 2))
327#define pud_present(pud) (pud_val(pud))
328
329static inline void set_pud(pud_t *pudp, pud_t pud)
330{
331 *pudp = pud;
332 dsb();
333}
334
335static inline void pud_clear(pud_t *pudp)
336{
337 set_pud(pudp, __pud(0));
338}
339
340static inline pmd_t *pud_page_vaddr(pud_t pud)
341{
342 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
343}
344
345#endif /* CONFIG_ARM64_64K_PAGES */
346
347/* to find an entry in a page-table-directory */
348#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
349
350#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
351
352/* to find an entry in a kernel page-table-directory */
353#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
354
355/* Find an entry in the second-level page table.. */
356#ifndef CONFIG_ARM64_64K_PAGES
357#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
358static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
359{
360 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
361}
362#endif
363
364/* Find an entry in the third-level page table.. */
Will Deacon9ab6d022013-06-10 19:34:41 +0100365#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000366
367static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
368{
Will Deacona6fadf72012-12-18 14:15:15 +0000369 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Steve Capperc2c93e52014-01-15 14:07:13 +0000370 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000371 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
372 return pte;
373}
374
Steve Capper9c7e5352014-02-25 10:02:13 +0000375static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
376{
377 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
378}
379
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000380extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
381extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
382
383#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
384#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
385
386/*
387 * Encode and decode a swap entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000388 * bits 0-1: present (must be zero)
389 * bit 2: PTE_FILE
390 * bits 3-8: swap type
391 * bits 9-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000392 */
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000393#define __SWP_TYPE_SHIFT 3
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000394#define __SWP_TYPE_BITS 6
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000395#define __SWP_OFFSET_BITS 49
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000396#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
397#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000398#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000399
400#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000401#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000402#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
403
404#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
405#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
406
407/*
408 * Ensure that there are not more swap files than can be encoded in the kernel
409 * the PTEs.
410 */
411#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
412
413/*
414 * Encode and decode a file entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000415 * bits 0-1: present (must be zero)
416 * bit 2: PTE_FILE
417 * bits 3-57: file offset / PAGE_SIZE
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000418 */
419#define pte_file(pte) (pte_val(pte) & PTE_FILE)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000420#define pte_to_pgoff(x) (pte_val(x) >> 3)
421#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000422
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000423#define PTE_FILE_MAX_BITS 55
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000424
425extern int kern_addr_valid(unsigned long addr);
426
427#include <asm-generic/pgtable.h>
428
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000429#define pgtable_cache_init() do { } while (0)
430
431#endif /* !__ASSEMBLY__ */
432
433#endif /* __ASM_PGTABLE_H */