blob: 9d0c86711de21b171bf2d0492040941310550c4d [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Stephen Warrena7db2c12011-10-25 02:01:28 +00002/dts-v1/;
3
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05304#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06005#include "tegra20.dtsi"
Dmitry Osipenkoc19c6312019-10-25 01:14:14 +03006#include "tegra20-cpu-opp.dtsi"
Stephen Warrena7db2c12011-10-25 02:01:28 +00007
8/ {
9 model = "Compulab TrimSlice board";
10 compatible = "compulab,trimslice", "nvidia,tegra20";
11
Stephen Warren553c0a22013-12-09 14:43:59 -070012 aliases {
13 rtc0 = "/i2c@7000c500/rtc@56";
14 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080015 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070016 };
17
Jon Hunterf5bbb322016-02-09 13:51:59 +000018 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21
Krzysztof Kozlowski48299762018-07-09 18:05:17 +020022 memory@0 {
Stephen Warren95decf82012-05-11 16:11:38 -060023 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000024 };
25
Stephen Warren58ecb232013-11-25 17:53:16 -070026 host1x@50000000 {
27 hdmi@54280000 {
Thierry Redingdced3e32012-09-20 10:39:20 +020028 status = "okay";
29
30 vdd-supply = <&hdmi_vdd_reg>;
31 pll-supply = <&hdmi_pll_reg>;
32
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070034 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
35 GPIO_ACTIVE_HIGH>;
Thierry Redingdced3e32012-09-20 10:39:20 +020036 };
37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -070039 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060040 pinctrl-names = "default";
41 pinctrl-0 = <&state_default>;
42
43 state_default: pinmux {
44 ata {
45 nvidia,pins = "ata";
46 nvidia,function = "ide";
47 };
48 atb {
49 nvidia,pins = "atb", "gma";
50 nvidia,function = "sdio4";
51 };
52 atc {
53 nvidia,pins = "atc", "gmb";
54 nvidia,function = "nand";
55 };
56 atd {
57 nvidia,pins = "atd", "ate", "gme", "pta";
58 nvidia,function = "gmi";
59 };
60 cdev1 {
61 nvidia,pins = "cdev1";
62 nvidia,function = "plla_out";
63 };
64 cdev2 {
65 nvidia,pins = "cdev2";
66 nvidia,function = "pllp_out4";
67 };
68 crtp {
69 nvidia,pins = "crtp";
70 nvidia,function = "crt";
71 };
72 csus {
73 nvidia,pins = "csus";
74 nvidia,function = "vi_sensor_clk";
75 };
76 dap1 {
77 nvidia,pins = "dap1";
78 nvidia,function = "dap1";
79 };
80 dap2 {
81 nvidia,pins = "dap2";
82 nvidia,function = "dap2";
83 };
84 dap3 {
85 nvidia,pins = "dap3";
86 nvidia,function = "dap3";
87 };
88 dap4 {
89 nvidia,pins = "dap4";
90 nvidia,function = "dap4";
91 };
92 ddc {
93 nvidia,pins = "ddc";
94 nvidia,function = "i2c2";
95 };
96 dta {
97 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
98 nvidia,function = "vi";
99 };
100 dtf {
101 nvidia,pins = "dtf";
102 nvidia,function = "i2c3";
103 };
104 gmc {
105 nvidia,pins = "gmc", "gmd";
106 nvidia,function = "sflash";
107 };
108 gpu {
109 nvidia,pins = "gpu";
110 nvidia,function = "uarta";
111 };
112 gpu7 {
113 nvidia,pins = "gpu7";
114 nvidia,function = "rtck";
115 };
116 gpv {
117 nvidia,pins = "gpv", "slxa", "slxk";
118 nvidia,function = "pcie";
119 };
120 hdint {
121 nvidia,pins = "hdint";
122 nvidia,function = "hdmi";
123 };
124 i2cp {
125 nvidia,pins = "i2cp";
126 nvidia,function = "i2cp";
127 };
128 irrx {
129 nvidia,pins = "irrx", "irtx";
130 nvidia,function = "uartb";
131 };
132 kbca {
133 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
134 "kbce", "kbcf";
135 nvidia,function = "kbc";
136 };
137 lcsn {
138 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
139 "ld3", "ld4", "ld5", "ld6", "ld7",
140 "ld8", "ld9", "ld10", "ld11", "ld12",
141 "ld13", "ld14", "ld15", "ld16", "ld17",
142 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
143 "lhs", "lm0", "lm1", "lpp", "lpw0",
144 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
145 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
146 "lvs";
147 nvidia,function = "displaya";
148 };
149 owc {
150 nvidia,pins = "owc", "uac";
151 nvidia,function = "rsvd2";
152 };
153 pmc {
154 nvidia,pins = "pmc";
155 nvidia,function = "pwr_on";
156 };
157 rm {
158 nvidia,pins = "rm";
159 nvidia,function = "i2c1";
160 };
161 sdb {
162 nvidia,pins = "sdb", "sdc", "sdd";
163 nvidia,function = "pwm";
164 };
165 sdio1 {
166 nvidia,pins = "sdio1";
167 nvidia,function = "sdio1";
168 };
169 slxc {
170 nvidia,pins = "slxc", "slxd";
171 nvidia,function = "sdio3";
172 };
173 spdi {
174 nvidia,pins = "spdi", "spdo";
175 nvidia,function = "spdif";
176 };
177 spia {
178 nvidia,pins = "spia", "spib", "spic";
179 nvidia,function = "spi2";
180 };
181 spid {
182 nvidia,pins = "spid", "spie", "spif";
183 nvidia,function = "spi1";
184 };
185 spig {
186 nvidia,pins = "spig", "spih";
187 nvidia,function = "spi2_alt";
188 };
189 uaa {
190 nvidia,pins = "uaa", "uab", "uda";
191 nvidia,function = "ulpi";
192 };
193 uad {
194 nvidia,pins = "uad";
195 nvidia,function = "irda";
196 };
197 uca {
198 nvidia,pins = "uca", "ucb";
199 nvidia,function = "uartc";
200 };
201 conf_ata {
202 nvidia,pins = "ata", "atc", "atd", "ate",
203 "crtp", "dap2", "dap3", "dap4", "dta",
204 "dtb", "dtc", "dtd", "dte", "gmb",
205 "gme", "i2cp", "pta", "slxc", "slxd",
206 "spdi", "spdo", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600209 };
210 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600211 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
212 "gma", "gmc", "gmd", "gpu", "gpu7",
213 "gpv", "sdio1", "slxa", "slxk", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600216 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600217 conf_ck32 {
218 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
219 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600221 };
Stephen Warren563da212012-04-13 16:35:20 -0600222 conf_csus {
223 nvidia,pins = "csus", "spia", "spib",
224 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530225 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600227 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600228 conf_ddc {
229 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530230 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600232 };
233 conf_hdint {
234 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
235 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
236 "lvp0", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530237 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600238 };
239 conf_irrx {
240 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
241 "kbcc", "kbcd", "kbce", "kbcf", "owc",
242 "spic", "spie", "spig", "spih", "uaa",
243 "uab", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600246 };
247 conf_lc {
248 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530249 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600250 };
251 conf_ld0 {
252 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
253 "ld5", "ld6", "ld7", "ld8", "ld9",
254 "ld10", "ld11", "ld12", "ld13", "ld14",
255 "ld15", "ld16", "ld17", "ldi", "lhp0",
256 "lhp1", "lhp2", "lhs", "lm0", "lpp",
257 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
258 "lvs", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530259 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600260 };
261 conf_ld17_0 {
262 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
263 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530264 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600265 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700266 conf_spif {
267 nvidia,pins = "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530268 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700270 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600271 };
272 };
273
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600274 i2s@70002800 {
275 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600276 };
277
278 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600279 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600280 };
281
Thierry Redingdced3e32012-09-20 10:39:20 +0200282 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600283 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200284 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000285 };
286
Stephen Warrenfea221e2012-11-12 12:51:22 -0700287 spi@7000c380 {
288 status = "okay";
289 spi-max-frequency = <48000000>;
Thierry Reding0b9f3942021-12-06 17:19:28 +0100290
291 flash@0 {
Rafał Miłeckide45b782015-08-16 08:13:25 +0200292 compatible = "winbond,w25q80bl", "jedec,spi-nor";
Stephen Warrenfea221e2012-11-12 12:51:22 -0700293 reg = <0>;
294 spi-max-frequency = <48000000>;
295 };
296 };
297
Thierry Redingdced3e32012-09-20 10:39:20 +0200298 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600299 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200300 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000301 };
302
303 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600304 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000305 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600306
Stephen Warren22bfe102012-04-27 13:24:03 -0600307 codec: codec@1a {
308 compatible = "ti,tlv320aic23";
309 reg = <0x1a>;
310 };
311
Stephen Warren081cc0a2012-04-27 09:22:44 -0600312 rtc@56 {
313 compatible = "emmicro,em3027";
314 reg = <0x56>;
315 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000316 };
317
Stephen Warren58ecb232013-11-25 17:53:16 -0700318 pmc@7000e400 {
Joseph Lo47d2d632013-08-12 17:40:07 +0800319 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800320 nvidia,cpu-pwr-good-time = <5000>;
321 nvidia,cpu-pwr-off-time = <5000>;
322 nvidia,core-pwr-good-time = <3845 3845>;
323 nvidia,core-pwr-off-time = <3875>;
324 nvidia,sys-clock-req-active-high;
Dmitry Osipenko83b7f0b2021-12-01 02:23:43 +0300325 core-supply = <&vdd_core>;
Joseph Loa44a0192013-04-03 19:31:52 +0800326 };
327
Rob Herring508d6902017-03-21 21:03:06 -0500328 pcie@80003000 {
Thierry Reding1798efd2013-08-09 16:49:23 +0200329 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200330
331 avdd-pex-supply = <&pci_vdd_reg>;
332 vdd-pex-supply = <&pci_vdd_reg>;
333 avdd-pex-pll-supply = <&pci_vdd_reg>;
334 avdd-plle-supply = <&pci_vdd_reg>;
335 vddio-pex-clk-supply = <&pci_clk_reg>;
336
Thierry Reding1798efd2013-08-09 16:49:23 +0200337 pci@1,0 {
338 status = "okay";
339 };
340 };
341
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600342 usb@c5000000 {
343 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700344 };
345
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530346 usb-phy@c5000000 {
347 status = "okay";
348 vbus-supply = <&vbus_reg>;
349 };
350
Stephen Warrenc04abb32012-05-11 17:03:26 -0600351 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600352 status = "okay";
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530353 };
354
355 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530356 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700357 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
358 GPIO_ACTIVE_LOW>;
Stephen Warren31c1ec92011-11-21 14:44:10 -0700359 };
360
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600361 usb@c5008000 {
362 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700363 };
364
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530365 usb-phy@c5008000 {
366 status = "okay";
367 };
368
Thierry Reding32c096c2020-06-11 19:21:17 +0200369 mmc@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600370 status = "okay";
Rask Ingemann Lambertsena3e48632017-01-22 22:17:48 +0100371 broken-cd;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200372 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700373 };
374
Thierry Reding32c096c2020-06-11 19:21:17 +0200375 mmc@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600376 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700377 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
378 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200379 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000380 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600381
David Heidelberg4f74ed82021-12-12 00:14:03 +0300382 clk32k_in: clock-32k {
Thierry Reding901c8652020-06-11 19:00:14 +0200383 compatible = "fixed-clock";
384 clock-frequency = <32768>;
385 #clock-cells = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800386 };
387
Joseph Lo5741a252013-04-03 19:31:48 +0800388 gpio-keys {
389 compatible = "gpio-keys";
390
391 power {
392 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700393 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530394 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000395 wakeup-source;
Joseph Lo5741a252013-04-03 19:31:48 +0800396 };
397 };
398
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700399 poweroff {
400 compatible = "gpio-poweroff";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700401 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700402 };
403
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300404 hdmi_vdd_reg: regulator-hdmi {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200405 compatible = "regulator-fixed";
406 regulator-name = "avdd_hdmi";
407 regulator-min-microvolt = <3300000>;
408 regulator-max-microvolt = <3300000>;
409 regulator-always-on;
410 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200411
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300412 hdmi_pll_reg: regulator-hdmipll {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200413 compatible = "regulator-fixed";
414 regulator-name = "avdd_hdmi_pll";
415 regulator-min-microvolt = <1800000>;
416 regulator-max-microvolt = <1800000>;
417 regulator-always-on;
418 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200419
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300420 vbus_reg: regulator-vbus {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200421 compatible = "regulator-fixed";
422 regulator-name = "usb1_vbus";
423 regulator-min-microvolt = <5000000>;
424 regulator-max-microvolt = <5000000>;
425 enable-active-high;
426 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
427 regulator-always-on;
428 regulator-boot-on;
429 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530430
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300431 pci_clk_reg: regulator-pciclk {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200432 compatible = "regulator-fixed";
433 regulator-name = "pci_clk";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 regulator-always-on;
437 };
Thierry Reding1798efd2013-08-09 16:49:23 +0200438
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300439 pci_vdd_reg: regulator-pcivdd {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200440 compatible = "regulator-fixed";
441 regulator-name = "pci_vdd";
442 regulator-min-microvolt = <1050000>;
443 regulator-max-microvolt = <1050000>;
444 regulator-always-on;
Thierry Redingdced3e32012-09-20 10:39:20 +0200445 };
446
Dmitry Osipenko83b7f0b2021-12-01 02:23:43 +0300447 vdd_core: regulator-core {
448 compatible = "regulator-fixed";
449 regulator-name = "vdd_core";
450 regulator-min-microvolt = <1300000>;
451 regulator-max-microvolt = <1300000>;
452 regulator-always-on;
453 };
454
Stephen Warrenc04abb32012-05-11 17:03:26 -0600455 sound {
456 compatible = "nvidia,tegra-audio-trimslice";
457 nvidia,i2s-controller = <&tegra_i2s1>;
458 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600459
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300460 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
461 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
462 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600463 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600464 };
Dmitry Osipenkoc19c6312019-10-25 01:14:14 +0300465
466 cpus {
467 cpu0: cpu@0 {
468 operating-points-v2 = <&cpu0_opp_table>;
469 };
470
471 cpu@1 {
472 operating-points-v2 = <&cpu0_opp_table>;
473 };
474 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000475};