Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 4567d5c3eb9b16dfbe8cc5103c0193affbad6491 / . / drivers / net / phy / bcm-phy-lib.h
blob: c3842f87c33b57878e506ee000b66b9085d60b98 [file] [log] [blame]
Nishad Kamdar9aab9062019-11-27 18:49:08 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]2/*
3 * Copyright (C) 2015 Broadcom Corporation
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]4 */
5
6#ifndef _LINUX_BCM_PHY_LIB_H
7#define _LINUX_BCM_PHY_LIB_H
8
Florian Fainelli79fb2182018-05-22 17:04:49 -0700[diff] [blame]9#include <linux/brcmphy.h>
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]10#include <linux/phy.h>
11
Florian Fainellif878fe52019-03-20 12:53:12 -0700[diff] [blame]12/* 28nm only register definitions */
13#define MISC_ADDR(base, channel) base, channel
14
15#define DSP_TAP10 MISC_ADDR(0x0a, 0)
16#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
17#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
18#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
19
20#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
21#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
22#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
23#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
24#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
25#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
26#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
27#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
28
29
Michael Walle7d7e7bc2020-05-13 18:35:21 +0200[diff] [blame]30int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
31int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
Michael Wallee184a902020-05-13 18:35:22 +0200[diff] [blame]32int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]33int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
34int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
Michael Wallee184a902020-05-13 18:35:22 +0200[diff] [blame]35int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]36
Florian Fainelli79fb2182018-05-22 17:04:49 -0700[diff] [blame]37static inline int bcm_phy_write_exp_sel(struct phy_device *phydev,
38 u16 reg, u16 val)
39{
40 return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val);
41}
42
Florian Fainelli5519da82016-11-22 11:40:54 -0800[diff] [blame]43int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
44int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
45
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]46int bcm_phy_write_misc(struct phy_device *phydev,
47 u16 reg, u16 chl, u16 value);
48int bcm_phy_read_misc(struct phy_device *phydev,
49 u16 reg, u16 chl);
50
51int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
52 u16 val);
53int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow);
54
Michael Walle0a32f1f2020-04-20 20:21:11 +0200[diff] [blame]55int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
56int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
57int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
58int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
59int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
60 u16 set);
61int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
62 u16 set);
63
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]64int bcm_phy_ack_intr(struct phy_device *phydev);
65int bcm_phy_config_intr(struct phy_device *phydev);
Ioana Ciornei4567d5c2020-11-01 14:51:06 +0200[diff] [blame^]66irqreturn_t bcm_phy_handle_interrupt(struct phy_device *phydev);
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]67
68int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down);
69
Florian Fainelli99cec8a2016-11-22 11:40:56 -0800[diff] [blame]70int bcm_phy_set_eee(struct phy_device *phydev, bool enable);
Florian Fainellid06f78c2016-11-22 11:40:55 -0800[diff] [blame]71
72int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count);
73
74int bcm_phy_downshift_set(struct phy_device *phydev, u8 count);
75
Florian Fainelli820ee172016-11-29 09:57:17 -0800[diff] [blame]76int bcm_phy_get_sset_count(struct phy_device *phydev);
77void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
78void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
79 struct ethtool_stats *stats, u64 *data);
Florian Fainellif878fe52019-03-20 12:53:12 -0700[diff] [blame]80void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
81int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
Murali Krishna Policharlaab41ca32020-03-27 21:55:40 +0200[diff] [blame]82int bcm_phy_enable_jumbo(struct phy_device *phydev);
Florian Fainelli820ee172016-11-29 09:57:17 -0800[diff] [blame]83
Michael Walle11ecf8c2020-05-13 18:35:23 +0200[diff] [blame]84int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
85 bool *finished);
86int bcm_phy_cable_test_start_rdb(struct phy_device *phydev);
87int bcm_phy_cable_test_start(struct phy_device *phydev);
88int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished);
89
Arun Parameswarana1cba562015-10-06 12:25:48 -0700[diff] [blame]90#endif /* _LINUX_BCM_PHY_LIB_H */