blob: 4d3de91cda6c49963ab3f429aca6ee6b52456cd5 [file] [log] [blame]
Nishad Kamdar9aab9062019-11-27 18:49:08 +05301/* SPDX-License-Identifier: GPL-2.0 */
Arun Parameswarana1cba562015-10-06 12:25:48 -07002/*
3 * Copyright (C) 2015 Broadcom Corporation
Arun Parameswarana1cba562015-10-06 12:25:48 -07004 */
5
6#ifndef _LINUX_BCM_PHY_LIB_H
7#define _LINUX_BCM_PHY_LIB_H
8
Florian Fainelli79fb2182018-05-22 17:04:49 -07009#include <linux/brcmphy.h>
Arun Parameswarana1cba562015-10-06 12:25:48 -070010#include <linux/phy.h>
11
Florian Fainellif878fe52019-03-20 12:53:12 -070012/* 28nm only register definitions */
13#define MISC_ADDR(base, channel) base, channel
14
15#define DSP_TAP10 MISC_ADDR(0x0a, 0)
16#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
17#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
18#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
19
20#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
21#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
22#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
23#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
24#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
25#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
26#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
27#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
28
29
Arun Parameswarana1cba562015-10-06 12:25:48 -070030int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
31int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
32
Florian Fainelli79fb2182018-05-22 17:04:49 -070033static inline int bcm_phy_write_exp_sel(struct phy_device *phydev,
34 u16 reg, u16 val)
35{
36 return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val);
37}
38
Florian Fainelli5519da82016-11-22 11:40:54 -080039int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
40int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
41
Arun Parameswarana1cba562015-10-06 12:25:48 -070042int bcm_phy_write_misc(struct phy_device *phydev,
43 u16 reg, u16 chl, u16 value);
44int bcm_phy_read_misc(struct phy_device *phydev,
45 u16 reg, u16 chl);
46
47int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
48 u16 val);
49int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow);
50
Michael Walle0a32f1f2020-04-20 20:21:11 +020051int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
52int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
53int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
54int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
55int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
56 u16 set);
57int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
58 u16 set);
59
Arun Parameswarana1cba562015-10-06 12:25:48 -070060int bcm_phy_ack_intr(struct phy_device *phydev);
61int bcm_phy_config_intr(struct phy_device *phydev);
62
63int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down);
64
Florian Fainelli99cec8a2016-11-22 11:40:56 -080065int bcm_phy_set_eee(struct phy_device *phydev, bool enable);
Florian Fainellid06f78c2016-11-22 11:40:55 -080066
67int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count);
68
69int bcm_phy_downshift_set(struct phy_device *phydev, u8 count);
70
Florian Fainelli820ee172016-11-29 09:57:17 -080071int bcm_phy_get_sset_count(struct phy_device *phydev);
72void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
73void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
74 struct ethtool_stats *stats, u64 *data);
Florian Fainellif878fe52019-03-20 12:53:12 -070075void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
76int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
Murali Krishna Policharlaab41ca32020-03-27 21:55:40 +020077int bcm_phy_enable_jumbo(struct phy_device *phydev);
Florian Fainelli820ee172016-11-29 09:57:17 -080078
Arun Parameswarana1cba562015-10-06 12:25:48 -070079#endif /* _LINUX_BCM_PHY_LIB_H */