Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 2 | # |
| 3 | # Performance Monitor Drivers |
| 4 | # |
| 5 | |
| 6 | menu "Performance monitor support" |
Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 7 | depends on PERF_EVENTS |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 8 | |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 9 | config ARM_CCI_PMU |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 10 | tristate "ARM CCI PMU driver" |
| 11 | depends on (ARM && CPU_V7) || ARM64 |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 12 | select ARM_CCI |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 13 | help |
| 14 | Support for PMU events monitoring on the ARM CCI (Cache Coherent |
| 15 | Interconnect) family of products. |
| 16 | |
| 17 | If compiled as a module, it will be called arm-cci. |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 18 | |
| 19 | config ARM_CCI400_PMU |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 20 | bool "support CCI-400" |
| 21 | default y |
| 22 | depends on ARM_CCI_PMU |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 23 | select ARM_CCI400_COMMON |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 24 | help |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 25 | CCI-400 provides 4 independent event counters counting events related |
| 26 | to the connected slave/master interfaces, plus a cycle counter. |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 27 | |
| 28 | config ARM_CCI5xx_PMU |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 29 | bool "support CCI-500/CCI-550" |
| 30 | default y |
| 31 | depends on ARM_CCI_PMU |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 32 | help |
Robin Murphy | 8b0c93c | 2018-05-14 14:34:53 +0100 | [diff] [blame] | 33 | CCI-500/CCI-550 both provide 8 independent event counters, which can |
| 34 | count events pertaining to the slave/master interfaces as well as the |
| 35 | internal events to the CCI. |
Robin Murphy | 3de6be7 | 2018-02-15 18:51:42 +0000 | [diff] [blame] | 36 | |
Robin Murphy | 1888d3d | 2018-02-15 18:51:41 +0000 | [diff] [blame] | 37 | config ARM_CCN |
| 38 | tristate "ARM CCN driver support" |
John Garry | e656972 | 2021-10-01 18:48:46 +0800 | [diff] [blame] | 39 | depends on ARM || ARM64 || COMPILE_TEST |
Robin Murphy | 1888d3d | 2018-02-15 18:51:41 +0000 | [diff] [blame] | 40 | help |
| 41 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) |
| 42 | interconnect. |
| 43 | |
Robin Murphy | 0ba6477 | 2020-09-18 14:28:38 +0100 | [diff] [blame] | 44 | config ARM_CMN |
| 45 | tristate "Arm CMN-600 PMU support" |
| 46 | depends on ARM64 || (COMPILE_TEST && 64BIT) |
| 47 | help |
| 48 | Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh |
| 49 | Network interconnect. |
| 50 | |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 51 | config ARM_PMU |
Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 52 | depends on ARM || ARM64 |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 53 | bool "ARM PMU framework" |
| 54 | default y |
| 55 | help |
| 56 | Say y if you want to use CPU performance monitors on ARM-based |
| 57 | systems. |
| 58 | |
Mark Rutland | 45736a7 | 2017-04-11 09:39:55 +0100 | [diff] [blame] | 59 | config ARM_PMU_ACPI |
| 60 | depends on ARM_PMU && ACPI |
| 61 | def_bool y |
| 62 | |
Neil Leeder | 7d839b4 | 2019-03-26 15:17:51 +0000 | [diff] [blame] | 63 | config ARM_SMMU_V3_PMU |
| 64 | tristate "ARM SMMUv3 Performance Monitors Extension" |
John Garry | e656972 | 2021-10-01 18:48:46 +0800 | [diff] [blame] | 65 | depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) |
| 66 | depends on GENERIC_MSI_IRQ_DOMAIN |
Neil Leeder | 7d839b4 | 2019-03-26 15:17:51 +0000 | [diff] [blame] | 67 | help |
| 68 | Provides support for the ARM SMMUv3 Performance Monitor Counter |
| 69 | Groups (PMCG), which provide monitoring of transactions passing |
| 70 | through the SMMU and allow the resulting information to be filtered |
| 71 | based on the Stream ID of the corresponding master. |
| 72 | |
Suzuki K Poulose | 7520fa9 | 2018-01-02 11:25:33 +0000 | [diff] [blame] | 73 | config ARM_DSU_PMU |
| 74 | tristate "ARM DynamIQ Shared Unit (DSU) PMU" |
| 75 | depends on ARM64 |
| 76 | help |
| 77 | Provides support for performance monitor unit in ARM DynamIQ Shared |
| 78 | Unit (DSU). The DSU integrates one or more cores with an L3 memory |
| 79 | system, control logic. The PMU allows counting various events related |
| 80 | to DSU. |
| 81 | |
Frank Li | 9a66d36 | 2019-05-01 18:43:29 +0000 | [diff] [blame] | 82 | config FSL_IMX8_DDR_PMU |
| 83 | tristate "Freescale i.MX8 DDR perf monitor" |
John Garry | e656972 | 2021-10-01 18:48:46 +0800 | [diff] [blame] | 84 | depends on ARCH_MXC || COMPILE_TEST |
Frank Li | 9a66d36 | 2019-05-01 18:43:29 +0000 | [diff] [blame] | 85 | help |
| 86 | Provides support for the DDR performance monitor in i.MX8, which |
| 87 | can give information about memory throughput and other related |
| 88 | events. |
| 89 | |
Neil Leeder | 21bdbb7 | 2017-02-07 13:14:04 -0500 | [diff] [blame] | 90 | config QCOM_L2_PMU |
| 91 | bool "Qualcomm Technologies L2-cache PMU" |
Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 92 | depends on ARCH_QCOM && ARM64 && ACPI |
Ilia Lin | 6d0efeb | 2020-07-03 10:49:41 +0200 | [diff] [blame] | 93 | select QCOM_KRYO_L2_ACCESSORS |
Neil Leeder | 21bdbb7 | 2017-02-07 13:14:04 -0500 | [diff] [blame] | 94 | help |
| 95 | Provides support for the L2 cache performance monitor unit (PMU) |
| 96 | in Qualcomm Technologies processors. |
| 97 | Adds the L2 cache PMU into the perf events subsystem for |
| 98 | monitoring L2 cache events. |
| 99 | |
Agustin Vega-Frias | 3071f13 | 2017-03-31 14:13:43 -0400 | [diff] [blame] | 100 | config QCOM_L3_PMU |
| 101 | bool "Qualcomm Technologies L3-cache PMU" |
Mark Rutland | bddb9b6 | 2017-06-13 13:45:51 +0100 | [diff] [blame] | 102 | depends on ARCH_QCOM && ARM64 && ACPI |
Agustin Vega-Frias | 3071f13 | 2017-03-31 14:13:43 -0400 | [diff] [blame] | 103 | select QCOM_IRQ_COMBINER |
| 104 | help |
| 105 | Provides support for the L3 cache performance monitor unit (PMU) |
| 106 | in Qualcomm Technologies processors. |
| 107 | Adds the L3 cache PMU into the perf events subsystem for |
| 108 | monitoring L3 cache events. |
| 109 | |
Kulkarni, Ganapatrao | 69c3297 | 2018-12-06 11:51:31 +0000 | [diff] [blame] | 110 | config THUNDERX2_PMU |
| 111 | tristate "Cavium ThunderX2 SoC PMU UNCORE" |
John Garry | e656972 | 2021-10-01 18:48:46 +0800 | [diff] [blame] | 112 | depends on ARCH_THUNDER2 || COMPILE_TEST |
| 113 | depends on NUMA && ACPI |
Kulkarni, Ganapatrao | 69c3297 | 2018-12-06 11:51:31 +0000 | [diff] [blame] | 114 | default m |
| 115 | help |
| 116 | Provides support for ThunderX2 UNCORE events. |
| 117 | The SoC has PMU support in its L3 cache controller (L3C) and |
| 118 | in the DDR4 Memory Controller (DMC). |
| 119 | |
Tai Nguyen | 832c927 | 2016-07-15 10:38:04 -0700 | [diff] [blame] | 120 | config XGENE_PMU |
John Garry | e656972 | 2021-10-01 18:48:46 +0800 | [diff] [blame] | 121 | depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) |
Tai Nguyen | 832c927 | 2016-07-15 10:38:04 -0700 | [diff] [blame] | 122 | bool "APM X-Gene SoC PMU" |
| 123 | default n |
| 124 | help |
| 125 | Say y if you want to use APM X-Gene SoC performance monitors. |
| 126 | |
Will Deacon | d5d9696 | 2016-09-22 11:36:32 +0100 | [diff] [blame] | 127 | config ARM_SPE_PMU |
| 128 | tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" |
John Garry | b89205b | 2018-05-22 23:54:04 +0800 | [diff] [blame] | 129 | depends on ARM64 |
Will Deacon | d5d9696 | 2016-09-22 11:36:32 +0100 | [diff] [blame] | 130 | help |
| 131 | Enable perf support for the ARMv8.2 Statistical Profiling |
| 132 | Extension, which provides periodic sampling of operations in |
| 133 | the CPU pipeline and reports this via the perf AUX interface. |
| 134 | |
Tuan Phan | 53c218d | 2020-11-04 11:30:43 -0800 | [diff] [blame] | 135 | config ARM_DMC620_PMU |
| 136 | tristate "Enable PMU support for the ARM DMC-620 memory controller" |
| 137 | depends on (ARM64 && ACPI) || COMPILE_TEST |
| 138 | help |
| 139 | Support for PMU events monitoring on the ARM DMC-620 memory |
| 140 | controller. |
| 141 | |
Zhou Wang | 9780732 | 2020-05-07 10:58:25 +0800 | [diff] [blame] | 142 | source "drivers/perf/hisilicon/Kconfig" |
| 143 | |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 144 | endmenu |