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Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Mark Rutlandfa8ad782015-07-06 12:23:53 +01002#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
Mark Rutlandbddb9b62017-06-13 13:45:51 +01007 depends on PERF_EVENTS
Mark Rutlandfa8ad782015-07-06 12:23:53 +01008
Robin Murphy3de6be72018-02-15 18:51:42 +00009config ARM_CCI_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010010 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
Robin Murphy3de6be72018-02-15 18:51:42 +000012 select ARM_CCI
Robin Murphy8b0c93c2018-05-14 14:34:53 +010013 help
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
16
17 If compiled as a module, it will be called arm-cci.
Robin Murphy3de6be72018-02-15 18:51:42 +000018
19config ARM_CCI400_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010020 bool "support CCI-400"
21 default y
22 depends on ARM_CCI_PMU
Robin Murphy3de6be72018-02-15 18:51:42 +000023 select ARM_CCI400_COMMON
Robin Murphy3de6be72018-02-15 18:51:42 +000024 help
Robin Murphy8b0c93c2018-05-14 14:34:53 +010025 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
Robin Murphy3de6be72018-02-15 18:51:42 +000027
28config ARM_CCI5xx_PMU
Robin Murphy8b0c93c2018-05-14 14:34:53 +010029 bool "support CCI-500/CCI-550"
30 default y
31 depends on ARM_CCI_PMU
Robin Murphy3de6be72018-02-15 18:51:42 +000032 help
Robin Murphy8b0c93c2018-05-14 14:34:53 +010033 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
Robin Murphy3de6be72018-02-15 18:51:42 +000036
Robin Murphy1888d3d2018-02-15 18:51:41 +000037config ARM_CCN
38 tristate "ARM CCN driver support"
John Garrye6569722021-10-01 18:48:46 +080039 depends on ARM || ARM64 || COMPILE_TEST
Robin Murphy1888d3d2018-02-15 18:51:41 +000040 help
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42 interconnect.
43
Robin Murphy0ba64772020-09-18 14:28:38 +010044config ARM_CMN
45 tristate "Arm CMN-600 PMU support"
46 depends on ARM64 || (COMPILE_TEST && 64BIT)
47 help
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
49 Network interconnect.
50
Mark Rutlandfa8ad782015-07-06 12:23:53 +010051config ARM_PMU
Mark Rutlandbddb9b62017-06-13 13:45:51 +010052 depends on ARM || ARM64
Mark Rutlandfa8ad782015-07-06 12:23:53 +010053 bool "ARM PMU framework"
54 default y
55 help
56 Say y if you want to use CPU performance monitors on ARM-based
57 systems.
58
Mark Rutland45736a72017-04-11 09:39:55 +010059config ARM_PMU_ACPI
60 depends on ARM_PMU && ACPI
61 def_bool y
62
Neil Leeder7d839b42019-03-26 15:17:51 +000063config ARM_SMMU_V3_PMU
64 tristate "ARM SMMUv3 Performance Monitors Extension"
John Garrye6569722021-10-01 18:48:46 +080065 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
66 depends on GENERIC_MSI_IRQ_DOMAIN
Neil Leeder7d839b42019-03-26 15:17:51 +000067 help
68 Provides support for the ARM SMMUv3 Performance Monitor Counter
69 Groups (PMCG), which provide monitoring of transactions passing
70 through the SMMU and allow the resulting information to be filtered
71 based on the Stream ID of the corresponding master.
72
Suzuki K Poulose7520fa92018-01-02 11:25:33 +000073config ARM_DSU_PMU
74 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
75 depends on ARM64
76 help
77 Provides support for performance monitor unit in ARM DynamIQ Shared
78 Unit (DSU). The DSU integrates one or more cores with an L3 memory
79 system, control logic. The PMU allows counting various events related
80 to DSU.
81
Frank Li9a66d362019-05-01 18:43:29 +000082config FSL_IMX8_DDR_PMU
83 tristate "Freescale i.MX8 DDR perf monitor"
John Garrye6569722021-10-01 18:48:46 +080084 depends on ARCH_MXC || COMPILE_TEST
Frank Li9a66d362019-05-01 18:43:29 +000085 help
86 Provides support for the DDR performance monitor in i.MX8, which
87 can give information about memory throughput and other related
88 events.
89
Neil Leeder21bdbb72017-02-07 13:14:04 -050090config QCOM_L2_PMU
91 bool "Qualcomm Technologies L2-cache PMU"
Mark Rutlandbddb9b62017-06-13 13:45:51 +010092 depends on ARCH_QCOM && ARM64 && ACPI
Ilia Lin6d0efeb2020-07-03 10:49:41 +020093 select QCOM_KRYO_L2_ACCESSORS
Neil Leeder21bdbb72017-02-07 13:14:04 -050094 help
95 Provides support for the L2 cache performance monitor unit (PMU)
96 in Qualcomm Technologies processors.
97 Adds the L2 cache PMU into the perf events subsystem for
98 monitoring L2 cache events.
99
Agustin Vega-Frias3071f132017-03-31 14:13:43 -0400100config QCOM_L3_PMU
101 bool "Qualcomm Technologies L3-cache PMU"
Mark Rutlandbddb9b62017-06-13 13:45:51 +0100102 depends on ARCH_QCOM && ARM64 && ACPI
Agustin Vega-Frias3071f132017-03-31 14:13:43 -0400103 select QCOM_IRQ_COMBINER
104 help
105 Provides support for the L3 cache performance monitor unit (PMU)
106 in Qualcomm Technologies processors.
107 Adds the L3 cache PMU into the perf events subsystem for
108 monitoring L3 cache events.
109
Kulkarni, Ganapatrao69c32972018-12-06 11:51:31 +0000110config THUNDERX2_PMU
111 tristate "Cavium ThunderX2 SoC PMU UNCORE"
John Garrye6569722021-10-01 18:48:46 +0800112 depends on ARCH_THUNDER2 || COMPILE_TEST
113 depends on NUMA && ACPI
Kulkarni, Ganapatrao69c32972018-12-06 11:51:31 +0000114 default m
115 help
116 Provides support for ThunderX2 UNCORE events.
117 The SoC has PMU support in its L3 cache controller (L3C) and
118 in the DDR4 Memory Controller (DMC).
119
Tai Nguyen832c9272016-07-15 10:38:04 -0700120config XGENE_PMU
John Garrye6569722021-10-01 18:48:46 +0800121 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
Tai Nguyen832c9272016-07-15 10:38:04 -0700122 bool "APM X-Gene SoC PMU"
123 default n
124 help
125 Say y if you want to use APM X-Gene SoC performance monitors.
126
Will Deacond5d96962016-09-22 11:36:32 +0100127config ARM_SPE_PMU
128 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
John Garryb89205b2018-05-22 23:54:04 +0800129 depends on ARM64
Will Deacond5d96962016-09-22 11:36:32 +0100130 help
131 Enable perf support for the ARMv8.2 Statistical Profiling
132 Extension, which provides periodic sampling of operations in
133 the CPU pipeline and reports this via the perf AUX interface.
134
Tuan Phan53c218d2020-11-04 11:30:43 -0800135config ARM_DMC620_PMU
136 tristate "Enable PMU support for the ARM DMC-620 memory controller"
137 depends on (ARM64 && ACPI) || COMPILE_TEST
138 help
139 Support for PMU events monitoring on the ARM DMC-620 memory
140 controller.
141
Zhou Wang97807322020-05-07 10:58:25 +0800142source "drivers/perf/hisilicon/Kconfig"
143
Mark Rutlandfa8ad782015-07-06 12:23:53 +0100144endmenu