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Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Catalin Marinas0aea86a2012-03-05 11:49:32 +00002/*
3 * Based on arch/arm/include/asm/uaccess.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
Catalin Marinas0aea86a2012-03-05 11:49:32 +00006 */
7#ifndef __ASM_UACCESS_H
8#define __ASM_UACCESS_H
9
Catalin Marinasbd389672016-07-01 14:58:21 +010010#include <asm/alternative.h>
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010011#include <asm/kernel-pgtable.h>
Catalin Marinasbd389672016-07-01 14:58:21 +010012#include <asm/sysreg.h>
13
Catalin Marinas0aea86a2012-03-05 11:49:32 +000014/*
15 * User space memory access functions
16 */
Andre Przywara87261d12016-10-19 14:40:54 +010017#include <linux/bitops.h>
Yang Shibffe1ba2016-06-08 14:40:56 -070018#include <linux/kasan-checks.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000019#include <linux/string.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000020
James Morse338d4f42015-07-22 19:05:54 +010021#include <asm/cpufeature.h>
Will Deacon5f1f7f62020-06-30 13:53:07 +010022#include <asm/mmu.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000023#include <asm/ptrace.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000024#include <asm/memory.h>
Al Viro46583932016-12-25 14:00:03 -050025#include <asm/extable.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000026
Mark Rutlandfc703d82020-12-02 13:15:53 +000027#define HAVE_GET_KERNEL_NOFAULT
28
Catalin Marinas0aea86a2012-03-05 11:49:32 +000029/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +000030 * Test whether a block of memory is a valid user space address.
31 * Returns 1 if the range is valid, 0 otherwise.
32 *
33 * This is equivalent to the following test:
Mark Rutland3d2403f2020-12-02 13:15:55 +000034 * (u65)addr + (u65)size <= (u65)TASK_SIZE_MAX
Catalin Marinas0aea86a2012-03-05 11:49:32 +000035 */
Robin Murphy9085b342018-02-19 13:38:00 +000036static inline unsigned long __range_ok(const void __user *addr, unsigned long size)
Robin Murphy51369e32018-02-05 15:34:18 +000037{
Mark Rutland3d2403f2020-12-02 13:15:55 +000038 unsigned long ret, limit = TASK_SIZE_MAX - 1;
Robin Murphy51369e32018-02-05 15:34:18 +000039
Catalin Marinasdf325e02019-12-05 13:57:36 +000040 /*
41 * Asynchronous I/O running in a kernel thread does not have the
42 * TIF_TAGGED_ADDR flag of the process owning the mm, so always untag
43 * the user address before checking.
44 */
Catalin Marinas63f0c602019-07-23 19:58:39 +020045 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) &&
Catalin Marinasdf325e02019-12-05 13:57:36 +000046 (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR)))
Catalin Marinas63f0c602019-07-23 19:58:39 +020047 addr = untagged_addr(addr);
Andrey Konovalov2b835e22019-07-23 19:58:38 +020048
Robin Murphy51369e32018-02-05 15:34:18 +000049 __chk_user_ptr(addr);
50 asm volatile(
51 // A + B <= C + 1 for all A,B,C, in four easy steps:
52 // 1: X = A + B; X' = X % 2^64
Robin Murphy9085b342018-02-19 13:38:00 +000053 " adds %0, %3, %2\n"
Robin Murphy51369e32018-02-05 15:34:18 +000054 // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4
55 " csel %1, xzr, %1, hi\n"
56 // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X'
57 // to compensate for the carry flag being set in step 4. For
58 // X > 2^64, X' merely has to remain nonzero, which it does.
59 " csinv %0, %0, xzr, cc\n"
60 // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1
61 // comes from the carry in being clear. Otherwise, we are
62 // testing X' - C == 0, subject to the previous adjustments.
63 " sbcs xzr, %0, %1\n"
64 " cset %0, ls\n"
Robin Murphy9085b342018-02-19 13:38:00 +000065 : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc");
Robin Murphy51369e32018-02-05 15:34:18 +000066
Robin Murphy9085b342018-02-19 13:38:00 +000067 return ret;
Robin Murphy51369e32018-02-05 15:34:18 +000068}
Catalin Marinas0aea86a2012-03-05 11:49:32 +000069
Linus Torvalds96d4f262019-01-03 18:57:57 -080070#define access_ok(addr, size) __range_ok(addr, size)
Catalin Marinas0aea86a2012-03-05 11:49:32 +000071
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010072#define _ASM_EXTABLE(from, to) \
73 " .pushsection __ex_table, \"a\"\n" \
74 " .align 3\n" \
75 " .long (" #from " - .), (" #to " - .)\n" \
76 " .popsection\n"
77
Catalin Marinas0aea86a2012-03-05 11:49:32 +000078/*
Catalin Marinasbd389672016-07-01 14:58:21 +010079 * User access enabling/disabling.
80 */
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010081#ifdef CONFIG_ARM64_SW_TTBR0_PAN
82static inline void __uaccess_ttbr0_disable(void)
83{
Catalin Marinas6b88a322018-01-10 13:18:30 +000084 unsigned long flags, ttbr;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010085
Catalin Marinas6b88a322018-01-10 13:18:30 +000086 local_irq_save(flags);
Will Deacon27a921e2017-08-10 13:58:16 +010087 ttbr = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +000088 ttbr &= ~TTBR_ASID_MASK;
Steve Capper9dfe4822018-01-11 10:11:57 +000089 /* reserved_ttbr0 placed before swapper_pg_dir */
90 write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1);
Will Deacon27a921e2017-08-10 13:58:16 +010091 isb();
92 /* Set reserved ASID */
Will Deacon27a921e2017-08-10 13:58:16 +010093 write_sysreg(ttbr, ttbr1_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010094 isb();
Catalin Marinas6b88a322018-01-10 13:18:30 +000095 local_irq_restore(flags);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010096}
97
98static inline void __uaccess_ttbr0_enable(void)
99{
Will Deacon27a921e2017-08-10 13:58:16 +0100100 unsigned long flags, ttbr0, ttbr1;
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100101
102 /*
103 * Disable interrupts to avoid preemption between reading the 'ttbr0'
104 * variable and the MSR. A context switch could trigger an ASID
105 * roll-over and an update of 'ttbr0'.
106 */
107 local_irq_save(flags);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000108 ttbr0 = READ_ONCE(current_thread_info()->ttbr0);
Will Deacon27a921e2017-08-10 13:58:16 +0100109
110 /* Restore active ASID */
111 ttbr1 = read_sysreg(ttbr1_el1);
Catalin Marinas6b88a322018-01-10 13:18:30 +0000112 ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */
Will Deaconb5195382017-12-01 17:33:48 +0000113 ttbr1 |= ttbr0 & TTBR_ASID_MASK;
Will Deacon27a921e2017-08-10 13:58:16 +0100114 write_sysreg(ttbr1, ttbr1_el1);
115 isb();
116
117 /* Restore user page table */
118 write_sysreg(ttbr0, ttbr0_el1);
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100119 isb();
120 local_irq_restore(flags);
121}
122
123static inline bool uaccess_ttbr0_disable(void)
124{
125 if (!system_uses_ttbr0_pan())
126 return false;
127 __uaccess_ttbr0_disable();
128 return true;
129}
130
131static inline bool uaccess_ttbr0_enable(void)
132{
133 if (!system_uses_ttbr0_pan())
134 return false;
135 __uaccess_ttbr0_enable();
136 return true;
137}
138#else
139static inline bool uaccess_ttbr0_disable(void)
140{
141 return false;
142}
143
144static inline bool uaccess_ttbr0_enable(void)
145{
146 return false;
147}
148#endif
149
James Morsee1281f52018-01-08 15:38:11 +0000150static inline void __uaccess_disable_hw_pan(void)
151{
152 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,
153 CONFIG_ARM64_PAN));
154}
155
156static inline void __uaccess_enable_hw_pan(void)
157{
158 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
159 CONFIG_ARM64_PAN));
160}
161
Catalin Marinasbd389672016-07-01 14:58:21 +0100162#define __uaccess_disable(alt) \
163do { \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100164 if (!uaccess_ttbr0_disable()) \
165 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \
166 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100167} while (0)
168
169#define __uaccess_enable(alt) \
170do { \
Marc Zyngier75037122016-12-12 13:50:26 +0000171 if (!uaccess_ttbr0_enable()) \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100172 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \
173 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100174} while (0)
175
Mark Rutland923e1e72020-12-02 13:15:50 +0000176static inline void uaccess_disable_privileged(void)
Catalin Marinasbd389672016-07-01 14:58:21 +0100177{
178 __uaccess_disable(ARM64_HAS_PAN);
179}
180
Mark Rutland923e1e72020-12-02 13:15:50 +0000181static inline void uaccess_enable_privileged(void)
Catalin Marinasbd389672016-07-01 14:58:21 +0100182{
183 __uaccess_enable(ARM64_HAS_PAN);
184}
185
186/*
187 * These functions are no-ops when UAO is present.
188 */
189static inline void uaccess_disable_not_uao(void)
190{
191 __uaccess_disable(ARM64_ALT_PAN_NOT_UAO);
192}
193
194static inline void uaccess_enable_not_uao(void)
195{
196 __uaccess_enable(ARM64_ALT_PAN_NOT_UAO);
197}
198
199/*
Mark Rutland3d2403f2020-12-02 13:15:55 +0000200 * Sanitise a uaccess pointer such that it becomes NULL if above the maximum
201 * user address. In case the pointer is tagged (has the top byte set), untag
202 * the pointer before checking.
Robin Murphy4d8efc22018-02-05 15:34:19 +0000203 */
204#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
205static inline void __user *__uaccess_mask_ptr(const void __user *ptr)
206{
207 void __user *safe_ptr;
208
209 asm volatile(
Andrey Konovalov2b835e22019-07-23 19:58:38 +0200210 " bics xzr, %3, %2\n"
Robin Murphy4d8efc22018-02-05 15:34:19 +0000211 " csel %0, %1, xzr, eq\n"
212 : "=&r" (safe_ptr)
Mark Rutland3d2403f2020-12-02 13:15:55 +0000213 : "r" (ptr), "r" (TASK_SIZE_MAX - 1),
Andrey Konovalov2b835e22019-07-23 19:58:38 +0200214 "r" (untagged_addr(ptr))
Robin Murphy4d8efc22018-02-05 15:34:19 +0000215 : "cc");
216
217 csdb();
218 return safe_ptr;
219}
220
221/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000222 * The "__xxx" versions of the user access functions do not verify the address
223 * space - it must have been done previously with a separate "access_ok()"
224 * call.
225 *
226 * The "__xxx_error" versions set the third argument to -EFAULT if an error
227 * occurs, and leave it unchanged on success.
228 */
Mark Rutlandfc703d82020-12-02 13:15:53 +0000229#define __get_mem_asm(load, reg, x, addr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000230 asm volatile( \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000231 "1: " load " " reg "1, [%2]\n" \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000232 "2:\n" \
233 " .section .fixup, \"ax\"\n" \
234 " .align 2\n" \
235 "3: mov %w0, %3\n" \
236 " mov %1, #0\n" \
237 " b 2b\n" \
238 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100239 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000240 : "+r" (err), "=&r" (x) \
241 : "r" (addr), "i" (-EFAULT))
242
Mark Rutlandfc703d82020-12-02 13:15:53 +0000243#define __raw_get_mem(ldr, x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000244do { \
245 unsigned long __gu_val; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000246 switch (sizeof(*(ptr))) { \
247 case 1: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000248 __get_mem_asm(ldr "b", "%w", __gu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000249 break; \
250 case 2: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000251 __get_mem_asm(ldr "h", "%w", __gu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000252 break; \
253 case 4: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000254 __get_mem_asm(ldr, "%w", __gu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000255 break; \
256 case 8: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000257 __get_mem_asm(ldr, "%x", __gu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000258 break; \
259 default: \
260 BUILD_BUG(); \
261 } \
Michael S. Tsirkin58fff512014-12-12 01:56:04 +0200262 (x) = (__force __typeof__(*(ptr)))__gu_val; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000263} while (0)
264
Mark Rutlandf253d822020-12-02 13:15:52 +0000265#define __raw_get_user(x, ptr, err) \
266do { \
267 __chk_user_ptr(ptr); \
268 uaccess_enable_not_uao(); \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000269 __raw_get_mem("ldtr", x, ptr, err); \
Mark Rutlandf253d822020-12-02 13:15:52 +0000270 uaccess_disable_not_uao(); \
271} while (0)
272
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000273#define __get_user_error(x, ptr, err) \
274do { \
Will Deacon84624082018-02-05 15:34:22 +0000275 __typeof__(*(ptr)) __user *__p = (ptr); \
276 might_fault(); \
Linus Torvalds96d4f262019-01-03 18:57:57 -0800277 if (access_ok(__p, sizeof(*__p))) { \
Will Deacon84624082018-02-05 15:34:22 +0000278 __p = uaccess_mask_ptr(__p); \
Catalin Marinas3cd0ddb2019-03-01 14:19:06 +0000279 __raw_get_user((x), __p, (err)); \
Will Deacon84624082018-02-05 15:34:22 +0000280 } else { \
Al Viro8cfb3472020-05-22 15:23:21 +0100281 (x) = (__force __typeof__(x))0; (err) = -EFAULT; \
Will Deacon84624082018-02-05 15:34:22 +0000282 } \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000283} while (0)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000284
Will Deacon84624082018-02-05 15:34:22 +0000285#define __get_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000286({ \
Will Deacon84624082018-02-05 15:34:22 +0000287 int __gu_err = 0; \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000288 __get_user_error((x), (ptr), __gu_err); \
Will Deacon84624082018-02-05 15:34:22 +0000289 __gu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000290})
291
Will Deacon84624082018-02-05 15:34:22 +0000292#define get_user __get_user
293
Mark Rutlandfc703d82020-12-02 13:15:53 +0000294#define __get_kernel_nofault(dst, src, type, err_label) \
295do { \
296 int __gkn_err = 0; \
297 \
298 __raw_get_mem("ldr", *((type *)(dst)), \
299 (__force type *)(src), __gkn_err); \
300 if (unlikely(__gkn_err)) \
301 goto err_label; \
302} while (0)
303
304#define __put_mem_asm(store, reg, x, addr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000305 asm volatile( \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000306 "1: " store " " reg "1, [%2]\n" \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000307 "2:\n" \
308 " .section .fixup,\"ax\"\n" \
309 " .align 2\n" \
310 "3: mov %w0, %3\n" \
311 " b 2b\n" \
312 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100313 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000314 : "+r" (err) \
315 : "r" (x), "r" (addr), "i" (-EFAULT))
316
Mark Rutlandfc703d82020-12-02 13:15:53 +0000317#define __raw_put_mem(str, x, ptr, err) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000318do { \
319 __typeof__(*(ptr)) __pu_val = (x); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000320 switch (sizeof(*(ptr))) { \
321 case 1: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000322 __put_mem_asm(str "b", "%w", __pu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000323 break; \
324 case 2: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000325 __put_mem_asm(str "h", "%w", __pu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000326 break; \
327 case 4: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000328 __put_mem_asm(str, "%w", __pu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000329 break; \
330 case 8: \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000331 __put_mem_asm(str, "%x", __pu_val, (ptr), (err)); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000332 break; \
333 default: \
334 BUILD_BUG(); \
335 } \
Mark Rutlandf253d822020-12-02 13:15:52 +0000336} while (0)
337
338#define __raw_put_user(x, ptr, err) \
339do { \
340 __chk_user_ptr(ptr); \
341 uaccess_enable_not_uao(); \
Mark Rutlandfc703d82020-12-02 13:15:53 +0000342 __raw_put_mem("sttr", x, ptr, err); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100343 uaccess_disable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000344} while (0)
345
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000346#define __put_user_error(x, ptr, err) \
347do { \
Will Deacon84624082018-02-05 15:34:22 +0000348 __typeof__(*(ptr)) __user *__p = (ptr); \
349 might_fault(); \
Linus Torvalds96d4f262019-01-03 18:57:57 -0800350 if (access_ok(__p, sizeof(*__p))) { \
Will Deacon84624082018-02-05 15:34:22 +0000351 __p = uaccess_mask_ptr(__p); \
Catalin Marinas3cd0ddb2019-03-01 14:19:06 +0000352 __raw_put_user((x), __p, (err)); \
Will Deacon84624082018-02-05 15:34:22 +0000353 } else { \
354 (err) = -EFAULT; \
355 } \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000356} while (0)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000357
Will Deacon84624082018-02-05 15:34:22 +0000358#define __put_user(x, ptr) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000359({ \
Will Deacon84624082018-02-05 15:34:22 +0000360 int __pu_err = 0; \
Julien Thierry13e4cdd2019-01-15 13:58:26 +0000361 __put_user_error((x), (ptr), __pu_err); \
Will Deacon84624082018-02-05 15:34:22 +0000362 __pu_err; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000363})
364
Will Deacon84624082018-02-05 15:34:22 +0000365#define put_user __put_user
366
Mark Rutlandfc703d82020-12-02 13:15:53 +0000367#define __put_kernel_nofault(dst, src, type, err_label) \
368do { \
369 int __pkn_err = 0; \
370 \
371 __raw_put_mem("str", *((type *)(src)), \
372 (__force type *)(dst), __pkn_err); \
373 if (unlikely(__pkn_err)) \
374 goto err_label; \
375} while(0)
376
Yang Shibffe1ba2016-06-08 14:40:56 -0700377extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000378#define raw_copy_from_user(to, from, n) \
379({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500380 unsigned long __acfu_ret; \
381 uaccess_enable_not_uao(); \
382 __acfu_ret = __arch_copy_from_user((to), \
383 __uaccess_mask_ptr(from), (n)); \
384 uaccess_disable_not_uao(); \
385 __acfu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000386})
387
Yang Shibffe1ba2016-06-08 14:40:56 -0700388extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000389#define raw_copy_to_user(to, from, n) \
390({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500391 unsigned long __actu_ret; \
392 uaccess_enable_not_uao(); \
393 __actu_ret = __arch_copy_to_user(__uaccess_mask_ptr(to), \
394 (from), (n)); \
395 uaccess_disable_not_uao(); \
396 __actu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000397})
398
399extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n);
400#define raw_copy_in_user(to, from, n) \
401({ \
Pavel Tatashine50be642019-11-20 12:07:40 -0500402 unsigned long __aciu_ret; \
403 uaccess_enable_not_uao(); \
404 __aciu_ret = __arch_copy_in_user(__uaccess_mask_ptr(to), \
405 __uaccess_mask_ptr(from), (n)); \
406 uaccess_disable_not_uao(); \
407 __aciu_ret; \
Will Deaconf71c2ff2018-02-05 15:34:23 +0000408})
409
Al Viro92430da2017-03-21 08:40:57 -0400410#define INLINE_COPY_TO_USER
411#define INLINE_COPY_FROM_USER
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000412
Will Deaconf71c2ff2018-02-05 15:34:23 +0000413extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n);
414static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n)
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000415{
Pavel Tatashine50be642019-11-20 12:07:40 -0500416 if (access_ok(to, n)) {
417 uaccess_enable_not_uao();
Will Deaconf71c2ff2018-02-05 15:34:23 +0000418 n = __arch_clear_user(__uaccess_mask_ptr(to), n);
Pavel Tatashine50be642019-11-20 12:07:40 -0500419 uaccess_disable_not_uao();
420 }
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000421 return n;
422}
Will Deaconf71c2ff2018-02-05 15:34:23 +0000423#define clear_user __clear_user
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000424
Will Deacon12a0ef72013-11-06 17:20:22 +0000425extern long strncpy_from_user(char *dest, const char __user *src, long count);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000426
Will Deacon12a0ef72013-11-06 17:20:22 +0000427extern __must_check long strnlen_user(const char __user *str, long n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000428
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100429#ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE
430struct page;
431void memcpy_page_flushcache(char *to, struct page *page, size_t offset, size_t len);
432extern unsigned long __must_check __copy_user_flushcache(void *to, const void __user *from, unsigned long n);
433
434static inline int __copy_from_user_flushcache(void *dst, const void __user *src, unsigned size)
435{
436 kasan_check_write(dst, size);
Will Deaconf71c2ff2018-02-05 15:34:23 +0000437 return __copy_user_flushcache(dst, __uaccess_mask_ptr(src), size);
Robin Murphy5d7bdeb2017-07-25 11:55:43 +0100438}
439#endif
440
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000441#endif /* __ASM_UACCESS_H */