Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Based on arch/arm/include/asm/uaccess.h |
| 4 | * |
| 5 | * Copyright (C) 2012 ARM Ltd. |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef __ASM_UACCESS_H |
| 8 | #define __ASM_UACCESS_H |
| 9 | |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 10 | #include <asm/alternative.h> |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 11 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 12 | #include <asm/sysreg.h> |
| 13 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 14 | /* |
| 15 | * User space memory access functions |
| 16 | */ |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 17 | #include <linux/bitops.h> |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 18 | #include <linux/kasan-checks.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 19 | #include <linux/string.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 20 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 21 | #include <asm/cpufeature.h> |
Will Deacon | 5f1f7f6 | 2020-06-30 13:53:07 +0100 | [diff] [blame] | 22 | #include <asm/mmu.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 23 | #include <asm/ptrace.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 24 | #include <asm/memory.h> |
Al Viro | 4658393 | 2016-12-25 14:00:03 -0500 | [diff] [blame] | 25 | #include <asm/extable.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 26 | |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 27 | #define HAVE_GET_KERNEL_NOFAULT |
| 28 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 29 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 30 | * Test whether a block of memory is a valid user space address. |
| 31 | * Returns 1 if the range is valid, 0 otherwise. |
| 32 | * |
| 33 | * This is equivalent to the following test: |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame^] | 34 | * (u65)addr + (u65)size <= (u65)TASK_SIZE_MAX |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 35 | */ |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 36 | static inline unsigned long __range_ok(const void __user *addr, unsigned long size) |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 37 | { |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame^] | 38 | unsigned long ret, limit = TASK_SIZE_MAX - 1; |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 39 | |
Catalin Marinas | df325e0 | 2019-12-05 13:57:36 +0000 | [diff] [blame] | 40 | /* |
| 41 | * Asynchronous I/O running in a kernel thread does not have the |
| 42 | * TIF_TAGGED_ADDR flag of the process owning the mm, so always untag |
| 43 | * the user address before checking. |
| 44 | */ |
Catalin Marinas | 63f0c60 | 2019-07-23 19:58:39 +0200 | [diff] [blame] | 45 | if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) && |
Catalin Marinas | df325e0 | 2019-12-05 13:57:36 +0000 | [diff] [blame] | 46 | (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR))) |
Catalin Marinas | 63f0c60 | 2019-07-23 19:58:39 +0200 | [diff] [blame] | 47 | addr = untagged_addr(addr); |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 48 | |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 49 | __chk_user_ptr(addr); |
| 50 | asm volatile( |
| 51 | // A + B <= C + 1 for all A,B,C, in four easy steps: |
| 52 | // 1: X = A + B; X' = X % 2^64 |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 53 | " adds %0, %3, %2\n" |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 54 | // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 |
| 55 | " csel %1, xzr, %1, hi\n" |
| 56 | // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' |
| 57 | // to compensate for the carry flag being set in step 4. For |
| 58 | // X > 2^64, X' merely has to remain nonzero, which it does. |
| 59 | " csinv %0, %0, xzr, cc\n" |
| 60 | // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 |
| 61 | // comes from the carry in being clear. Otherwise, we are |
| 62 | // testing X' - C == 0, subject to the previous adjustments. |
| 63 | " sbcs xzr, %0, %1\n" |
| 64 | " cset %0, ls\n" |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 65 | : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc"); |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 66 | |
Robin Murphy | 9085b34 | 2018-02-19 13:38:00 +0000 | [diff] [blame] | 67 | return ret; |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 68 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 69 | |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 70 | #define access_ok(addr, size) __range_ok(addr, size) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 71 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 72 | #define _ASM_EXTABLE(from, to) \ |
| 73 | " .pushsection __ex_table, \"a\"\n" \ |
| 74 | " .align 3\n" \ |
| 75 | " .long (" #from " - .), (" #to " - .)\n" \ |
| 76 | " .popsection\n" |
| 77 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 78 | /* |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 79 | * User access enabling/disabling. |
| 80 | */ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 81 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 82 | static inline void __uaccess_ttbr0_disable(void) |
| 83 | { |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 84 | unsigned long flags, ttbr; |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 85 | |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 86 | local_irq_save(flags); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 87 | ttbr = read_sysreg(ttbr1_el1); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 88 | ttbr &= ~TTBR_ASID_MASK; |
Steve Capper | 9dfe482 | 2018-01-11 10:11:57 +0000 | [diff] [blame] | 89 | /* reserved_ttbr0 placed before swapper_pg_dir */ |
| 90 | write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 91 | isb(); |
| 92 | /* Set reserved ASID */ |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 93 | write_sysreg(ttbr, ttbr1_el1); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 94 | isb(); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 95 | local_irq_restore(flags); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | static inline void __uaccess_ttbr0_enable(void) |
| 99 | { |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 100 | unsigned long flags, ttbr0, ttbr1; |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 101 | |
| 102 | /* |
| 103 | * Disable interrupts to avoid preemption between reading the 'ttbr0' |
| 104 | * variable and the MSR. A context switch could trigger an ASID |
| 105 | * roll-over and an update of 'ttbr0'. |
| 106 | */ |
| 107 | local_irq_save(flags); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 108 | ttbr0 = READ_ONCE(current_thread_info()->ttbr0); |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 109 | |
| 110 | /* Restore active ASID */ |
| 111 | ttbr1 = read_sysreg(ttbr1_el1); |
Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 112 | ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */ |
Will Deacon | b519538 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 113 | ttbr1 |= ttbr0 & TTBR_ASID_MASK; |
Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 114 | write_sysreg(ttbr1, ttbr1_el1); |
| 115 | isb(); |
| 116 | |
| 117 | /* Restore user page table */ |
| 118 | write_sysreg(ttbr0, ttbr0_el1); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 119 | isb(); |
| 120 | local_irq_restore(flags); |
| 121 | } |
| 122 | |
| 123 | static inline bool uaccess_ttbr0_disable(void) |
| 124 | { |
| 125 | if (!system_uses_ttbr0_pan()) |
| 126 | return false; |
| 127 | __uaccess_ttbr0_disable(); |
| 128 | return true; |
| 129 | } |
| 130 | |
| 131 | static inline bool uaccess_ttbr0_enable(void) |
| 132 | { |
| 133 | if (!system_uses_ttbr0_pan()) |
| 134 | return false; |
| 135 | __uaccess_ttbr0_enable(); |
| 136 | return true; |
| 137 | } |
| 138 | #else |
| 139 | static inline bool uaccess_ttbr0_disable(void) |
| 140 | { |
| 141 | return false; |
| 142 | } |
| 143 | |
| 144 | static inline bool uaccess_ttbr0_enable(void) |
| 145 | { |
| 146 | return false; |
| 147 | } |
| 148 | #endif |
| 149 | |
James Morse | e1281f5 | 2018-01-08 15:38:11 +0000 | [diff] [blame] | 150 | static inline void __uaccess_disable_hw_pan(void) |
| 151 | { |
| 152 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, |
| 153 | CONFIG_ARM64_PAN)); |
| 154 | } |
| 155 | |
| 156 | static inline void __uaccess_enable_hw_pan(void) |
| 157 | { |
| 158 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, |
| 159 | CONFIG_ARM64_PAN)); |
| 160 | } |
| 161 | |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 162 | #define __uaccess_disable(alt) \ |
| 163 | do { \ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 164 | if (!uaccess_ttbr0_disable()) \ |
| 165 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ |
| 166 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 167 | } while (0) |
| 168 | |
| 169 | #define __uaccess_enable(alt) \ |
| 170 | do { \ |
Marc Zyngier | 7503712 | 2016-12-12 13:50:26 +0000 | [diff] [blame] | 171 | if (!uaccess_ttbr0_enable()) \ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 172 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ |
| 173 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 174 | } while (0) |
| 175 | |
Mark Rutland | 923e1e7 | 2020-12-02 13:15:50 +0000 | [diff] [blame] | 176 | static inline void uaccess_disable_privileged(void) |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 177 | { |
| 178 | __uaccess_disable(ARM64_HAS_PAN); |
| 179 | } |
| 180 | |
Mark Rutland | 923e1e7 | 2020-12-02 13:15:50 +0000 | [diff] [blame] | 181 | static inline void uaccess_enable_privileged(void) |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 182 | { |
| 183 | __uaccess_enable(ARM64_HAS_PAN); |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * These functions are no-ops when UAO is present. |
| 188 | */ |
| 189 | static inline void uaccess_disable_not_uao(void) |
| 190 | { |
| 191 | __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); |
| 192 | } |
| 193 | |
| 194 | static inline void uaccess_enable_not_uao(void) |
| 195 | { |
| 196 | __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); |
| 197 | } |
| 198 | |
| 199 | /* |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame^] | 200 | * Sanitise a uaccess pointer such that it becomes NULL if above the maximum |
| 201 | * user address. In case the pointer is tagged (has the top byte set), untag |
| 202 | * the pointer before checking. |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 203 | */ |
| 204 | #define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) |
| 205 | static inline void __user *__uaccess_mask_ptr(const void __user *ptr) |
| 206 | { |
| 207 | void __user *safe_ptr; |
| 208 | |
| 209 | asm volatile( |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 210 | " bics xzr, %3, %2\n" |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 211 | " csel %0, %1, xzr, eq\n" |
| 212 | : "=&r" (safe_ptr) |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame^] | 213 | : "r" (ptr), "r" (TASK_SIZE_MAX - 1), |
Andrey Konovalov | 2b835e2 | 2019-07-23 19:58:38 +0200 | [diff] [blame] | 214 | "r" (untagged_addr(ptr)) |
Robin Murphy | 4d8efc2 | 2018-02-05 15:34:19 +0000 | [diff] [blame] | 215 | : "cc"); |
| 216 | |
| 217 | csdb(); |
| 218 | return safe_ptr; |
| 219 | } |
| 220 | |
| 221 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 222 | * The "__xxx" versions of the user access functions do not verify the address |
| 223 | * space - it must have been done previously with a separate "access_ok()" |
| 224 | * call. |
| 225 | * |
| 226 | * The "__xxx_error" versions set the third argument to -EFAULT if an error |
| 227 | * occurs, and leave it unchanged on success. |
| 228 | */ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 229 | #define __get_mem_asm(load, reg, x, addr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 230 | asm volatile( \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 231 | "1: " load " " reg "1, [%2]\n" \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 232 | "2:\n" \ |
| 233 | " .section .fixup, \"ax\"\n" \ |
| 234 | " .align 2\n" \ |
| 235 | "3: mov %w0, %3\n" \ |
| 236 | " mov %1, #0\n" \ |
| 237 | " b 2b\n" \ |
| 238 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 239 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 240 | : "+r" (err), "=&r" (x) \ |
| 241 | : "r" (addr), "i" (-EFAULT)) |
| 242 | |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 243 | #define __raw_get_mem(ldr, x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 244 | do { \ |
| 245 | unsigned long __gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 246 | switch (sizeof(*(ptr))) { \ |
| 247 | case 1: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 248 | __get_mem_asm(ldr "b", "%w", __gu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 249 | break; \ |
| 250 | case 2: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 251 | __get_mem_asm(ldr "h", "%w", __gu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 252 | break; \ |
| 253 | case 4: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 254 | __get_mem_asm(ldr, "%w", __gu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 255 | break; \ |
| 256 | case 8: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 257 | __get_mem_asm(ldr, "%x", __gu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 258 | break; \ |
| 259 | default: \ |
| 260 | BUILD_BUG(); \ |
| 261 | } \ |
Michael S. Tsirkin | 58fff51 | 2014-12-12 01:56:04 +0200 | [diff] [blame] | 262 | (x) = (__force __typeof__(*(ptr)))__gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 263 | } while (0) |
| 264 | |
Mark Rutland | f253d82 | 2020-12-02 13:15:52 +0000 | [diff] [blame] | 265 | #define __raw_get_user(x, ptr, err) \ |
| 266 | do { \ |
| 267 | __chk_user_ptr(ptr); \ |
| 268 | uaccess_enable_not_uao(); \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 269 | __raw_get_mem("ldtr", x, ptr, err); \ |
Mark Rutland | f253d82 | 2020-12-02 13:15:52 +0000 | [diff] [blame] | 270 | uaccess_disable_not_uao(); \ |
| 271 | } while (0) |
| 272 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 273 | #define __get_user_error(x, ptr, err) \ |
| 274 | do { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 275 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 276 | might_fault(); \ |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 277 | if (access_ok(__p, sizeof(*__p))) { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 278 | __p = uaccess_mask_ptr(__p); \ |
Catalin Marinas | 3cd0ddb | 2019-03-01 14:19:06 +0000 | [diff] [blame] | 279 | __raw_get_user((x), __p, (err)); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 280 | } else { \ |
Al Viro | 8cfb347 | 2020-05-22 15:23:21 +0100 | [diff] [blame] | 281 | (x) = (__force __typeof__(x))0; (err) = -EFAULT; \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 282 | } \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 283 | } while (0) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 284 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 285 | #define __get_user(x, ptr) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 286 | ({ \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 287 | int __gu_err = 0; \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 288 | __get_user_error((x), (ptr), __gu_err); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 289 | __gu_err; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 290 | }) |
| 291 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 292 | #define get_user __get_user |
| 293 | |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 294 | #define __get_kernel_nofault(dst, src, type, err_label) \ |
| 295 | do { \ |
| 296 | int __gkn_err = 0; \ |
| 297 | \ |
| 298 | __raw_get_mem("ldr", *((type *)(dst)), \ |
| 299 | (__force type *)(src), __gkn_err); \ |
| 300 | if (unlikely(__gkn_err)) \ |
| 301 | goto err_label; \ |
| 302 | } while (0) |
| 303 | |
| 304 | #define __put_mem_asm(store, reg, x, addr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 305 | asm volatile( \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 306 | "1: " store " " reg "1, [%2]\n" \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 307 | "2:\n" \ |
| 308 | " .section .fixup,\"ax\"\n" \ |
| 309 | " .align 2\n" \ |
| 310 | "3: mov %w0, %3\n" \ |
| 311 | " b 2b\n" \ |
| 312 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 313 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 314 | : "+r" (err) \ |
| 315 | : "r" (x), "r" (addr), "i" (-EFAULT)) |
| 316 | |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 317 | #define __raw_put_mem(str, x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 318 | do { \ |
| 319 | __typeof__(*(ptr)) __pu_val = (x); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 320 | switch (sizeof(*(ptr))) { \ |
| 321 | case 1: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 322 | __put_mem_asm(str "b", "%w", __pu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 323 | break; \ |
| 324 | case 2: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 325 | __put_mem_asm(str "h", "%w", __pu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 326 | break; \ |
| 327 | case 4: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 328 | __put_mem_asm(str, "%w", __pu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 329 | break; \ |
| 330 | case 8: \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 331 | __put_mem_asm(str, "%x", __pu_val, (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 332 | break; \ |
| 333 | default: \ |
| 334 | BUILD_BUG(); \ |
| 335 | } \ |
Mark Rutland | f253d82 | 2020-12-02 13:15:52 +0000 | [diff] [blame] | 336 | } while (0) |
| 337 | |
| 338 | #define __raw_put_user(x, ptr, err) \ |
| 339 | do { \ |
| 340 | __chk_user_ptr(ptr); \ |
| 341 | uaccess_enable_not_uao(); \ |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 342 | __raw_put_mem("sttr", x, ptr, err); \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 343 | uaccess_disable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 344 | } while (0) |
| 345 | |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 346 | #define __put_user_error(x, ptr, err) \ |
| 347 | do { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 348 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 349 | might_fault(); \ |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 350 | if (access_ok(__p, sizeof(*__p))) { \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 351 | __p = uaccess_mask_ptr(__p); \ |
Catalin Marinas | 3cd0ddb | 2019-03-01 14:19:06 +0000 | [diff] [blame] | 352 | __raw_put_user((x), __p, (err)); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 353 | } else { \ |
| 354 | (err) = -EFAULT; \ |
| 355 | } \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 356 | } while (0) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 357 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 358 | #define __put_user(x, ptr) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 359 | ({ \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 360 | int __pu_err = 0; \ |
Julien Thierry | 13e4cdd | 2019-01-15 13:58:26 +0000 | [diff] [blame] | 361 | __put_user_error((x), (ptr), __pu_err); \ |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 362 | __pu_err; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 363 | }) |
| 364 | |
Will Deacon | 8462408 | 2018-02-05 15:34:22 +0000 | [diff] [blame] | 365 | #define put_user __put_user |
| 366 | |
Mark Rutland | fc703d8 | 2020-12-02 13:15:53 +0000 | [diff] [blame] | 367 | #define __put_kernel_nofault(dst, src, type, err_label) \ |
| 368 | do { \ |
| 369 | int __pkn_err = 0; \ |
| 370 | \ |
| 371 | __raw_put_mem("str", *((type *)(src)), \ |
| 372 | (__force type *)(dst), __pkn_err); \ |
| 373 | if (unlikely(__pkn_err)) \ |
| 374 | goto err_label; \ |
| 375 | } while(0) |
| 376 | |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 377 | extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 378 | #define raw_copy_from_user(to, from, n) \ |
| 379 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 380 | unsigned long __acfu_ret; \ |
| 381 | uaccess_enable_not_uao(); \ |
| 382 | __acfu_ret = __arch_copy_from_user((to), \ |
| 383 | __uaccess_mask_ptr(from), (n)); \ |
| 384 | uaccess_disable_not_uao(); \ |
| 385 | __acfu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 386 | }) |
| 387 | |
Yang Shi | bffe1ba | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 388 | extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 389 | #define raw_copy_to_user(to, from, n) \ |
| 390 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 391 | unsigned long __actu_ret; \ |
| 392 | uaccess_enable_not_uao(); \ |
| 393 | __actu_ret = __arch_copy_to_user(__uaccess_mask_ptr(to), \ |
| 394 | (from), (n)); \ |
| 395 | uaccess_disable_not_uao(); \ |
| 396 | __actu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 397 | }) |
| 398 | |
| 399 | extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); |
| 400 | #define raw_copy_in_user(to, from, n) \ |
| 401 | ({ \ |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 402 | unsigned long __aciu_ret; \ |
| 403 | uaccess_enable_not_uao(); \ |
| 404 | __aciu_ret = __arch_copy_in_user(__uaccess_mask_ptr(to), \ |
| 405 | __uaccess_mask_ptr(from), (n)); \ |
| 406 | uaccess_disable_not_uao(); \ |
| 407 | __aciu_ret; \ |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 408 | }) |
| 409 | |
Al Viro | 92430da | 2017-03-21 08:40:57 -0400 | [diff] [blame] | 410 | #define INLINE_COPY_TO_USER |
| 411 | #define INLINE_COPY_FROM_USER |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 412 | |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 413 | extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); |
| 414 | static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 415 | { |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 416 | if (access_ok(to, n)) { |
| 417 | uaccess_enable_not_uao(); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 418 | n = __arch_clear_user(__uaccess_mask_ptr(to), n); |
Pavel Tatashin | e50be64 | 2019-11-20 12:07:40 -0500 | [diff] [blame] | 419 | uaccess_disable_not_uao(); |
| 420 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 421 | return n; |
| 422 | } |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 423 | #define clear_user __clear_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 424 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 425 | extern long strncpy_from_user(char *dest, const char __user *src, long count); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 426 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 427 | extern __must_check long strnlen_user(const char __user *str, long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 428 | |
Robin Murphy | 5d7bdeb | 2017-07-25 11:55:43 +0100 | [diff] [blame] | 429 | #ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE |
| 430 | struct page; |
| 431 | void memcpy_page_flushcache(char *to, struct page *page, size_t offset, size_t len); |
| 432 | extern unsigned long __must_check __copy_user_flushcache(void *to, const void __user *from, unsigned long n); |
| 433 | |
| 434 | static inline int __copy_from_user_flushcache(void *dst, const void __user *src, unsigned size) |
| 435 | { |
| 436 | kasan_check_write(dst, size); |
Will Deacon | f71c2ff | 2018-02-05 15:34:23 +0000 | [diff] [blame] | 437 | return __copy_user_flushcache(dst, __uaccess_mask_ptr(src), size); |
Robin Murphy | 5d7bdeb | 2017-07-25 11:55:43 +0100 | [diff] [blame] | 438 | } |
| 439 | #endif |
| 440 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 441 | #endif /* __ASM_UACCESS_H */ |