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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 39ac5ba51b69a77a30d2e783aed02ec73c9f6d70 / . / arch / arm / boot / dts / imx28.dtsi
blob: f8e9b20f69820c6948bd84b11a14166db6b4bdd3 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
16 interrupt-parent = <&icoll>;
17
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]18 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]26 saif0 = &saif0;
27 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]33 spi0 = &ssp1;
34 spi1 = &ssp2;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]35 };
36
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]37 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]44 };
45 };
46
47 apb@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x80000>;
52 ranges;
53
54 apbh@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x3c900>;
59 ranges;
60
61 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]62 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
66 };
67
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]68 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]69 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]70 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]71 dmas = <&dma_apbh 12>;
72 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]73 status = "disabled";
74 };
75
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]76 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]77 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]78 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]79 interrupts = <82 83 84 85
80 88 88 88 88
81 88 88 88 88
82 87 86 0 0>;
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
87 #dma-cells = <1>;
88 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]89 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]90 };
91
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]92 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]93 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]94 interrupts = <27>;
95 status = "disabled";
96 };
97
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]98 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
101 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]103 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]104 interrupts = <41>;
105 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]106 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]107 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]108 dmas = <&dma_apbh 4>;
109 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]110 status = "disabled";
111 };
112
113 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]114 #address-cells = <1>;
115 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]116 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]117 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]118 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]121 status = "disabled";
122 };
123
124 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]127 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]128 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]129 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]130 dmas = <&dma_apbh 1>;
131 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]132 status = "disabled";
133 };
134
135 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]136 #address-cells = <1>;
137 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]138 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]139 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]140 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]141 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]143 status = "disabled";
144 };
145
146 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]147 #address-cells = <1>;
148 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]149 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]150 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]151 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]152 dmas = <&dma_apbh 3>;
153 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]154 status = "disabled";
155 };
156
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]157 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]158 #address-cells = <1>;
159 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]160 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]161 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]162
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]163 gpio0: gpio@0 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <127>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio1: gpio@1 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <126>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 gpio2: gpio@2 {
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupts = <125>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio3: gpio@3 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192 interrupts = <124>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpio4: gpio@4 {
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
201 interrupts = <123>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]208 duart_pins_a: duart@0 {
209 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]210 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]213 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]214 fsl,drive-strength = <MXS_DRIVE_4mA>;
215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
216 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]217 };
218
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]219 duart_pins_b: duart@1 {
220 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]221 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]224 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]225 fsl,drive-strength = <MXS_DRIVE_4mA>;
226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
227 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]228 };
229
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]230 duart_4pins_a: duart-4pins@0 {
231 reg = <0>;
232 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]237 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]238 fsl,drive-strength = <MXS_DRIVE_4mA>;
239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
240 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]241 };
242
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]243 gpmi_pins_a: gpmi-nand@0 {
244 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]245 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]261 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]262 fsl,drive-strength = <MXS_DRIVE_4mA>;
263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
264 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]265 };
266
267 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]268 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]272 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]273 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]274 };
275
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]276 auart0_pins_a: auart0@0 {
277 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]278 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]283 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]284 fsl,drive-strength = <MXS_DRIVE_4mA>;
285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
286 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]287 };
288
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]289 auart0_2pins_a: auart0-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]294 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]295 fsl,drive-strength = <MXS_DRIVE_4mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]298 };
299
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]300 auart1_pins_a: auart1@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]307 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]311 };
312
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]313 auart1_2pins_a: auart1-2pins@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]318 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]319 fsl,drive-strength = <MXS_DRIVE_4mA>;
320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
321 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]322 };
323
324 auart2_2pins_a: auart2-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]329 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]330 fsl,drive-strength = <MXS_DRIVE_4mA>;
331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
332 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]333 };
334
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]335 auart2_2pins_b: auart2-2pins@1 {
336 reg = <1>;
337 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]340 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]341 fsl,drive-strength = <MXS_DRIVE_4mA>;
342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
343 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]344 };
345
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]346 auart3_pins_a: auart3@0 {
347 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]348 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]349 MX28_PAD_AUART3_RX__AUART3_RX
350 MX28_PAD_AUART3_TX__AUART3_TX
351 MX28_PAD_AUART3_CTS__AUART3_CTS
352 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]353 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]357 };
358
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]359 auart3_2pins_a: auart3-2pins@0 {
360 reg = <0>;
361 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]362 MX28_PAD_SSP2_MISO__AUART3_RX
363 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]364 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]365 fsl,drive-strength = <MXS_DRIVE_4mA>;
366 fsl,voltage = <MXS_VOLTAGE_HIGH>;
367 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]368 };
369
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]370 auart3_2pins_b: auart3-2pins@1 {
371 reg = <1>;
372 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]373 MX28_PAD_AUART3_RX__AUART3_RX
374 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]375 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]376 fsl,drive-strength = <MXS_DRIVE_4mA>;
377 fsl,voltage = <MXS_VOLTAGE_HIGH>;
378 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]379 };
380
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]381 auart4_2pins_a: auart4@0 {
382 reg = <0>;
383 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]384 MX28_PAD_SSP3_SCK__AUART4_TX
385 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]386 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]390 };
391
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]392 mac0_pins_a: mac0@0 {
393 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]394 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]395 MX28_PAD_ENET0_MDC__ENET0_MDC
396 MX28_PAD_ENET0_MDIO__ENET0_MDIO
397 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
398 MX28_PAD_ENET0_RXD0__ENET0_RXD0
399 MX28_PAD_ENET0_RXD1__ENET0_RXD1
400 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
401 MX28_PAD_ENET0_TXD0__ENET0_TXD0
402 MX28_PAD_ENET0_TXD1__ENET0_TXD1
403 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]404 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]405 fsl,drive-strength = <MXS_DRIVE_8mA>;
406 fsl,voltage = <MXS_VOLTAGE_HIGH>;
407 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]408 };
409
410 mac1_pins_a: mac1@0 {
411 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]412 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]413 MX28_PAD_ENET0_CRS__ENET1_RX_EN
414 MX28_PAD_ENET0_RXD2__ENET1_RXD0
415 MX28_PAD_ENET0_RXD3__ENET1_RXD1
416 MX28_PAD_ENET0_COL__ENET1_TX_EN
417 MX28_PAD_ENET0_TXD2__ENET1_TXD0
418 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]419 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]420 fsl,drive-strength = <MXS_DRIVE_8mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]423 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]424
425 mmc0_8bit_pins_a: mmc0-8bit@0 {
426 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]427 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]428 MX28_PAD_SSP0_DATA0__SSP0_D0
429 MX28_PAD_SSP0_DATA1__SSP0_D1
430 MX28_PAD_SSP0_DATA2__SSP0_D2
431 MX28_PAD_SSP0_DATA3__SSP0_D3
432 MX28_PAD_SSP0_DATA4__SSP0_D4
433 MX28_PAD_SSP0_DATA5__SSP0_D5
434 MX28_PAD_SSP0_DATA6__SSP0_D6
435 MX28_PAD_SSP0_DATA7__SSP0_D7
436 MX28_PAD_SSP0_CMD__SSP0_CMD
437 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
438 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]439 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]440 fsl,drive-strength = <MXS_DRIVE_8mA>;
441 fsl,voltage = <MXS_VOLTAGE_HIGH>;
442 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]443 };
444
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]445 mmc0_4bit_pins_a: mmc0-4bit@0 {
446 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]447 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]448 MX28_PAD_SSP0_DATA0__SSP0_D0
449 MX28_PAD_SSP0_DATA1__SSP0_D1
450 MX28_PAD_SSP0_DATA2__SSP0_D2
451 MX28_PAD_SSP0_DATA3__SSP0_D3
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]455 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]459 };
460
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]461 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]462 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]463 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]464 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]465 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]466 };
467
468 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]469 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]470 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]471 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]472 fsl,drive-strength = <MXS_DRIVE_12mA>;
473 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]474 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]475
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]476 mmc2_4bit_pins_a: mmc2-4bit@0 {
477 reg = <0>;
478 fsl,pinmux-ids = <
479 MX28_PAD_SSP0_DATA4__SSP2_D0
480 MX28_PAD_SSP1_SCK__SSP2_D1
481 MX28_PAD_SSP1_CMD__SSP2_D2
482 MX28_PAD_SSP0_DATA5__SSP2_D3
483 MX28_PAD_SSP0_DATA6__SSP2_CMD
484 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
485 MX28_PAD_SSP0_DATA7__SSP2_SCK
486 >;
487 fsl,drive-strength = <MXS_DRIVE_8mA>;
488 fsl,voltage = <MXS_VOLTAGE_HIGH>;
489 fsl,pull-up = <MXS_PULL_ENABLE>;
490 };
491
492 mmc2_cd_cfg: mmc2-cd-cfg {
493 fsl,pinmux-ids = <
494 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
495 >;
496 fsl,pull-up = <MXS_PULL_DISABLE>;
497 };
498
499 mmc2_sck_cfg: mmc2-sck-cfg {
500 fsl,pinmux-ids = <
501 MX28_PAD_SSP0_DATA7__SSP2_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_12mA>;
504 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]505 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]506
507 i2c0_pins_a: i2c0@0 {
508 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]509 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]510 MX28_PAD_I2C0_SCL__I2C0_SCL
511 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]512 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]513 fsl,drive-strength = <MXS_DRIVE_8mA>;
514 fsl,voltage = <MXS_VOLTAGE_HIGH>;
515 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]516 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]517
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]518 i2c0_pins_b: i2c0@1 {
519 reg = <1>;
520 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]521 MX28_PAD_AUART0_RX__I2C0_SCL
522 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]523 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]524 fsl,drive-strength = <MXS_DRIVE_8mA>;
525 fsl,voltage = <MXS_VOLTAGE_HIGH>;
526 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]527 };
528
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]529 i2c1_pins_a: i2c1@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]532 MX28_PAD_PWM0__I2C1_SCL
533 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]534 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]535 fsl,drive-strength = <MXS_DRIVE_8mA>;
536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
537 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]538 };
539
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]540 saif0_pins_a: saif0@0 {
541 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]542 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]543 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
544 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
545 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
546 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]547 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]548 fsl,drive-strength = <MXS_DRIVE_12mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]551 };
552
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]553 saif0_pins_b: saif0@1 {
554 reg = <1>;
555 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]556 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
557 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
558 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]559 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]560 fsl,drive-strength = <MXS_DRIVE_12mA>;
561 fsl,voltage = <MXS_VOLTAGE_HIGH>;
562 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]563 };
564
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]565 saif1_pins_a: saif1@0 {
566 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]567 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]568 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]569 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]570 fsl,drive-strength = <MXS_DRIVE_12mA>;
571 fsl,voltage = <MXS_VOLTAGE_HIGH>;
572 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]573 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]574
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]575 pwm0_pins_a: pwm0@0 {
576 reg = <0>;
577 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]578 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]579 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]580 fsl,drive-strength = <MXS_DRIVE_4mA>;
581 fsl,voltage = <MXS_VOLTAGE_HIGH>;
582 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]583 };
584
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]585 pwm2_pins_a: pwm2@0 {
586 reg = <0>;
587 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]588 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]589 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]590 fsl,drive-strength = <MXS_DRIVE_4mA>;
591 fsl,voltage = <MXS_VOLTAGE_HIGH>;
592 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]593 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]594
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]595 pwm3_pins_a: pwm3@0 {
596 reg = <0>;
597 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]598 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]599 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]600 fsl,drive-strength = <MXS_DRIVE_4mA>;
601 fsl,voltage = <MXS_VOLTAGE_HIGH>;
602 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]603 };
604
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]605 pwm3_pins_b: pwm3@1 {
606 reg = <1>;
607 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]608 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]609 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]610 fsl,drive-strength = <MXS_DRIVE_4mA>;
611 fsl,voltage = <MXS_VOLTAGE_HIGH>;
612 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]613 };
614
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]615 pwm4_pins_a: pwm4@0 {
616 reg = <0>;
617 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]618 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]619 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]620 fsl,drive-strength = <MXS_DRIVE_4mA>;
621 fsl,voltage = <MXS_VOLTAGE_HIGH>;
622 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]623 };
624
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]625 lcdif_24bit_pins_a: lcdif-24bit@0 {
626 reg = <0>;
627 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]628 MX28_PAD_LCD_D00__LCD_D0
629 MX28_PAD_LCD_D01__LCD_D1
630 MX28_PAD_LCD_D02__LCD_D2
631 MX28_PAD_LCD_D03__LCD_D3
632 MX28_PAD_LCD_D04__LCD_D4
633 MX28_PAD_LCD_D05__LCD_D5
634 MX28_PAD_LCD_D06__LCD_D6
635 MX28_PAD_LCD_D07__LCD_D7
636 MX28_PAD_LCD_D08__LCD_D8
637 MX28_PAD_LCD_D09__LCD_D9
638 MX28_PAD_LCD_D10__LCD_D10
639 MX28_PAD_LCD_D11__LCD_D11
640 MX28_PAD_LCD_D12__LCD_D12
641 MX28_PAD_LCD_D13__LCD_D13
642 MX28_PAD_LCD_D14__LCD_D14
643 MX28_PAD_LCD_D15__LCD_D15
644 MX28_PAD_LCD_D16__LCD_D16
645 MX28_PAD_LCD_D17__LCD_D17
646 MX28_PAD_LCD_D18__LCD_D18
647 MX28_PAD_LCD_D19__LCD_D19
648 MX28_PAD_LCD_D20__LCD_D20
649 MX28_PAD_LCD_D21__LCD_D21
650 MX28_PAD_LCD_D22__LCD_D22
651 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]652 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]653 fsl,drive-strength = <MXS_DRIVE_4mA>;
654 fsl,voltage = <MXS_VOLTAGE_HIGH>;
655 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]656 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]657
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]658 lcdif_16bit_pins_a: lcdif-16bit@0 {
659 reg = <0>;
660 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]661 MX28_PAD_LCD_D00__LCD_D0
662 MX28_PAD_LCD_D01__LCD_D1
663 MX28_PAD_LCD_D02__LCD_D2
664 MX28_PAD_LCD_D03__LCD_D3
665 MX28_PAD_LCD_D04__LCD_D4
666 MX28_PAD_LCD_D05__LCD_D5
667 MX28_PAD_LCD_D06__LCD_D6
668 MX28_PAD_LCD_D07__LCD_D7
669 MX28_PAD_LCD_D08__LCD_D8
670 MX28_PAD_LCD_D09__LCD_D9
671 MX28_PAD_LCD_D10__LCD_D10
672 MX28_PAD_LCD_D11__LCD_D11
673 MX28_PAD_LCD_D12__LCD_D12
674 MX28_PAD_LCD_D13__LCD_D13
675 MX28_PAD_LCD_D14__LCD_D14
676 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]677 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]678 fsl,drive-strength = <MXS_DRIVE_4mA>;
679 fsl,voltage = <MXS_VOLTAGE_HIGH>;
680 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]681 };
682
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]683 lcdif_sync_pins_a: lcdif-sync@0 {
684 reg = <0>;
685 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]686 MX28_PAD_LCD_RS__LCD_DOTCLK
687 MX28_PAD_LCD_CS__LCD_ENABLE
688 MX28_PAD_LCD_RD_E__LCD_VSYNC
689 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]690 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]691 fsl,drive-strength = <MXS_DRIVE_4mA>;
692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
693 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]694 };
695
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]696 can0_pins_a: can0@0 {
697 reg = <0>;
698 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]699 MX28_PAD_GPMI_RDY2__CAN0_TX
700 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]701 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]702 fsl,drive-strength = <MXS_DRIVE_4mA>;
703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
704 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]705 };
706
707 can1_pins_a: can1@0 {
708 reg = <0>;
709 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]710 MX28_PAD_GPMI_CE2N__CAN1_TX
711 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]712 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]713 fsl,drive-strength = <MXS_DRIVE_4mA>;
714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
715 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]716 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]717
718 spi2_pins_a: spi2@0 {
719 reg = <0>;
720 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]721 MX28_PAD_SSP2_SCK__SSP2_SCK
722 MX28_PAD_SSP2_MOSI__SSP2_CMD
723 MX28_PAD_SSP2_MISO__SSP2_D0
724 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]725 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]726 fsl,drive-strength = <MXS_DRIVE_8mA>;
727 fsl,voltage = <MXS_VOLTAGE_HIGH>;
728 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]729 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]730
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]731 spi3_pins_a: spi3@0 {
732 reg = <0>;
733 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]734 MX28_PAD_AUART2_RX__SSP3_D4
735 MX28_PAD_AUART2_TX__SSP3_D5
736 MX28_PAD_SSP3_SCK__SSP3_SCK
737 MX28_PAD_SSP3_MOSI__SSP3_CMD
738 MX28_PAD_SSP3_MISO__SSP3_D0
739 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]740 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]741 fsl,drive-strength = <MXS_DRIVE_8mA>;
742 fsl,voltage = <MXS_VOLTAGE_HIGH>;
743 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]744 };
745
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]746 usbphy0_pins_a: usbphy0@0 {
747 reg = <0>;
748 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]749 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]750 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]751 fsl,drive-strength = <MXS_DRIVE_12mA>;
752 fsl,voltage = <MXS_VOLTAGE_HIGH>;
753 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]754 };
755
756 usbphy0_pins_b: usbphy0@1 {
757 reg = <1>;
758 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]759 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]760 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]761 fsl,drive-strength = <MXS_DRIVE_12mA>;
762 fsl,voltage = <MXS_VOLTAGE_HIGH>;
763 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]764 };
765
766 usbphy1_pins_a: usbphy1@0 {
767 reg = <0>;
768 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]769 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]770 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]771 fsl,drive-strength = <MXS_DRIVE_12mA>;
772 fsl,voltage = <MXS_VOLTAGE_HIGH>;
773 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]774 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]775
776 usb0_id_pins_a: usb0id@0 {
777 reg = <0>;
778 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]779 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]780 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]781 fsl,drive-strength = <MXS_DRIVE_12mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]784 };
785 };
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]786
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]787 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]788 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]789 reg = <0x8001c000 0x2000>;
790 interrupts = <89>;
791 status = "disabled";
792 };
793
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]794 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]795 reg = <0x80022000 0x2000>;
796 status = "disabled";
797 };
798
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]799 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]800 compatible = "fsl,imx28-dma-apbx";
801 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]802 interrupts = <78 79 66 0
803 80 81 68 69
804 70 71 72 73
805 74 75 76 77>;
806 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
807 "saif0", "saif1", "i2c0", "i2c1",
808 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
809 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
810 #dma-cells = <1>;
811 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]812 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]813 };
814
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]815 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]816 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]817 reg = <0x80028000 0x2000>;
818 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]819 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]820 };
821
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]822 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]823 reg = <0x8002a000 0x2000>;
824 interrupts = <39>;
825 status = "disabled";
826 };
827
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]828 ocotp: ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800[diff] [blame]829 compatible = "fsl,ocotp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]830 reg = <0x8002c000 0x2000>;
831 status = "disabled";
832 };
833
834 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]835 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]836 status = "disabled";
837 };
838
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]839 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]840 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]841 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]842 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]843 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]844 dmas = <&dma_apbh 13>;
845 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]846 status = "disabled";
847 };
848
849 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]850 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]851 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]852 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]853 clocks = <&clks 58>, <&clks 58>;
854 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]855 status = "disabled";
856 };
857
858 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]859 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]860 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]861 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]862 clocks = <&clks 59>, <&clks 59>;
863 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]864 status = "disabled";
865 };
866
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]867 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]868 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]869 status = "disabled";
870 };
871
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]872 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]873 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]874 status = "disabled";
875 };
876
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]877 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]878 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]879 status = "disabled";
880 };
881
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]882 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]883 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]884 status = "disabled";
885 };
886
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]887 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]888 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]889 status = "disabled";
890 };
891
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]892 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]893 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]894 status = "disabled";
895 };
896
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]897 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]898 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]899 status = "disabled";
900 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]901 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]902
903 apbx@80040000 {
904 compatible = "simple-bus";
905 #address-cells = <1>;
906 #size-cells = <1>;
907 reg = <0x80040000 0x40000>;
908 ranges;
909
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]910 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]911 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]912 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]913 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]914 };
915
916 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]917 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]918 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]919 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]920 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]921 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]922 dmas = <&dma_apbx 4>;
923 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]924 status = "disabled";
925 };
926
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]927 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]928 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]929 status = "disabled";
930 };
931
932 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]933 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]934 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]935 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]936 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]937 dmas = <&dma_apbx 5>;
938 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]939 status = "disabled";
940 };
941
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]942 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]943 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]944 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]945 interrupts = <10 14 15 16 17 18 19
946 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]947 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]948 clocks = <&clks 41>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]949 };
950
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]951 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]952 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]953 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]954 dmas = <&dma_apbx 2>;
955 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]956 status = "disabled";
957 };
958
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]959 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]960 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]961 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]962 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]963 };
964
965 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]966 #address-cells = <1>;
967 #size-cells = <0>;
968 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]969 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]970 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]971 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]972 dmas = <&dma_apbx 6>;
973 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]974 status = "disabled";
975 };
976
977 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]978 #address-cells = <1>;
979 #size-cells = <0>;
980 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]981 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]982 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]983 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]984 dmas = <&dma_apbx 7>;
985 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]986 status = "disabled";
987 };
988
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]989 pwm: pwm@80064000 {
990 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]991 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]992 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]993 #pwm-cells = <2>;
994 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]995 status = "disabled";
996 };
997
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]998 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]999 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1000 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1001 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1002 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1003 };
1004
1005 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1006 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1007 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1008 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1009 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1010 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1011 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1012 status = "disabled";
1013 };
1014
1015 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1016 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1017 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1018 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1019 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1020 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1021 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1022 status = "disabled";
1023 };
1024
1025 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1026 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1027 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1028 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1029 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1030 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1031 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1032 status = "disabled";
1033 };
1034
1035 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1036 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1037 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1038 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1039 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1040 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1041 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1042 status = "disabled";
1043 };
1044
1045 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1046 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1047 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1048 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1049 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1050 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1051 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1052 status = "disabled";
1053 };
1054
1055 duart: serial@80074000 {
1056 compatible = "arm,pl011", "arm,primecell";
1057 reg = <0x80074000 0x1000>;
1058 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1059 clocks = <&clks 45>, <&clks 26>;
1060 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1061 status = "disabled";
1062 };
1063
1064 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1065 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1066 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1067 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1068 status = "disabled";
1069 };
1070
1071 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1072 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1073 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1074 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1075 status = "disabled";
1076 };
1077 };
1078 };
1079
1080 ahb@80080000 {
1081 compatible = "simple-bus";
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 reg = <0x80080000 0x80000>;
1085 ranges;
1086
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1087 usb0: usb@80080000 {
1088 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1089 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1090 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1091 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1092 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1093 status = "disabled";
1094 };
1095
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1096 usb1: usb@80090000 {
1097 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1098 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1099 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1100 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1101 fsl,usbphy = <&usbphy1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1102 status = "disabled";
1103 };
1104
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1105 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1106 reg = <0x800c0000 0x10000>;
1107 status = "disabled";
1108 };
1109
1110 mac0: ethernet@800f0000 {
1111 compatible = "fsl,imx28-fec";
1112 reg = <0x800f0000 0x4000>;
1113 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1114 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1115 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1116 status = "disabled";
1117 };
1118
1119 mac1: ethernet@800f4000 {
1120 compatible = "fsl,imx28-fec";
1121 reg = <0x800f4000 0x4000>;
1122 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1123 clocks = <&clks 57>, <&clks 57>;
1124 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1125 status = "disabled";
1126 };
1127
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1128 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1129 reg = <0x800f8000 0x8000>;
1130 status = "disabled";
1131 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1132 };
1133};