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Catalin Marinas0be73202012-03-05 11:49:26 +00001/*
2 * Based on arch/arm/kernel/asm-offsets.c
3 *
4 * Copyright (C) 1995-2003 Russell King
5 * 2001-2002 Keith Owens
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
James Morsef5df2692018-01-08 15:38:12 +000021#include <linux/arm_sdei.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000022#include <linux/sched.h>
23#include <linux/mm.h>
24#include <linux/dma-mapping.h>
Marc Zyngierc3eb5b12013-07-04 13:34:32 +010025#include <linux/kvm_host.h>
Ard Biesheuvel24534b32018-03-29 15:13:23 +020026#include <linux/preempt.h>
James Morse82869ac2016-04-27 17:47:12 +010027#include <linux/suspend.h>
Suzuki K Poulose116c81f2016-09-09 14:07:16 +010028#include <asm/cpufeature.h>
Will Deacon51a00482017-11-14 14:14:17 +000029#include <asm/fixmap.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000030#include <asm/thread_info.h>
31#include <asm/memory.h>
Lorenzo Pieralisi95322522013-07-22 12:22:13 +010032#include <asm/smp_plat.h>
33#include <asm/suspend.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000034#include <asm/vdso_datapage.h>
35#include <linux/kbuild.h>
Jens Wiklander14457452016-01-04 15:44:32 +010036#include <linux/arm-smccc.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000037
38int main(void)
39{
40 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
41 BLANK();
Mark Rutlandc02433d2016-11-03 20:23:13 +000042 DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
43 DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count));
44 DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit));
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010045#ifdef CONFIG_ARM64_SW_TTBR0_PAN
46 DEFINE(TSK_TI_TTBR0, offsetof(struct task_struct, thread_info.ttbr0));
47#endif
Mark Rutlandc02433d2016-11-03 20:23:13 +000048 DEFINE(TSK_STACK, offsetof(struct task_struct, stack));
Ard Biesheuvel0a1213f2018-12-12 13:08:44 +010049#ifdef CONFIG_STACKPROTECTOR
50 DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
51#endif
Catalin Marinas0be73202012-03-05 11:49:26 +000052 BLANK();
53 DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
54 BLANK();
55 DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
Catalin Marinas0be73202012-03-05 11:49:26 +000056 DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
Catalin Marinas0be73202012-03-05 11:49:26 +000057 DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
Catalin Marinas0be73202012-03-05 11:49:26 +000058 DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
William Cohenda6a9122016-07-08 12:35:52 -040059 DEFINE(S_X8, offsetof(struct pt_regs, regs[8]));
60 DEFINE(S_X10, offsetof(struct pt_regs, regs[10]));
61 DEFINE(S_X12, offsetof(struct pt_regs, regs[12]));
62 DEFINE(S_X14, offsetof(struct pt_regs, regs[14]));
63 DEFINE(S_X16, offsetof(struct pt_regs, regs[16]));
64 DEFINE(S_X18, offsetof(struct pt_regs, regs[18]));
65 DEFINE(S_X20, offsetof(struct pt_regs, regs[20]));
66 DEFINE(S_X22, offsetof(struct pt_regs, regs[22]));
67 DEFINE(S_X24, offsetof(struct pt_regs, regs[24]));
68 DEFINE(S_X26, offsetof(struct pt_regs, regs[26]));
69 DEFINE(S_X28, offsetof(struct pt_regs, regs[28]));
Catalin Marinas0be73202012-03-05 11:49:26 +000070 DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
71 DEFINE(S_SP, offsetof(struct pt_regs, sp));
Catalin Marinas0be73202012-03-05 11:49:26 +000072 DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
73 DEFINE(S_PC, offsetof(struct pt_regs, pc));
Catalin Marinas0be73202012-03-05 11:49:26 +000074 DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
James Morsee19a6ee2016-06-20 18:28:01 +010075 DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
Julien Thierry133d0512019-01-31 14:58:46 +000076 DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
Ard Biesheuvel73267492017-07-22 18:45:33 +010077 DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
Catalin Marinas0be73202012-03-05 11:49:26 +000078 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
79 BLANK();
Will Deacon5aec7152015-10-06 18:46:24 +010080 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
Catalin Marinas0be73202012-03-05 11:49:26 +000081 BLANK();
82 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
83 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
84 BLANK();
85 DEFINE(VM_EXEC, VM_EXEC);
86 BLANK();
87 DEFINE(PAGE_SZ, PAGE_SIZE);
88 BLANK();
Catalin Marinas0be73202012-03-05 11:49:26 +000089 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
90 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
91 BLANK();
Ard Biesheuvel24534b32018-03-29 15:13:23 +020092 DEFINE(PREEMPT_DISABLE_OFFSET, PREEMPT_DISABLE_OFFSET);
93 BLANK();
Catalin Marinas0be73202012-03-05 11:49:26 +000094 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
95 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
Kevin Brodsky49eea432016-07-12 11:24:00 +010096 DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW);
Catalin Marinas0be73202012-03-05 11:49:26 +000097 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
98 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
99 DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
100 DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
101 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
102 BLANK();
103 DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
Kevin Brodsky49eea432016-07-12 11:24:00 +0100104 DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000105 DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000106 DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
107 DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
108 DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000109 DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
Kevin Brodsky49eea432016-07-12 11:24:00 +0100110 DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult));
Catalin Marinas0be73202012-03-05 11:49:26 +0000111 DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
112 DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
Catalin Marinas0be73202012-03-05 11:49:26 +0000113 DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
114 BLANK();
115 DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000116 DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000117 BLANK();
118 DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
119 DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
Marc Zyngier55c74012012-12-10 16:40:18 +0000120 BLANK();
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000121 DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack));
Mark Rutlandc02433d2016-11-03 20:23:13 +0000122 DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task));
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000123 BLANK();
Marc Zyngier55c74012012-12-10 16:40:18 +0000124#ifdef CONFIG_KVM_ARM_HOST
125 DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
James Morse0067df42018-01-15 19:39:05 +0000126 DEFINE(VCPU_FAULT_DISR, offsetof(struct kvm_vcpu, arch.fault.disr_el1));
Marc Zyngierb4f18c02018-05-29 13:11:17 +0100127 DEFINE(VCPU_WORKAROUND_FLAGS, offsetof(struct kvm_vcpu, arch.workaround_flags));
Mark Rutland384b40c2019-04-23 10:12:35 +0530128 DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
Marc Zyngier55c74012012-12-10 16:40:18 +0000129 DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
Mark Rutland384b40c2019-04-23 10:12:35 +0530130 DEFINE(CPU_APIAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APIAKEYLO_EL1]));
131 DEFINE(CPU_APIBKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APIBKEYLO_EL1]));
132 DEFINE(CPU_APDAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APDAKEYLO_EL1]));
133 DEFINE(CPU_APDBKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APDBKEYLO_EL1]));
134 DEFINE(CPU_APGAKEYLO_EL1, offsetof(struct kvm_cpu_context, sys_regs[APGAKEYLO_EL1]));
Marc Zyngier55c74012012-12-10 16:40:18 +0000135 DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
Christoffer Dall4464e212017-10-08 17:01:56 +0200136 DEFINE(HOST_CONTEXT_VCPU, offsetof(struct kvm_cpu_context, __hyp_running_vcpu));
Marc Zyngier55c74012012-12-10 16:40:18 +0000137#endif
Lorenzo Pieralisiaf3cfdb2015-01-26 18:33:44 +0000138#ifdef CONFIG_CPU_PM
Lorenzo Pieralisi95322522013-07-22 12:22:13 +0100139 DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
140 DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
141 DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
James Morseadc9b2d2016-04-27 17:47:06 +0100142 DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs));
143 DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs));
Lorenzo Pieralisi95322522013-07-22 12:22:13 +0100144#endif
Andy Gross680a0872017-02-01 11:28:27 -0600145 DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
146 DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
147 DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
148 DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
James Morse82869ac2016-04-27 17:47:12 +0100149 BLANK();
150 DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address));
151 DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address));
152 DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next));
Suzuki K Poulose116c81f2016-09-09 14:07:16 +0100153 DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val));
Will Deacon51a00482017-11-14 14:14:17 +0000154 BLANK();
155#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
156 DEFINE(TRAMP_VALIAS, TRAMP_VALIAS);
157#endif
James Morsef5df2692018-01-08 15:38:12 +0000158#ifdef CONFIG_ARM_SDE_INTERFACE
159 DEFINE(SDEI_EVENT_INTREGS, offsetof(struct sdei_registered_event, interrupted_regs));
160 DEFINE(SDEI_EVENT_PRIORITY, offsetof(struct sdei_registered_event, priority));
161#endif
Catalin Marinas0be73202012-03-05 11:49:26 +0000162 return 0;
163}