Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/asm-offsets.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2003 Russell King |
| 5 | * 2001-2002 Keith Owens |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/sched.h> |
| 22 | #include <linux/mm.h> |
| 23 | #include <linux/dma-mapping.h> |
Marc Zyngier | c3eb5b1 | 2013-07-04 13:34:32 +0100 | [diff] [blame] | 24 | #include <linux/kvm_host.h> |
James Morse | 82869ac | 2016-04-27 17:47:12 +0100 | [diff] [blame] | 25 | #include <linux/suspend.h> |
Suzuki K Poulose | 116c81f | 2016-09-09 14:07:16 +0100 | [diff] [blame] | 26 | #include <asm/cpufeature.h> |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 27 | #include <asm/thread_info.h> |
| 28 | #include <asm/memory.h> |
Lorenzo Pieralisi | 9532252 | 2013-07-22 12:22:13 +0100 | [diff] [blame] | 29 | #include <asm/smp_plat.h> |
| 30 | #include <asm/suspend.h> |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 31 | #include <asm/vdso_datapage.h> |
| 32 | #include <linux/kbuild.h> |
Jens Wiklander | 1445745 | 2016-01-04 15:44:32 +0100 | [diff] [blame] | 33 | #include <linux/arm-smccc.h> |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 34 | |
| 35 | int main(void) |
| 36 | { |
| 37 | DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); |
| 38 | BLANK(); |
Mark Rutland | c02433d | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 39 | DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags)); |
| 40 | DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count)); |
| 41 | DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit)); |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 42 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 43 | DEFINE(TSK_TI_TTBR0, offsetof(struct task_struct, thread_info.ttbr0)); |
| 44 | #endif |
Mark Rutland | c02433d | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 45 | DEFINE(TSK_STACK, offsetof(struct task_struct, stack)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 46 | BLANK(); |
| 47 | DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context)); |
| 48 | BLANK(); |
| 49 | DEFINE(S_X0, offsetof(struct pt_regs, regs[0])); |
| 50 | DEFINE(S_X1, offsetof(struct pt_regs, regs[1])); |
| 51 | DEFINE(S_X2, offsetof(struct pt_regs, regs[2])); |
| 52 | DEFINE(S_X3, offsetof(struct pt_regs, regs[3])); |
| 53 | DEFINE(S_X4, offsetof(struct pt_regs, regs[4])); |
| 54 | DEFINE(S_X5, offsetof(struct pt_regs, regs[5])); |
| 55 | DEFINE(S_X6, offsetof(struct pt_regs, regs[6])); |
| 56 | DEFINE(S_X7, offsetof(struct pt_regs, regs[7])); |
William Cohen | da6a912 | 2016-07-08 12:35:52 -0400 | [diff] [blame] | 57 | DEFINE(S_X8, offsetof(struct pt_regs, regs[8])); |
| 58 | DEFINE(S_X10, offsetof(struct pt_regs, regs[10])); |
| 59 | DEFINE(S_X12, offsetof(struct pt_regs, regs[12])); |
| 60 | DEFINE(S_X14, offsetof(struct pt_regs, regs[14])); |
| 61 | DEFINE(S_X16, offsetof(struct pt_regs, regs[16])); |
| 62 | DEFINE(S_X18, offsetof(struct pt_regs, regs[18])); |
| 63 | DEFINE(S_X20, offsetof(struct pt_regs, regs[20])); |
| 64 | DEFINE(S_X22, offsetof(struct pt_regs, regs[22])); |
| 65 | DEFINE(S_X24, offsetof(struct pt_regs, regs[24])); |
| 66 | DEFINE(S_X26, offsetof(struct pt_regs, regs[26])); |
| 67 | DEFINE(S_X28, offsetof(struct pt_regs, regs[28])); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 68 | DEFINE(S_LR, offsetof(struct pt_regs, regs[30])); |
| 69 | DEFINE(S_SP, offsetof(struct pt_regs, sp)); |
| 70 | #ifdef CONFIG_COMPAT |
| 71 | DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp)); |
| 72 | #endif |
| 73 | DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate)); |
| 74 | DEFINE(S_PC, offsetof(struct pt_regs, pc)); |
| 75 | DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); |
| 76 | DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 77 | DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit)); |
Ard Biesheuvel | 7326749 | 2017-07-22 18:45:33 +0100 | [diff] [blame^] | 78 | DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 79 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); |
| 80 | BLANK(); |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 81 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 82 | BLANK(); |
| 83 | DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); |
| 84 | DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); |
| 85 | BLANK(); |
| 86 | DEFINE(VM_EXEC, VM_EXEC); |
| 87 | BLANK(); |
| 88 | DEFINE(PAGE_SZ, PAGE_SIZE); |
| 89 | BLANK(); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 90 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); |
| 91 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); |
| 92 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); |
| 93 | BLANK(); |
| 94 | DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); |
| 95 | DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); |
Kevin Brodsky | 49eea43 | 2016-07-12 11:24:00 +0100 | [diff] [blame] | 96 | DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 97 | DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); |
| 98 | DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); |
| 99 | DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE); |
| 100 | DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC); |
| 101 | DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); |
| 102 | BLANK(); |
| 103 | DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last)); |
Kevin Brodsky | 49eea43 | 2016-07-12 11:24:00 +0100 | [diff] [blame] | 104 | DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec)); |
| 105 | DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 106 | DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec)); |
| 107 | DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec)); |
| 108 | DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec)); |
| 109 | DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec)); |
| 110 | DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec)); |
| 111 | DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec)); |
| 112 | DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count)); |
Kevin Brodsky | 49eea43 | 2016-07-12 11:24:00 +0100 | [diff] [blame] | 113 | DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult)); |
| 114 | DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 115 | DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift)); |
| 116 | DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest)); |
| 117 | DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); |
| 118 | DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall)); |
| 119 | BLANK(); |
| 120 | DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec)); |
| 121 | DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec)); |
| 122 | DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec)); |
| 123 | DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec)); |
| 124 | BLANK(); |
| 125 | DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); |
| 126 | DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); |
Marc Zyngier | 55c7401 | 2012-12-10 16:40:18 +0000 | [diff] [blame] | 127 | BLANK(); |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 128 | DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack)); |
Mark Rutland | c02433d | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 129 | DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task)); |
Suzuki K Poulose | bb90527 | 2016-02-23 10:31:42 +0000 | [diff] [blame] | 130 | BLANK(); |
Marc Zyngier | 55c7401 | 2012-12-10 16:40:18 +0000 | [diff] [blame] | 131 | #ifdef CONFIG_KVM_ARM_HOST |
| 132 | DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt)); |
| 133 | DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs)); |
| 134 | DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs)); |
| 135 | DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs)); |
Marc Zyngier | 9d8415d | 2015-10-25 19:57:11 +0000 | [diff] [blame] | 136 | DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2])); |
Marc Zyngier | 55c7401 | 2012-12-10 16:40:18 +0000 | [diff] [blame] | 137 | DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context)); |
Marc Zyngier | 55c7401 | 2012-12-10 16:40:18 +0000 | [diff] [blame] | 138 | #endif |
Lorenzo Pieralisi | af3cfdb | 2015-01-26 18:33:44 +0000 | [diff] [blame] | 139 | #ifdef CONFIG_CPU_PM |
Lorenzo Pieralisi | 9532252 | 2013-07-22 12:22:13 +0100 | [diff] [blame] | 140 | DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx)); |
| 141 | DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); |
| 142 | DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask)); |
| 143 | DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff)); |
James Morse | adc9b2d | 2016-04-27 17:47:06 +0100 | [diff] [blame] | 144 | DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs)); |
| 145 | DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs)); |
Lorenzo Pieralisi | 9532252 | 2013-07-22 12:22:13 +0100 | [diff] [blame] | 146 | #endif |
Andy Gross | 680a087 | 2017-02-01 11:28:27 -0600 | [diff] [blame] | 147 | DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0)); |
| 148 | DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); |
| 149 | DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); |
| 150 | DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); |
| 151 | |
James Morse | 82869ac | 2016-04-27 17:47:12 +0100 | [diff] [blame] | 152 | BLANK(); |
| 153 | DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); |
| 154 | DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); |
| 155 | DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next)); |
Suzuki K Poulose | 116c81f | 2016-09-09 14:07:16 +0100 | [diff] [blame] | 156 | DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val)); |
Catalin Marinas | 0be7320 | 2012-03-05 11:49:26 +0000 | [diff] [blame] | 157 | return 0; |
| 158 | } |