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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 362ed48dee509abe24cf84b7e137c7a29a8f4d2d / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 281a223591ff83d5a9eef96c6775c77c99a356ad [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]68 dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]71 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]72 };
73
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]74 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]75 compatible = "fsl,imx6q-gpmi-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
79 reg-names = "gpmi-nand", "bch";
80 interrupts = <0 13 0x04>, <0 15 0x04>;
81 interrupt-names = "gpmi-dma", "bch";
82 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
83 <&clks 150>, <&clks 149>;
84 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
85 "gpmi_bch_apb", "per1_bch";
86 fsl,gpmi-dma-channel = <0>;
87 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]88 };
89
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]90 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]94 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]95 };
96
97 L2: l2-cache@00a02000 {
98 compatible = "arm,pl310-cache";
99 reg = <0x00a02000 0x1000>;
100 interrupts = <0 92 0x04>;
101 cache-unified;
102 cache-level = <2>;
103 };
104
105 aips-bus@02000000 { /* AIPS1 */
106 compatible = "fsl,aips-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x02000000 0x100000>;
110 ranges;
111
112 spba-bus@02000000 {
113 compatible = "fsl,spba-bus", "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0x02000000 0x40000>;
117 ranges;
118
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]119 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]120 reg = <0x02004000 0x4000>;
121 interrupts = <0 52 0x04>;
122 };
123
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]124 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
128 reg = <0x02008000 0x4000>;
129 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]130 clocks = <&clks 112>, <&clks 112>;
131 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]132 status = "disabled";
133 };
134
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]135 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
139 reg = <0x0200c000 0x4000>;
140 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]141 clocks = <&clks 113>, <&clks 113>;
142 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]143 status = "disabled";
144 };
145
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]146 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02010000 0x4000>;
151 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]152 clocks = <&clks 114>, <&clks 114>;
153 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]154 status = "disabled";
155 };
156
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]157 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02014000 0x4000>;
162 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]163 clocks = <&clks 115>, <&clks 115>;
164 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]165 status = "disabled";
166 };
167
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]168 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]172 clocks = <&clks 160>, <&clks 161>;
173 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]174 status = "disabled";
175 };
176
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]177 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]178 reg = <0x02024000 0x4000>;
179 interrupts = <0 51 0x04>;
180 };
181
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]182 ssi1: ssi@02028000 {
183 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]184 reg = <0x02028000 0x4000>;
185 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]186 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]187 fsl,fifo-depth = <15>;
188 fsl,ssi-dma-events = <38 37>;
189 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]190 };
191
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]192 ssi2: ssi@0202c000 {
193 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]194 reg = <0x0202c000 0x4000>;
195 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]196 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]197 fsl,fifo-depth = <15>;
198 fsl,ssi-dma-events = <42 41>;
199 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]200 };
201
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]202 ssi3: ssi@02030000 {
203 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 reg = <0x02030000 0x4000>;
205 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]206 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]207 fsl,fifo-depth = <15>;
208 fsl,ssi-dma-events = <46 45>;
209 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]210 };
211
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]212 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 reg = <0x02034000 0x4000>;
214 interrupts = <0 50 0x04>;
215 };
216
217 spba@0203c000 {
218 reg = <0x0203c000 0x4000>;
219 };
220 };
221
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]222 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 reg = <0x02040000 0x3c000>;
224 interrupts = <0 3 0x04 0 12 0x04>;
225 };
226
227 aipstz@0207c000 { /* AIPSTZ1 */
228 reg = <0x0207c000 0x4000>;
229 };
230
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]231 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]232 #pwm-cells = <2>;
233 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]234 reg = <0x02080000 0x4000>;
235 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]236 clocks = <&clks 62>, <&clks 145>;
237 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]238 };
239
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]240 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]241 #pwm-cells = <2>;
242 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 reg = <0x02084000 0x4000>;
244 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]245 clocks = <&clks 62>, <&clks 146>;
246 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]247 };
248
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]249 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]250 #pwm-cells = <2>;
251 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]252 reg = <0x02088000 0x4000>;
253 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]254 clocks = <&clks 62>, <&clks 147>;
255 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]256 };
257
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]258 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]259 #pwm-cells = <2>;
260 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]261 reg = <0x0208c000 0x4000>;
262 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]263 clocks = <&clks 62>, <&clks 148>;
264 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]265 };
266
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]267 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]268 reg = <0x02090000 0x4000>;
269 interrupts = <0 110 0x04>;
270 };
271
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]272 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]273 reg = <0x02094000 0x4000>;
274 interrupts = <0 111 0x04>;
275 };
276
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]277 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]278 compatible = "fsl,imx6q-gpt";
279 reg = <0x02098000 0x4000>;
280 interrupts = <0 55 0x04>;
281 };
282
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]283 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]284 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]285 reg = <0x0209c000 0x4000>;
286 interrupts = <0 66 0x04 0 67 0x04>;
287 gpio-controller;
288 #gpio-cells = <2>;
289 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]290 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]291 };
292
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]293 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]294 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]295 reg = <0x020a0000 0x4000>;
296 interrupts = <0 68 0x04 0 69 0x04>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]300 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]301 };
302
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]303 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]304 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]305 reg = <0x020a4000 0x4000>;
306 interrupts = <0 70 0x04 0 71 0x04>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]310 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]311 };
312
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]313 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]314 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]315 reg = <0x020a8000 0x4000>;
316 interrupts = <0 72 0x04 0 73 0x04>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]320 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]321 };
322
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]323 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]324 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]325 reg = <0x020ac000 0x4000>;
326 interrupts = <0 74 0x04 0 75 0x04>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]330 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]331 };
332
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]333 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]334 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]335 reg = <0x020b0000 0x4000>;
336 interrupts = <0 76 0x04 0 77 0x04>;
337 gpio-controller;
338 #gpio-cells = <2>;
339 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]340 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]341 };
342
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]343 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]344 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]345 reg = <0x020b4000 0x4000>;
346 interrupts = <0 78 0x04 0 79 0x04>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]350 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]351 };
352
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]353 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 reg = <0x020b8000 0x4000>;
355 interrupts = <0 82 0x04>;
356 };
357
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]358 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]359 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
360 reg = <0x020bc000 0x4000>;
361 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]362 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]363 };
364
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]365 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]366 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
367 reg = <0x020c0000 0x4000>;
368 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]369 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]370 status = "disabled";
371 };
372
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]373 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 compatible = "fsl,imx6q-ccm";
375 reg = <0x020c4000 0x4000>;
376 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]377 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]378 };
379
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]380 anatop: anatop@020c8000 {
381 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]382 reg = <0x020c8000 0x1000>;
383 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]384
385 regulator-1p1@110 {
386 compatible = "fsl,anatop-regulator";
387 regulator-name = "vdd1p1";
388 regulator-min-microvolt = <800000>;
389 regulator-max-microvolt = <1375000>;
390 regulator-always-on;
391 anatop-reg-offset = <0x110>;
392 anatop-vol-bit-shift = <8>;
393 anatop-vol-bit-width = <5>;
394 anatop-min-bit-val = <4>;
395 anatop-min-voltage = <800000>;
396 anatop-max-voltage = <1375000>;
397 };
398
399 regulator-3p0@120 {
400 compatible = "fsl,anatop-regulator";
401 regulator-name = "vdd3p0";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <3150000>;
404 regulator-always-on;
405 anatop-reg-offset = <0x120>;
406 anatop-vol-bit-shift = <8>;
407 anatop-vol-bit-width = <5>;
408 anatop-min-bit-val = <0>;
409 anatop-min-voltage = <2625000>;
410 anatop-max-voltage = <3400000>;
411 };
412
413 regulator-2p5@130 {
414 compatible = "fsl,anatop-regulator";
415 regulator-name = "vdd2p5";
416 regulator-min-microvolt = <2000000>;
417 regulator-max-microvolt = <2750000>;
418 regulator-always-on;
419 anatop-reg-offset = <0x130>;
420 anatop-vol-bit-shift = <8>;
421 anatop-vol-bit-width = <5>;
422 anatop-min-bit-val = <0>;
423 anatop-min-voltage = <2000000>;
424 anatop-max-voltage = <2750000>;
425 };
426
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]427 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]428 compatible = "fsl,anatop-regulator";
429 regulator-name = "cpu";
430 regulator-min-microvolt = <725000>;
431 regulator-max-microvolt = <1450000>;
432 regulator-always-on;
433 anatop-reg-offset = <0x140>;
434 anatop-vol-bit-shift = <0>;
435 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]436 anatop-delay-reg-offset = <0x170>;
437 anatop-delay-bit-shift = <24>;
438 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]439 anatop-min-bit-val = <1>;
440 anatop-min-voltage = <725000>;
441 anatop-max-voltage = <1450000>;
442 };
443
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]444 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]445 compatible = "fsl,anatop-regulator";
446 regulator-name = "vddpu";
447 regulator-min-microvolt = <725000>;
448 regulator-max-microvolt = <1450000>;
449 regulator-always-on;
450 anatop-reg-offset = <0x140>;
451 anatop-vol-bit-shift = <9>;
452 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]453 anatop-delay-reg-offset = <0x170>;
454 anatop-delay-bit-shift = <26>;
455 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]456 anatop-min-bit-val = <1>;
457 anatop-min-voltage = <725000>;
458 anatop-max-voltage = <1450000>;
459 };
460
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]461 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]462 compatible = "fsl,anatop-regulator";
463 regulator-name = "vddsoc";
464 regulator-min-microvolt = <725000>;
465 regulator-max-microvolt = <1450000>;
466 regulator-always-on;
467 anatop-reg-offset = <0x140>;
468 anatop-vol-bit-shift = <18>;
469 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]470 anatop-delay-reg-offset = <0x170>;
471 anatop-delay-bit-shift = <28>;
472 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]473 anatop-min-bit-val = <1>;
474 anatop-min-voltage = <725000>;
475 anatop-max-voltage = <1450000>;
476 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]477 };
478
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]479 usbphy1: usbphy@020c9000 {
480 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]481 reg = <0x020c9000 0x1000>;
482 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]483 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]484 };
485
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]486 usbphy2: usbphy@020ca000 {
487 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]488 reg = <0x020ca000 0x1000>;
489 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]490 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]491 };
492
493 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]494 compatible = "fsl,sec-v4.0-mon", "simple-bus";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 ranges = <0 0x020cc000 0x4000>;
498
499 snvs-rtc-lp@34 {
500 compatible = "fsl,sec-v4.0-mon-rtc-lp";
501 reg = <0x34 0x58>;
502 interrupts = <0 19 0x04 0 20 0x04>;
503 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]504 };
505
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]506 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]507 reg = <0x020d0000 0x4000>;
508 interrupts = <0 56 0x04>;
509 };
510
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]511 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]512 reg = <0x020d4000 0x4000>;
513 interrupts = <0 57 0x04>;
514 };
515
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]516 src: src@020d8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]517 compatible = "fsl,imx6q-src";
518 reg = <0x020d8000 0x4000>;
519 interrupts = <0 91 0x04 0 96 0x04>;
520 };
521
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]522 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]523 compatible = "fsl,imx6q-gpc";
524 reg = <0x020dc000 0x4000>;
525 interrupts = <0 89 0x04 0 90 0x04>;
526 };
527
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]528 gpr: iomuxc-gpr@020e0000 {
529 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
530 reg = <0x020e0000 0x38>;
531 };
532
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]533 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]534 reg = <0x020e4000 0x4000>;
535 interrupts = <0 124 0x04>;
536 };
537
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]538 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 reg = <0x020e8000 0x4000>;
540 interrupts = <0 125 0x04>;
541 };
542
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]543 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]544 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
545 reg = <0x020ec000 0x4000>;
546 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]547 clocks = <&clks 155>, <&clks 155>;
548 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]549 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]550 };
551 };
552
553 aips-bus@02100000 { /* AIPS2 */
554 compatible = "fsl,aips-bus", "simple-bus";
555 #address-cells = <1>;
556 #size-cells = <1>;
557 reg = <0x02100000 0x100000>;
558 ranges;
559
560 caam@02100000 {
561 reg = <0x02100000 0x40000>;
562 interrupts = <0 105 0x04 0 106 0x04>;
563 };
564
565 aipstz@0217c000 { /* AIPSTZ2 */
566 reg = <0x0217c000 0x4000>;
567 };
568
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]569 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]570 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
571 reg = <0x02184000 0x200>;
572 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]573 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]574 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]575 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]576 status = "disabled";
577 };
578
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]579 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]580 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
581 reg = <0x02184200 0x200>;
582 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]583 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]584 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]585 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]586 status = "disabled";
587 };
588
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]589 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]590 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
591 reg = <0x02184400 0x200>;
592 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]593 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]594 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]595 status = "disabled";
596 };
597
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]598 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]599 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
600 reg = <0x02184600 0x200>;
601 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]602 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]603 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]604 status = "disabled";
605 };
606
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]607 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]608 #index-cells = <1>;
609 compatible = "fsl,imx6q-usbmisc";
610 reg = <0x02184800 0x200>;
611 clocks = <&clks 162>;
612 };
613
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]614 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]615 compatible = "fsl,imx6q-fec";
616 reg = <0x02188000 0x4000>;
617 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]618 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]619 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]620 status = "disabled";
621 };
622
623 mlb@0218c000 {
624 reg = <0x0218c000 0x4000>;
625 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
626 };
627
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]628 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]629 compatible = "fsl,imx6q-usdhc";
630 reg = <0x02190000 0x4000>;
631 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]632 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
633 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]634 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]635 status = "disabled";
636 };
637
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]638 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]639 compatible = "fsl,imx6q-usdhc";
640 reg = <0x02194000 0x4000>;
641 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]642 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
643 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]644 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]645 status = "disabled";
646 };
647
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]648 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]649 compatible = "fsl,imx6q-usdhc";
650 reg = <0x02198000 0x4000>;
651 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]652 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
653 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]654 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]655 status = "disabled";
656 };
657
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]658 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]659 compatible = "fsl,imx6q-usdhc";
660 reg = <0x0219c000 0x4000>;
661 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]662 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
663 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]664 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]665 status = "disabled";
666 };
667
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]668 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]669 #address-cells = <1>;
670 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]671 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]672 reg = <0x021a0000 0x4000>;
673 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]674 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]675 status = "disabled";
676 };
677
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]678 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]679 #address-cells = <1>;
680 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]681 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]682 reg = <0x021a4000 0x4000>;
683 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]684 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]685 status = "disabled";
686 };
687
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]688 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]689 #address-cells = <1>;
690 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]691 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]692 reg = <0x021a8000 0x4000>;
693 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]694 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]695 status = "disabled";
696 };
697
698 romcp@021ac000 {
699 reg = <0x021ac000 0x4000>;
700 };
701
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]702 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]703 compatible = "fsl,imx6q-mmdc";
704 reg = <0x021b0000 0x4000>;
705 };
706
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]707 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]708 reg = <0x021b4000 0x4000>;
709 };
710
711 weim@021b8000 {
712 reg = <0x021b8000 0x4000>;
713 interrupts = <0 14 0x04>;
714 };
715
716 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]717 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]718 reg = <0x021bc000 0x4000>;
719 };
720
721 ocotp@021c0000 {
722 reg = <0x021c0000 0x4000>;
723 interrupts = <0 21 0x04>;
724 };
725
726 tzasc@021d0000 { /* TZASC1 */
727 reg = <0x021d0000 0x4000>;
728 interrupts = <0 108 0x04>;
729 };
730
731 tzasc@021d4000 { /* TZASC2 */
732 reg = <0x021d4000 0x4000>;
733 interrupts = <0 109 0x04>;
734 };
735
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]736 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]737 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]738 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]739 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]740 };
741
742 mipi@021dc000 { /* MIPI-CSI */
743 reg = <0x021dc000 0x4000>;
744 };
745
746 mipi@021e0000 { /* MIPI-DSI */
747 reg = <0x021e0000 0x4000>;
748 };
749
750 vdoa@021e4000 {
751 reg = <0x021e4000 0x4000>;
752 interrupts = <0 18 0x04>;
753 };
754
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]755 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]756 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
757 reg = <0x021e8000 0x4000>;
758 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]759 clocks = <&clks 160>, <&clks 161>;
760 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]761 status = "disabled";
762 };
763
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]764 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]765 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
766 reg = <0x021ec000 0x4000>;
767 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]768 clocks = <&clks 160>, <&clks 161>;
769 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]770 status = "disabled";
771 };
772
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]773 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]774 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
775 reg = <0x021f0000 0x4000>;
776 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]777 clocks = <&clks 160>, <&clks 161>;
778 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]779 status = "disabled";
780 };
781
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]782 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]783 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
784 reg = <0x021f4000 0x4000>;
785 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]786 clocks = <&clks 160>, <&clks 161>;
787 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]788 status = "disabled";
789 };
790 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]791
792 ipu1: ipu@02400000 {
793 #crtc-cells = <1>;
794 compatible = "fsl,imx6q-ipu";
795 reg = <0x02400000 0x400000>;
796 interrupts = <0 6 0x4 0 5 0x4>;
797 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
798 clock-names = "bus", "di0", "di1";
799 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]800 };
801};