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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7b7d6727344a2a7727255d61fa1bd3ff447c4f6c / . / arch / arm / boot / dts / imx6q.dtsi
blob: 6dfeaedef3077dd8732f659c764f67b7f0cb4a03 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
Shawn Guod90df972012-07-19 23:16:30 +0800[diff] [blame]39 operating-points = <
40 /* kHz uV */
41 792000 1100000
42 396000 950000
43 198000 850000
44 >;
45 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]47 };
48
49 cpu@1 {
50 compatible = "arm,cortex-a9";
51 reg = <1>;
52 next-level-cache = <&L2>;
53 };
54
55 cpu@2 {
56 compatible = "arm,cortex-a9";
57 reg = <2>;
58 next-level-cache = <&L2>;
59 };
60
61 cpu@3 {
62 compatible = "arm,cortex-a9";
63 reg = <3>;
64 next-level-cache = <&L2>;
65 };
66 };
67
68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller;
74 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fsl,imx-ckil", "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 ckih1 {
88 compatible = "fsl,imx-ckih1", "fixed-clock";
89 clock-frequency = <0>;
90 };
91
92 osc {
93 compatible = "fsl,imx-osc", "fixed-clock";
94 clock-frequency = <24000000>;
95 };
96 };
97
98 soc {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "simple-bus";
102 interrupt-parent = <&intc>;
103 ranges;
104
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]105 dma-apbh@00110000 {
106 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
107 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]108 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]109 };
110
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]111 nfc: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]112 compatible = "fsl,imx6q-gpmi-nand";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
116 reg-names = "gpmi-nand", "bch";
117 interrupts = <0 13 0x04>, <0 15 0x04>;
118 interrupt-names = "gpmi-dma", "bch";
119 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
120 <&clks 150>, <&clks 149>;
121 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
122 "gpmi_bch_apb", "per1_bch";
123 fsl,gpmi-dma-channel = <0>;
124 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]125 };
126
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]127 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]128 compatible = "arm,cortex-a9-twd-timer";
129 reg = <0x00a00600 0x20>;
130 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]131 };
132
133 L2: l2-cache@00a02000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x00a02000 0x1000>;
136 interrupts = <0 92 0x04>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
141 aips-bus@02000000 { /* AIPS1 */
142 compatible = "fsl,aips-bus", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 reg = <0x02000000 0x100000>;
146 ranges;
147
148 spba-bus@02000000 {
149 compatible = "fsl,spba-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x02000000 0x40000>;
153 ranges;
154
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]155 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>;
158 };
159
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]160 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x02008000 0x4000>;
165 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]166 clocks = <&clks 112>, <&clks 112>;
167 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]168 status = "disabled";
169 };
170
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]171 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x0200c000 0x4000>;
176 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]177 clocks = <&clks 113>, <&clks 113>;
178 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]179 status = "disabled";
180 };
181
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]182 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]188 clocks = <&clks 114>, <&clks 114>;
189 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]190 status = "disabled";
191 };
192
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]193 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]199 clocks = <&clks 115>, <&clks 115>;
200 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]201 status = "disabled";
202 };
203
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]204 ecspi5: ecspi@02018000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02018000 0x4000>;
209 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]210 clocks = <&clks 116>, <&clks 116>;
211 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]212 status = "disabled";
213 };
214
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]215 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]221 status = "disabled";
222 };
223
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]224 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]225 reg = <0x02024000 0x4000>;
226 interrupts = <0 51 0x04>;
227 };
228
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]229 ssi1: ssi@02028000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]231 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]233 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <38 37>;
236 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]237 };
238
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]239 ssi2: ssi@0202c000 {
240 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]241 reg = <0x0202c000 0x4000>;
242 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]243 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]244 fsl,fifo-depth = <15>;
245 fsl,ssi-dma-events = <42 41>;
246 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]247 };
248
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]249 ssi3: ssi@02030000 {
250 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]251 reg = <0x02030000 0x4000>;
252 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]253 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]254 fsl,fifo-depth = <15>;
255 fsl,ssi-dma-events = <46 45>;
256 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]257 };
258
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]259 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]260 reg = <0x02034000 0x4000>;
261 interrupts = <0 50 0x04>;
262 };
263
264 spba@0203c000 {
265 reg = <0x0203c000 0x4000>;
266 };
267 };
268
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]269 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]270 reg = <0x02040000 0x3c000>;
271 interrupts = <0 3 0x04 0 12 0x04>;
272 };
273
274 aipstz@0207c000 { /* AIPSTZ1 */
275 reg = <0x0207c000 0x4000>;
276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]278 pwm1: pwm@02080000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]279 reg = <0x02080000 0x4000>;
280 interrupts = <0 83 0x04>;
281 };
282
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]283 pwm2: pwm@02084000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]284 reg = <0x02084000 0x4000>;
285 interrupts = <0 84 0x04>;
286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]288 pwm3: pwm@02088000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]289 reg = <0x02088000 0x4000>;
290 interrupts = <0 85 0x04>;
291 };
292
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]293 pwm4: pwm@0208c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]294 reg = <0x0208c000 0x4000>;
295 interrupts = <0 86 0x04>;
296 };
297
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]298 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]299 reg = <0x02090000 0x4000>;
300 interrupts = <0 110 0x04>;
301 };
302
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]303 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]304 reg = <0x02094000 0x4000>;
305 interrupts = <0 111 0x04>;
306 };
307
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]308 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]309 compatible = "fsl,imx6q-gpt";
310 reg = <0x02098000 0x4000>;
311 interrupts = <0 55 0x04>;
312 };
313
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]314 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]315 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]316 reg = <0x0209c000 0x4000>;
317 interrupts = <0 66 0x04 0 67 0x04>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]321 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]322 };
323
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]324 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]325 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]326 reg = <0x020a0000 0x4000>;
327 interrupts = <0 68 0x04 0 69 0x04>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]331 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]332 };
333
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]334 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]335 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]336 reg = <0x020a4000 0x4000>;
337 interrupts = <0 70 0x04 0 71 0x04>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]341 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]342 };
343
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]344 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]345 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]346 reg = <0x020a8000 0x4000>;
347 interrupts = <0 72 0x04 0 73 0x04>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]351 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]352 };
353
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]354 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]355 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]356 reg = <0x020ac000 0x4000>;
357 interrupts = <0 74 0x04 0 75 0x04>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]361 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]362 };
363
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]364 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]365 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]366 reg = <0x020b0000 0x4000>;
367 interrupts = <0 76 0x04 0 77 0x04>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]371 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]372 };
373
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]374 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]375 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]376 reg = <0x020b4000 0x4000>;
377 interrupts = <0 78 0x04 0 79 0x04>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]381 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]382 };
383
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]384 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]385 reg = <0x020b8000 0x4000>;
386 interrupts = <0 82 0x04>;
387 };
388
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]389 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]390 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
391 reg = <0x020bc000 0x4000>;
392 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]393 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]394 };
395
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]396 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]397 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
398 reg = <0x020c0000 0x4000>;
399 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]400 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]401 status = "disabled";
402 };
403
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]404 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]405 compatible = "fsl,imx6q-ccm";
406 reg = <0x020c4000 0x4000>;
407 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]408 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]409 };
410
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]411 anatop: anatop@020c8000 {
412 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]413 reg = <0x020c8000 0x1000>;
414 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]415
416 regulator-1p1@110 {
417 compatible = "fsl,anatop-regulator";
418 regulator-name = "vdd1p1";
419 regulator-min-microvolt = <800000>;
420 regulator-max-microvolt = <1375000>;
421 regulator-always-on;
422 anatop-reg-offset = <0x110>;
423 anatop-vol-bit-shift = <8>;
424 anatop-vol-bit-width = <5>;
425 anatop-min-bit-val = <4>;
426 anatop-min-voltage = <800000>;
427 anatop-max-voltage = <1375000>;
428 };
429
430 regulator-3p0@120 {
431 compatible = "fsl,anatop-regulator";
432 regulator-name = "vdd3p0";
433 regulator-min-microvolt = <2800000>;
434 regulator-max-microvolt = <3150000>;
435 regulator-always-on;
436 anatop-reg-offset = <0x120>;
437 anatop-vol-bit-shift = <8>;
438 anatop-vol-bit-width = <5>;
439 anatop-min-bit-val = <0>;
440 anatop-min-voltage = <2625000>;
441 anatop-max-voltage = <3400000>;
442 };
443
444 regulator-2p5@130 {
445 compatible = "fsl,anatop-regulator";
446 regulator-name = "vdd2p5";
447 regulator-min-microvolt = <2000000>;
448 regulator-max-microvolt = <2750000>;
449 regulator-always-on;
450 anatop-reg-offset = <0x130>;
451 anatop-vol-bit-shift = <8>;
452 anatop-vol-bit-width = <5>;
453 anatop-min-bit-val = <0>;
454 anatop-min-voltage = <2000000>;
455 anatop-max-voltage = <2750000>;
456 };
457
Shawn Guod90df972012-07-19 23:16:30 +0800[diff] [blame]458 reg_cpu: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]459 compatible = "fsl,anatop-regulator";
460 regulator-name = "cpu";
461 regulator-min-microvolt = <725000>;
462 regulator-max-microvolt = <1450000>;
463 regulator-always-on;
464 anatop-reg-offset = <0x140>;
465 anatop-vol-bit-shift = <0>;
466 anatop-vol-bit-width = <5>;
467 anatop-min-bit-val = <1>;
468 anatop-min-voltage = <725000>;
469 anatop-max-voltage = <1450000>;
470 };
471
472 regulator-vddpu@140 {
473 compatible = "fsl,anatop-regulator";
474 regulator-name = "vddpu";
475 regulator-min-microvolt = <725000>;
476 regulator-max-microvolt = <1450000>;
477 regulator-always-on;
478 anatop-reg-offset = <0x140>;
479 anatop-vol-bit-shift = <9>;
480 anatop-vol-bit-width = <5>;
481 anatop-min-bit-val = <1>;
482 anatop-min-voltage = <725000>;
483 anatop-max-voltage = <1450000>;
484 };
485
486 regulator-vddsoc@140 {
487 compatible = "fsl,anatop-regulator";
488 regulator-name = "vddsoc";
489 regulator-min-microvolt = <725000>;
490 regulator-max-microvolt = <1450000>;
491 regulator-always-on;
492 anatop-reg-offset = <0x140>;
493 anatop-vol-bit-shift = <18>;
494 anatop-vol-bit-width = <5>;
495 anatop-min-bit-val = <1>;
496 anatop-min-voltage = <725000>;
497 anatop-max-voltage = <1450000>;
498 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]499 };
500
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]501 usbphy1: usbphy@020c9000 {
502 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]503 reg = <0x020c9000 0x1000>;
504 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]505 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]506 };
507
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]508 usbphy2: usbphy@020ca000 {
509 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]510 reg = <0x020ca000 0x1000>;
511 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]512 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]513 };
514
515 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]516 compatible = "fsl,sec-v4.0-mon", "simple-bus";
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges = <0 0x020cc000 0x4000>;
520
521 snvs-rtc-lp@34 {
522 compatible = "fsl,sec-v4.0-mon-rtc-lp";
523 reg = <0x34 0x58>;
524 interrupts = <0 19 0x04 0 20 0x04>;
525 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]526 };
527
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]528 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]529 reg = <0x020d0000 0x4000>;
530 interrupts = <0 56 0x04>;
531 };
532
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]533 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]534 reg = <0x020d4000 0x4000>;
535 interrupts = <0 57 0x04>;
536 };
537
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]538 src: src@020d8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 compatible = "fsl,imx6q-src";
540 reg = <0x020d8000 0x4000>;
541 interrupts = <0 91 0x04 0 96 0x04>;
542 };
543
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]544 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]545 compatible = "fsl,imx6q-gpc";
546 reg = <0x020dc000 0x4000>;
547 interrupts = <0 89 0x04 0 90 0x04>;
548 };
549
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]550 gpr: iomuxc-gpr@020e0000 {
551 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
552 reg = <0x020e0000 0x38>;
553 };
554
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]555 iomuxc: iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]556 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]557 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]558
559 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]560 audmux {
561 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]562 fsl,pins = <
563 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
564 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
565 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
566 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
567 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]568 };
569 };
570
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]571 ecspi1 {
572 pinctrl_ecspi1_1: ecspi1grp-1 {
573 fsl,pins = <
574 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
575 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
576 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
577 >;
578 };
579 };
580
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]581 enet {
582 pinctrl_enet_1: enetgrp-1 {
583 fsl,pins = <
584 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
585 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
586 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
587 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
588 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
589 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
590 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
591 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
592 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
593 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
594 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
595 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
596 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
597 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
598 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
599 >;
600 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]601
602 pinctrl_enet_2: enetgrp-2 {
603 fsl,pins = <
604 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
605 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
606 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
607 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
608 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
609 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
610 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
611 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
612 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
613 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
614 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
615 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
616 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
617 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
618 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
619 >;
620 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]621 };
622
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]623 gpmi-nand {
624 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]625 fsl,pins = <
626 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
627 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
628 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
629 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
630 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
631 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
632 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
633 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
634 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
635 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
636 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
637 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
638 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
639 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
640 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
641 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
642 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
643 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
644 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
645 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]646 };
647 };
648
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]649 i2c1 {
650 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]651 fsl,pins = <
652 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
653 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
654 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]655 };
656 };
657
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]658 uart1 {
659 pinctrl_uart1_1: uart1grp-1 {
660 fsl,pins = <
661 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
662 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
663 >;
664 };
665 };
666
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]667 uart2 {
668 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]669 fsl,pins = <
670 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
671 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
672 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]673 };
674 };
675
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]676 uart4 {
677 pinctrl_uart4_1: uart4grp-1 {
678 fsl,pins = <
679 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
680 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
681 >;
682 };
683 };
684
Richard Zhao97a53092012-09-19 11:25:16 +0800[diff] [blame]685 usbotg {
686 pinctrl_usbotg_1: usbotggrp-1 {
687 fsl,pins = <
688 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
689 >;
690 };
691 };
692
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]693 usdhc2 {
694 pinctrl_usdhc2_1: usdhc2grp-1 {
695 fsl,pins = <
696 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
697 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
698 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
699 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
700 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
701 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
702 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
703 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
704 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
705 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
706 >;
707 };
708 };
709
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]710 usdhc3 {
711 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]712 fsl,pins = <
713 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
714 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
715 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
716 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
717 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
718 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
719 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
720 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
721 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
722 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
723 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]724 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]725
726 pinctrl_usdhc3_2: usdhc3grp-2 {
727 fsl,pins = <
728 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
729 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
730 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
731 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
732 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
733 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
734 >;
735 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]736 };
737
738 usdhc4 {
739 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]740 fsl,pins = <
741 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
742 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
743 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
744 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
745 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
746 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
747 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
748 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
749 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
750 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
751 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]752 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]753
754 pinctrl_usdhc4_2: usdhc4grp-2 {
755 fsl,pins = <
756 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
757 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
758 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
759 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
760 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
761 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
762 >;
763 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]764 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]765 };
766
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]767 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]768 reg = <0x020e4000 0x4000>;
769 interrupts = <0 124 0x04>;
770 };
771
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]772 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]773 reg = <0x020e8000 0x4000>;
774 interrupts = <0 125 0x04>;
775 };
776
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]777 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
779 reg = <0x020ec000 0x4000>;
780 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]781 clocks = <&clks 155>, <&clks 155>;
782 clock-names = "ipg", "ahb";
783 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]784 };
785 };
786
787 aips-bus@02100000 { /* AIPS2 */
788 compatible = "fsl,aips-bus", "simple-bus";
789 #address-cells = <1>;
790 #size-cells = <1>;
791 reg = <0x02100000 0x100000>;
792 ranges;
793
794 caam@02100000 {
795 reg = <0x02100000 0x40000>;
796 interrupts = <0 105 0x04 0 106 0x04>;
797 };
798
799 aipstz@0217c000 { /* AIPSTZ2 */
800 reg = <0x0217c000 0x4000>;
801 };
802
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]803 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]804 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
805 reg = <0x02184000 0x200>;
806 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]807 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]808 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]809 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]810 status = "disabled";
811 };
812
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]813 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
815 reg = <0x02184200 0x200>;
816 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]817 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]818 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]819 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]820 status = "disabled";
821 };
822
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]823 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]824 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
825 reg = <0x02184400 0x200>;
826 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]827 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]828 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]829 status = "disabled";
830 };
831
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]832 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]833 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
834 reg = <0x02184600 0x200>;
835 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]836 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]837 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]838 status = "disabled";
839 };
840
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]841 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]842 #index-cells = <1>;
843 compatible = "fsl,imx6q-usbmisc";
844 reg = <0x02184800 0x200>;
845 clocks = <&clks 162>;
846 };
847
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]848 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]849 compatible = "fsl,imx6q-fec";
850 reg = <0x02188000 0x4000>;
851 interrupts = <0 118 0x04 0 119 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]852 clocks = <&clks 117>, <&clks 117>;
853 clock-names = "ipg", "ahb";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]854 status = "disabled";
855 };
856
857 mlb@0218c000 {
858 reg = <0x0218c000 0x4000>;
859 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
860 };
861
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]862 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]863 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02190000 0x4000>;
865 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]866 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
867 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]868 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]869 status = "disabled";
870 };
871
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]872 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]873 compatible = "fsl,imx6q-usdhc";
874 reg = <0x02194000 0x4000>;
875 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]876 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
877 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]878 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]879 status = "disabled";
880 };
881
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]882 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]883 compatible = "fsl,imx6q-usdhc";
884 reg = <0x02198000 0x4000>;
885 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]886 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
887 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]888 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]889 status = "disabled";
890 };
891
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]892 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]893 compatible = "fsl,imx6q-usdhc";
894 reg = <0x0219c000 0x4000>;
895 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]896 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
897 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]898 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]899 status = "disabled";
900 };
901
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]902 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]903 #address-cells = <1>;
904 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]905 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]906 reg = <0x021a0000 0x4000>;
907 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]908 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]909 status = "disabled";
910 };
911
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]912 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]913 #address-cells = <1>;
914 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]915 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]916 reg = <0x021a4000 0x4000>;
917 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]918 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]919 status = "disabled";
920 };
921
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]922 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]923 #address-cells = <1>;
924 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]925 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]926 reg = <0x021a8000 0x4000>;
927 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]928 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]929 status = "disabled";
930 };
931
932 romcp@021ac000 {
933 reg = <0x021ac000 0x4000>;
934 };
935
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]936 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]937 compatible = "fsl,imx6q-mmdc";
938 reg = <0x021b0000 0x4000>;
939 };
940
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]941 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]942 reg = <0x021b4000 0x4000>;
943 };
944
945 weim@021b8000 {
946 reg = <0x021b8000 0x4000>;
947 interrupts = <0 14 0x04>;
948 };
949
950 ocotp@021bc000 {
951 reg = <0x021bc000 0x4000>;
952 };
953
954 ocotp@021c0000 {
955 reg = <0x021c0000 0x4000>;
956 interrupts = <0 21 0x04>;
957 };
958
959 tzasc@021d0000 { /* TZASC1 */
960 reg = <0x021d0000 0x4000>;
961 interrupts = <0 108 0x04>;
962 };
963
964 tzasc@021d4000 { /* TZASC2 */
965 reg = <0x021d4000 0x4000>;
966 interrupts = <0 109 0x04>;
967 };
968
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame^]969 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]970 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]971 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]972 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]973 };
974
975 mipi@021dc000 { /* MIPI-CSI */
976 reg = <0x021dc000 0x4000>;
977 };
978
979 mipi@021e0000 { /* MIPI-DSI */
980 reg = <0x021e0000 0x4000>;
981 };
982
983 vdoa@021e4000 {
984 reg = <0x021e4000 0x4000>;
985 interrupts = <0 18 0x04>;
986 };
987
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]988 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]989 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
990 reg = <0x021e8000 0x4000>;
991 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]992 clocks = <&clks 160>, <&clks 161>;
993 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]994 status = "disabled";
995 };
996
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]997 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]998 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
999 reg = <0x021ec000 0x4000>;
1000 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1001 clocks = <&clks 160>, <&clks 161>;
1002 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1003 status = "disabled";
1004 };
1005
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1006 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1007 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1008 reg = <0x021f0000 0x4000>;
1009 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1010 clocks = <&clks 160>, <&clks 161>;
1011 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1012 status = "disabled";
1013 };
1014
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1015 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1016 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1017 reg = <0x021f4000 0x4000>;
1018 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1019 clocks = <&clks 160>, <&clks 161>;
1020 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1021 status = "disabled";
1022 };
1023 };
1024 };
1025};