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Thomas Gleixnerb886d83c2019-06-01 10:08:55 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Ashwin Chaugule337aadf2015-10-02 10:01:19 -04002/*
3 * CPPC (Collaborative Processor Performance Control) methods used
4 * by CPUfreq drivers.
5 *
6 * (C) Copyright 2014, 2015 Linaro Ltd.
7 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -04008 */
9
10#ifndef _CPPC_ACPI_H
11#define _CPPC_ACPI_H
12
13#include <linux/acpi.h>
Rafael J. Wysocki8a02d992021-03-16 16:54:03 +010014#include <linux/cpufreq.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040015#include <linux/types.h>
16
Hoan Tran866ae692016-06-16 14:09:38 -070017#include <acpi/pcc.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040018#include <acpi/processor.h>
19
Prashanth Prakash4773e772018-04-04 12:14:50 -060020/* Support CPPCv2 and CPPCv3 */
21#define CPPC_V2_REV 2
22#define CPPC_V3_REV 3
23#define CPPC_V2_NUM_ENT 21
24#define CPPC_V3_NUM_ENT 23
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040025
Prakash, Prashanth139aee72016-08-16 14:39:44 -060026#define PCC_CMD_COMPLETE_MASK (1 << 0)
27#define PCC_ERROR_MASK (1 << 2)
28
Prashanth Prakash4773e772018-04-04 12:14:50 -060029#define MAX_CPC_REG_ENT 21
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040030
31/* CPPC specific PCC commands. */
32#define CMD_READ 0
33#define CMD_WRITE 1
34
35/* Each register has the folowing format. */
36struct cpc_reg {
37 u8 descriptor;
38 u16 length;
39 u8 space_id;
40 u8 bit_width;
41 u8 bit_offset;
42 u8 access_width;
Ionela Voinescud8f85cc2021-01-07 11:17:15 +000043 u64 address;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040044} __packed;
45
46/*
47 * Each entry in the CPC table is either
48 * of type ACPI_TYPE_BUFFER or
49 * ACPI_TYPE_INTEGER.
50 */
51struct cpc_register_resource {
52 acpi_object_type type;
Ashwin Chaugule5bbb86a2016-08-16 14:39:38 -060053 u64 __iomem *sys_mem_vaddr;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040054 union {
55 struct cpc_reg reg;
56 u64 int_value;
57 } cpc_entry;
58};
59
60/* Container to hold the CPC details for each CPU */
61struct cpc_desc {
62 int num_entries;
63 int version;
64 int cpu_id;
Prakash, Prashanth80b82862016-08-16 14:39:40 -060065 int write_cmd_status;
66 int write_cmd_id;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040067 struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
68 struct acpi_psd_package domain_info;
Ashwin Chaugule158c9982016-08-16 14:39:42 -060069 struct kobject kobj;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040070};
71
72/* These are indexes into the per-cpu cpc_regs[]. Order is important. */
73enum cppc_regs {
74 HIGHEST_PERF,
75 NOMINAL_PERF,
76 LOW_NON_LINEAR_PERF,
77 LOWEST_PERF,
78 GUARANTEED_PERF,
79 DESIRED_PERF,
80 MIN_PERF,
81 MAX_PERF,
82 PERF_REDUC_TOLERANCE,
83 TIME_WINDOW,
84 CTR_WRAP_TIME,
85 REFERENCE_CTR,
86 DELIVERED_CTR,
87 PERF_LIMITED,
88 ENABLE,
89 AUTO_SEL_ENABLE,
90 AUTO_ACT_WINDOW,
91 ENERGY_PERF,
92 REFERENCE_PERF,
Prashanth Prakash4773e772018-04-04 12:14:50 -060093 LOWEST_FREQ,
94 NOMINAL_FREQ,
Ashwin Chaugule337aadf2015-10-02 10:01:19 -040095};
96
97/*
98 * Categorization of registers as described
99 * in the ACPI v.5.1 spec.
100 * XXX: Only filling up ones which are used by governors
101 * today.
102 */
103struct cppc_perf_caps {
Srinivas Pandruvada29523f02018-10-15 10:37:19 -0700104 u32 guaranteed_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400105 u32 highest_perf;
106 u32 nominal_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400107 u32 lowest_perf;
Prakash, Prashanth368520a2017-03-29 13:49:59 -0600108 u32 lowest_nonlinear_perf;
Prashanth Prakash4773e772018-04-04 12:14:50 -0600109 u32 lowest_freq;
110 u32 nominal_freq;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400111};
112
113struct cppc_perf_ctrls {
114 u32 max_perf;
115 u32 min_perf;
116 u32 desired_perf;
117};
118
119struct cppc_perf_fb_ctrs {
120 u64 reference;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400121 u64 delivered;
Ashwin Chaugule158c9982016-08-16 14:39:42 -0600122 u64 reference_perf;
Prakash, Prashanth2c74d842017-03-29 13:50:00 -0600123 u64 wraparound_time;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400124};
125
126/* Per CPU container for runtime CPPC management. */
Srinivas Pandruvada41dd6402016-09-01 13:37:11 -0700127struct cppc_cpudata {
Ionela Voinescua28b2bf2020-12-14 12:38:23 +0000128 struct list_head node;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400129 struct cppc_perf_caps perf_caps;
130 struct cppc_perf_ctrls perf_ctrls;
131 struct cppc_perf_fb_ctrs perf_fb_ctrs;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400132 unsigned int shared_type;
133 cpumask_var_t shared_cpu_map;
134};
135
Rafael J. Wysocki8a02d992021-03-16 16:54:03 +0100136#ifdef CONFIG_ACPI_CPPC_LIB
Xiongfeng Wang1757d052019-02-17 11:54:14 +0800137extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400138extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
139extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
140extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
Ionela Voinescua28b2bf2020-12-14 12:38:23 +0000141extern bool acpi_cpc_valid(void);
142extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data);
Prakash, Prashanthbe8b88d2016-08-16 14:39:41 -0600143extern unsigned int cppc_get_transition_latency(int cpu);
Borislav Petkovad3bc252018-12-05 00:34:56 +0100144extern bool cpc_ffh_supported(void);
145extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
146extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
Rafael J. Wysocki8a02d992021-03-16 16:54:03 +0100147#else /* !CONFIG_ACPI_CPPC_LIB */
148static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
149{
150 return -ENOTSUPP;
151}
152static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
153{
154 return -ENOTSUPP;
155}
156static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
157{
158 return -ENOTSUPP;
159}
160static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps)
161{
162 return -ENOTSUPP;
163}
164static inline bool acpi_cpc_valid(void)
165{
166 return false;
167}
168static inline unsigned int cppc_get_transition_latency(int cpu)
169{
170 return CPUFREQ_ETERNAL;
171}
172static inline bool cpc_ffh_supported(void)
173{
174 return false;
175}
176static inline int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
177{
178 return -ENOTSUPP;
179}
180static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
181{
182 return -ENOTSUPP;
183}
184#endif /* !CONFIG_ACPI_CPPC_LIB */
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400185
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400186#endif /* _CPPC_ACPI_H*/