Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 29523f095397637edca60c627bc3e5c25a02c40f / . / include / acpi / cppc_acpi.h
blob: cf59e6210d271c55500e7ceb597533ad6a5c90ad [file] [log] [blame]
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]1/*
2 * CPPC (Collaborative Processor Performance Control) methods used
3 * by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14#ifndef _CPPC_ACPI_H
15#define _CPPC_ACPI_H
16
17#include <linux/acpi.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]18#include <linux/types.h>
19
Hoan Tran866ae692016-06-16 14:09:38 -0700[diff] [blame]20#include <acpi/pcc.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]21#include <acpi/processor.h>
22
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]23/* Support CPPCv2 and CPPCv3 */
24#define CPPC_V2_REV 2
25#define CPPC_V3_REV 3
26#define CPPC_V2_NUM_ENT 21
27#define CPPC_V3_NUM_ENT 23
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]28
Prakash, Prashanth139aee72016-08-16 14:39:44 -0600[diff] [blame]29#define PCC_CMD_COMPLETE_MASK (1 << 0)
30#define PCC_ERROR_MASK (1 << 2)
31
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]32#define MAX_CPC_REG_ENT 21
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]33
34/* CPPC specific PCC commands. */
35#define CMD_READ 0
36#define CMD_WRITE 1
37
38/* Each register has the folowing format. */
39struct cpc_reg {
40 u8 descriptor;
41 u16 length;
42 u8 space_id;
43 u8 bit_width;
44 u8 bit_offset;
45 u8 access_width;
46 u64 __iomem address;
47} __packed;
48
49/*
50 * Each entry in the CPC table is either
51 * of type ACPI_TYPE_BUFFER or
52 * ACPI_TYPE_INTEGER.
53 */
54struct cpc_register_resource {
55 acpi_object_type type;
Ashwin Chaugule5bbb86a2016-08-16 14:39:38 -0600[diff] [blame]56 u64 __iomem *sys_mem_vaddr;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]57 union {
58 struct cpc_reg reg;
59 u64 int_value;
60 } cpc_entry;
61};
62
63/* Container to hold the CPC details for each CPU */
64struct cpc_desc {
65 int num_entries;
66 int version;
67 int cpu_id;
Prakash, Prashanth80b82862016-08-16 14:39:40 -0600[diff] [blame]68 int write_cmd_status;
69 int write_cmd_id;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]70 struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
71 struct acpi_psd_package domain_info;
Ashwin Chaugule158c9982016-08-16 14:39:42 -0600[diff] [blame]72 struct kobject kobj;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]73};
74
75/* These are indexes into the per-cpu cpc_regs[]. Order is important. */
76enum cppc_regs {
77 HIGHEST_PERF,
78 NOMINAL_PERF,
79 LOW_NON_LINEAR_PERF,
80 LOWEST_PERF,
81 GUARANTEED_PERF,
82 DESIRED_PERF,
83 MIN_PERF,
84 MAX_PERF,
85 PERF_REDUC_TOLERANCE,
86 TIME_WINDOW,
87 CTR_WRAP_TIME,
88 REFERENCE_CTR,
89 DELIVERED_CTR,
90 PERF_LIMITED,
91 ENABLE,
92 AUTO_SEL_ENABLE,
93 AUTO_ACT_WINDOW,
94 ENERGY_PERF,
95 REFERENCE_PERF,
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]96 LOWEST_FREQ,
97 NOMINAL_FREQ,
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]98};
99
100/*
101 * Categorization of registers as described
102 * in the ACPI v.5.1 spec.
103 * XXX: Only filling up ones which are used by governors
104 * today.
105 */
106struct cppc_perf_caps {
Srinivas Pandruvada29523f02018-10-15 10:37:19 -0700[diff] [blame^]107 u32 guaranteed_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]108 u32 highest_perf;
109 u32 nominal_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]110 u32 lowest_perf;
Prakash, Prashanth368520a2017-03-29 13:49:59 -0600[diff] [blame]111 u32 lowest_nonlinear_perf;
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]112 u32 lowest_freq;
113 u32 nominal_freq;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]114};
115
116struct cppc_perf_ctrls {
117 u32 max_perf;
118 u32 min_perf;
119 u32 desired_perf;
120};
121
122struct cppc_perf_fb_ctrs {
123 u64 reference;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]124 u64 delivered;
Ashwin Chaugule158c9982016-08-16 14:39:42 -0600[diff] [blame]125 u64 reference_perf;
Prakash, Prashanth2c74d842017-03-29 13:50:00 -0600[diff] [blame]126 u64 wraparound_time;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]127};
128
129/* Per CPU container for runtime CPPC management. */
Srinivas Pandruvada41dd6402016-09-01 13:37:11 -0700[diff] [blame]130struct cppc_cpudata {
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]131 int cpu;
132 struct cppc_perf_caps perf_caps;
133 struct cppc_perf_ctrls perf_ctrls;
134 struct cppc_perf_fb_ctrs perf_fb_ctrs;
135 struct cpufreq_policy *cur_policy;
136 unsigned int shared_type;
137 cpumask_var_t shared_cpu_map;
138};
139
140extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
141extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
142extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
Srinivas Pandruvada41dd6402016-09-01 13:37:11 -0700[diff] [blame]143extern int acpi_get_psd_map(struct cppc_cpudata **);
Prakash, Prashanthbe8b88d2016-08-16 14:39:41 -0600[diff] [blame]144extern unsigned int cppc_get_transition_latency(int cpu);
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]145
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]146#endif /* _CPPC_ACPI_H*/