Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 21 | static void dynamic_irq_init_x(unsigned int irq, bool keep_chip_data) |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 22 | { |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 23 | struct irq_desc *desc; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 24 | unsigned long flags; |
| 25 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 26 | desc = irq_to_desc(irq); |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 27 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 28 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 29 | return; |
| 30 | } |
| 31 | |
| 32 | /* Ensure we don't have left over values from a previous use of this irq */ |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 33 | raw_spin_lock_irqsave(&desc->lock, flags); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 34 | desc->status = IRQ_DISABLED; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 35 | desc->irq_data.chip = &no_irq_chip; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 36 | desc->handle_irq = handle_bad_irq; |
| 37 | desc->depth = 1; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 38 | desc->irq_data.msi_desc = NULL; |
| 39 | desc->irq_data.handler_data = NULL; |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 40 | if (!keep_chip_data) |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 41 | desc->irq_data.chip_data = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 42 | desc->action = NULL; |
| 43 | desc->irq_count = 0; |
| 44 | desc->irqs_unhandled = 0; |
| 45 | #ifdef CONFIG_SMP |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 46 | cpumask_setall(desc->irq_data.affinity); |
Mike Travis | 7f7ace0 | 2009-01-10 21:58:08 -0800 | [diff] [blame] | 47 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
| 48 | cpumask_clear(desc->pending_mask); |
| 49 | #endif |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 50 | #endif |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 51 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | /** |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 55 | * dynamic_irq_init - initialize a dynamically allocated irq |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 56 | * @irq: irq number to initialize |
| 57 | */ |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 58 | void dynamic_irq_init(unsigned int irq) |
| 59 | { |
| 60 | dynamic_irq_init_x(irq, false); |
| 61 | } |
| 62 | |
| 63 | /** |
| 64 | * dynamic_irq_init_keep_chip_data - initialize a dynamically allocated irq |
| 65 | * @irq: irq number to initialize |
| 66 | * |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 67 | * does not set irq_to_desc(irq)->irq_data.chip_data to NULL |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 68 | */ |
| 69 | void dynamic_irq_init_keep_chip_data(unsigned int irq) |
| 70 | { |
| 71 | dynamic_irq_init_x(irq, true); |
| 72 | } |
| 73 | |
| 74 | static void dynamic_irq_cleanup_x(unsigned int irq, bool keep_chip_data) |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 75 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 76 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 77 | unsigned long flags; |
| 78 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 79 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 80 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 81 | return; |
| 82 | } |
| 83 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 84 | raw_spin_lock_irqsave(&desc->lock, flags); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 85 | if (desc->action) { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 86 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 87 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 88 | irq); |
Eric W. Biederman | 1f80025 | 2006-10-04 02:16:56 -0700 | [diff] [blame] | 89 | return; |
| 90 | } |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 91 | desc->irq_data.msi_desc = NULL; |
| 92 | desc->irq_data.handler_data = NULL; |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 93 | if (!keep_chip_data) |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 94 | desc->irq_data.chip_data = NULL; |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 95 | desc->handle_irq = handle_bad_irq; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 96 | desc->irq_data.chip = &no_irq_chip; |
Dean Nelson | b6f3b78 | 2008-10-18 16:06:56 -0700 | [diff] [blame] | 97 | desc->name = NULL; |
Yinghai Lu | 0f3c2a8 | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 98 | clear_kstat_irqs(desc); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 99 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 100 | } |
| 101 | |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 102 | /** |
| 103 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq |
| 104 | * @irq: irq number to initialize |
| 105 | */ |
| 106 | void dynamic_irq_cleanup(unsigned int irq) |
| 107 | { |
| 108 | dynamic_irq_cleanup_x(irq, false); |
| 109 | } |
| 110 | |
| 111 | /** |
| 112 | * dynamic_irq_cleanup_keep_chip_data - cleanup a dynamically allocated irq |
| 113 | * @irq: irq number to initialize |
| 114 | * |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 115 | * does not set irq_to_desc(irq)->irq_data.chip_data to NULL |
Brandon Phiilps | ced5b69 | 2010-02-10 01:20:06 -0800 | [diff] [blame] | 116 | */ |
| 117 | void dynamic_irq_cleanup_keep_chip_data(unsigned int irq) |
| 118 | { |
| 119 | dynamic_irq_cleanup_x(irq, true); |
| 120 | } |
| 121 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 122 | |
| 123 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 124 | * set_irq_chip - set the irq chip for an irq |
| 125 | * @irq: irq number |
| 126 | * @chip: pointer to irq chip description structure |
| 127 | */ |
| 128 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) |
| 129 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 130 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 131 | unsigned long flags; |
| 132 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 133 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 134 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 135 | return -EINVAL; |
| 136 | } |
| 137 | |
| 138 | if (!chip) |
| 139 | chip = &no_irq_chip; |
| 140 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 141 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 142 | irq_chip_set_defaults(chip); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 143 | desc->irq_data.chip = chip; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 144 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 145 | |
| 146 | return 0; |
| 147 | } |
| 148 | EXPORT_SYMBOL(set_irq_chip); |
| 149 | |
| 150 | /** |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 151 | * set_irq_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 152 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 153 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 154 | */ |
| 155 | int set_irq_type(unsigned int irq, unsigned int type) |
| 156 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 157 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 158 | unsigned long flags; |
| 159 | int ret = -ENXIO; |
| 160 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 161 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 162 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
| 163 | return -ENODEV; |
| 164 | } |
| 165 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 166 | type &= IRQ_TYPE_SENSE_MASK; |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 167 | if (type == IRQ_TYPE_NONE) |
| 168 | return 0; |
| 169 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 170 | raw_spin_lock_irqsave(&desc->lock, flags); |
Chris Friesen | 0b3682ba3 | 2008-10-20 12:41:58 -0600 | [diff] [blame] | 171 | ret = __irq_set_trigger(desc, irq, type); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 172 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 173 | return ret; |
| 174 | } |
| 175 | EXPORT_SYMBOL(set_irq_type); |
| 176 | |
| 177 | /** |
| 178 | * set_irq_data - set irq type data for an irq |
| 179 | * @irq: Interrupt number |
| 180 | * @data: Pointer to interrupt specific data |
| 181 | * |
| 182 | * Set the hardware irq controller data for an irq |
| 183 | */ |
| 184 | int set_irq_data(unsigned int irq, void *data) |
| 185 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 186 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 187 | unsigned long flags; |
| 188 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 189 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 190 | printk(KERN_ERR |
| 191 | "Trying to install controller data for IRQ%d\n", irq); |
| 192 | return -EINVAL; |
| 193 | } |
| 194 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 195 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 196 | desc->irq_data.handler_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 197 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 198 | return 0; |
| 199 | } |
| 200 | EXPORT_SYMBOL(set_irq_data); |
| 201 | |
| 202 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 203 | * set_irq_msi - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 204 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 205 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 206 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 207 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 208 | */ |
| 209 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) |
| 210 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 211 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 212 | unsigned long flags; |
| 213 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 214 | if (!desc) { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 215 | printk(KERN_ERR |
| 216 | "Trying to install msi data for IRQ%d\n", irq); |
| 217 | return -EINVAL; |
| 218 | } |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 219 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 220 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 221 | desc->irq_data.msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 222 | if (entry) |
| 223 | entry->irq = irq; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 224 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 225 | return 0; |
| 226 | } |
| 227 | |
| 228 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 229 | * set_irq_chip_data - set irq chip data for an irq |
| 230 | * @irq: Interrupt number |
| 231 | * @data: Pointer to chip specific data |
| 232 | * |
| 233 | * Set the hardware irq chip data for an irq |
| 234 | */ |
| 235 | int set_irq_chip_data(unsigned int irq, void *data) |
| 236 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 237 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 238 | unsigned long flags; |
| 239 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 240 | if (!desc) { |
| 241 | printk(KERN_ERR |
| 242 | "Trying to install chip data for IRQ%d\n", irq); |
| 243 | return -EINVAL; |
| 244 | } |
| 245 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 246 | if (!desc->irq_data.chip) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 247 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
| 248 | return -EINVAL; |
| 249 | } |
| 250 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 251 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 252 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 253 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | EXPORT_SYMBOL(set_irq_chip_data); |
| 258 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 259 | /** |
| 260 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq |
| 261 | * |
| 262 | * @irq: Interrupt number |
| 263 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag |
| 264 | * |
| 265 | * The IRQ_NESTED_THREAD flag indicates that on |
| 266 | * request_threaded_irq() no separate interrupt thread should be |
| 267 | * created for the irq as the handler are called nested in the |
| 268 | * context of a demultiplexing interrupt handler thread. |
| 269 | */ |
| 270 | void set_irq_nested_thread(unsigned int irq, int nest) |
| 271 | { |
| 272 | struct irq_desc *desc = irq_to_desc(irq); |
| 273 | unsigned long flags; |
| 274 | |
| 275 | if (!desc) |
| 276 | return; |
| 277 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 278 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 279 | if (nest) |
| 280 | desc->status |= IRQ_NESTED_THREAD; |
| 281 | else |
| 282 | desc->status &= ~IRQ_NESTED_THREAD; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 283 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 284 | } |
| 285 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); |
| 286 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 287 | /* |
| 288 | * default enable function |
| 289 | */ |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 290 | static void default_enable(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 291 | { |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 292 | struct irq_desc *desc = irq_data_to_desc(data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 293 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 294 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 295 | desc->status &= ~IRQ_MASKED; |
| 296 | } |
| 297 | |
| 298 | /* |
| 299 | * default disable function |
| 300 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 301 | static void default_disable(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 302 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | /* |
| 306 | * default startup function |
| 307 | */ |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 308 | static unsigned int default_startup(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 309 | { |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 310 | struct irq_desc *desc = irq_data_to_desc(data); |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 311 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 312 | desc->irq_data.chip->irq_enable(data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | /* |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 317 | * default shutdown function |
| 318 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 319 | static void default_shutdown(struct irq_data *data) |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 320 | { |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 321 | struct irq_desc *desc = irq_data_to_desc(data); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 322 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 323 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 324 | desc->status |= IRQ_MASKED; |
| 325 | } |
| 326 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 327 | /* Temporary migration helpers */ |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 328 | static void compat_irq_mask(struct irq_data *data) |
| 329 | { |
| 330 | data->chip->mask(data->irq); |
| 331 | } |
| 332 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 333 | static void compat_irq_unmask(struct irq_data *data) |
| 334 | { |
| 335 | data->chip->unmask(data->irq); |
| 336 | } |
| 337 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 338 | static void compat_irq_ack(struct irq_data *data) |
| 339 | { |
| 340 | data->chip->ack(data->irq); |
| 341 | } |
| 342 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 343 | static void compat_irq_mask_ack(struct irq_data *data) |
| 344 | { |
| 345 | data->chip->mask_ack(data->irq); |
| 346 | } |
| 347 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 348 | static void compat_irq_eoi(struct irq_data *data) |
| 349 | { |
| 350 | data->chip->eoi(data->irq); |
| 351 | } |
| 352 | |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 353 | static void compat_irq_enable(struct irq_data *data) |
| 354 | { |
| 355 | data->chip->enable(data->irq); |
| 356 | } |
| 357 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 358 | static void compat_irq_disable(struct irq_data *data) |
| 359 | { |
| 360 | data->chip->disable(data->irq); |
| 361 | } |
| 362 | |
| 363 | static void compat_irq_shutdown(struct irq_data *data) |
| 364 | { |
| 365 | data->chip->shutdown(data->irq); |
| 366 | } |
| 367 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 368 | static unsigned int compat_irq_startup(struct irq_data *data) |
| 369 | { |
| 370 | return data->chip->startup(data->irq); |
| 371 | } |
| 372 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 373 | static int compat_irq_set_affinity(struct irq_data *data, |
| 374 | const struct cpumask *dest, bool force) |
| 375 | { |
| 376 | return data->chip->set_affinity(data->irq, dest); |
| 377 | } |
| 378 | |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 379 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
| 380 | { |
| 381 | return data->chip->set_type(data->irq, type); |
| 382 | } |
| 383 | |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame^] | 384 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
| 385 | { |
| 386 | return data->chip->set_wake(data->irq, on); |
| 387 | } |
| 388 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 389 | static void compat_bus_lock(struct irq_data *data) |
| 390 | { |
| 391 | data->chip->bus_lock(data->irq); |
| 392 | } |
| 393 | |
| 394 | static void compat_bus_sync_unlock(struct irq_data *data) |
| 395 | { |
| 396 | data->chip->bus_sync_unlock(data->irq); |
| 397 | } |
| 398 | |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 399 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 400 | * Fixup enable/disable function pointers |
| 401 | */ |
| 402 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 403 | { |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 404 | /* |
| 405 | * Compat fixup functions need to be before we set the |
| 406 | * defaults for enable/disable/startup/shutdown |
| 407 | */ |
| 408 | if (chip->enable) |
| 409 | chip->irq_enable = compat_irq_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 410 | if (chip->disable) |
| 411 | chip->irq_disable = compat_irq_disable; |
| 412 | if (chip->shutdown) |
| 413 | chip->irq_shutdown = compat_irq_shutdown; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 414 | if (chip->startup) |
| 415 | chip->irq_startup = compat_irq_startup; |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 416 | |
| 417 | /* |
| 418 | * The real defaults |
| 419 | */ |
| 420 | if (!chip->irq_enable) |
| 421 | chip->irq_enable = default_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 422 | if (!chip->irq_disable) |
| 423 | chip->irq_disable = default_disable; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 424 | if (!chip->irq_startup) |
| 425 | chip->irq_startup = default_startup; |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 426 | /* |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 427 | * We use chip->irq_disable, when the user provided its own. When |
| 428 | * we have default_disable set for chip->irq_disable, then we need |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 429 | * to use default_shutdown, otherwise the irq line is not |
| 430 | * disabled on free_irq(): |
| 431 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 432 | if (!chip->irq_shutdown) |
| 433 | chip->irq_shutdown = chip->irq_disable != default_disable ? |
| 434 | chip->irq_disable : default_shutdown; |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 435 | if (!chip->end) |
| 436 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 437 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 438 | /* |
| 439 | * Now fix up the remaining compat handlers |
| 440 | */ |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 441 | if (chip->bus_lock) |
| 442 | chip->irq_bus_lock = compat_bus_lock; |
| 443 | if (chip->bus_sync_unlock) |
| 444 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 445 | if (chip->mask) |
| 446 | chip->irq_mask = compat_irq_mask; |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 447 | if (chip->unmask) |
| 448 | chip->irq_unmask = compat_irq_unmask; |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 449 | if (chip->ack) |
| 450 | chip->irq_ack = compat_irq_ack; |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 451 | if (chip->mask_ack) |
| 452 | chip->irq_mask_ack = compat_irq_mask_ack; |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 453 | if (chip->eoi) |
| 454 | chip->irq_eoi = compat_irq_eoi; |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 455 | if (chip->set_affinity) |
| 456 | chip->irq_set_affinity = compat_irq_set_affinity; |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 457 | if (chip->set_type) |
| 458 | chip->irq_set_type = compat_irq_set_type; |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame^] | 459 | if (chip->set_wake) |
| 460 | chip->irq_set_wake = compat_irq_set_wake; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 461 | } |
| 462 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 463 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 464 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 465 | if (desc->irq_data.chip->irq_mask_ack) |
| 466 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 467 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 468 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 469 | if (desc->irq_data.chip->irq_ack) |
| 470 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 471 | } |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 472 | desc->status |= IRQ_MASKED; |
| 473 | } |
| 474 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 475 | static inline void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 476 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 477 | if (desc->irq_data.chip->irq_mask) { |
| 478 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 479 | desc->status |= IRQ_MASKED; |
| 480 | } |
| 481 | } |
| 482 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 483 | static inline void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 484 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 485 | if (desc->irq_data.chip->irq_unmask) { |
| 486 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 487 | desc->status &= ~IRQ_MASKED; |
| 488 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 489 | } |
| 490 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 491 | /* |
| 492 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 493 | * @irq: the interrupt number |
| 494 | * |
| 495 | * Handle interrupts which are nested into a threaded interrupt |
| 496 | * handler. The handler function is called inside the calling |
| 497 | * threads context. |
| 498 | */ |
| 499 | void handle_nested_irq(unsigned int irq) |
| 500 | { |
| 501 | struct irq_desc *desc = irq_to_desc(irq); |
| 502 | struct irqaction *action; |
| 503 | irqreturn_t action_ret; |
| 504 | |
| 505 | might_sleep(); |
| 506 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 507 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 508 | |
| 509 | kstat_incr_irqs_this_cpu(irq, desc); |
| 510 | |
| 511 | action = desc->action; |
| 512 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
| 513 | goto out_unlock; |
| 514 | |
| 515 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 516 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 517 | |
| 518 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 519 | if (!noirqdebug) |
| 520 | note_interrupt(irq, desc, action_ret); |
| 521 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 522 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 523 | desc->status &= ~IRQ_INPROGRESS; |
| 524 | |
| 525 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 526 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 527 | } |
| 528 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 529 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 530 | /** |
| 531 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 532 | * @irq: the interrupt number |
| 533 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 534 | * |
| 535 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 536 | * handler or come from hardware, where no interrupt hardware control |
| 537 | * is necessary. |
| 538 | * |
| 539 | * Note: The caller is expected to handle the ack, clear, mask and |
| 540 | * unmask issues if necessary. |
| 541 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 542 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 543 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | { |
| 545 | struct irqaction *action; |
| 546 | irqreturn_t action_ret; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 547 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 548 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 549 | |
| 550 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 551 | goto out_unlock; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 552 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 553 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 554 | |
| 555 | action = desc->action; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 556 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 557 | goto out_unlock; |
| 558 | |
| 559 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 560 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 561 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 562 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 563 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 564 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 565 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 566 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 567 | desc->status &= ~IRQ_INPROGRESS; |
| 568 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 569 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | /** |
| 573 | * handle_level_irq - Level type irq handler |
| 574 | * @irq: the interrupt number |
| 575 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 576 | * |
| 577 | * Level type interrupts are active as long as the hardware line has |
| 578 | * the active level. This may require to mask the interrupt and unmask |
| 579 | * it after the associated handler has acknowledged the device, so the |
| 580 | * interrupt line is back to inactive. |
| 581 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 582 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 583 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 585 | struct irqaction *action; |
| 586 | irqreturn_t action_ret; |
| 587 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 588 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 589 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 590 | |
| 591 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 592 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 593 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 594 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 595 | |
| 596 | /* |
| 597 | * If its disabled or no action available |
| 598 | * keep it masked and get out of here |
| 599 | */ |
| 600 | action = desc->action; |
Thomas Gleixner | 4966342 | 2007-08-12 15:46:34 +0000 | [diff] [blame] | 601 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 602 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 | |
| 604 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 605 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 606 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 607 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 608 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 609 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 610 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 611 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 612 | desc->status &= ~IRQ_INPROGRESS; |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 613 | |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 614 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 615 | unmask_irq(desc); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 616 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 617 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 618 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 619 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 620 | |
| 621 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 622 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 623 | * @irq: the interrupt number |
| 624 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 625 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 626 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 627 | * call when the interrupt has been serviced. This enables support |
| 628 | * for modern forms of interrupt handlers, which handle the flow |
| 629 | * details in hardware, transparently. |
| 630 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 631 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 632 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 633 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 634 | struct irqaction *action; |
| 635 | irqreturn_t action_ret; |
| 636 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 637 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 638 | |
| 639 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 640 | goto out; |
| 641 | |
| 642 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 643 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 644 | |
| 645 | /* |
| 646 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 647 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 648 | */ |
| 649 | action = desc->action; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 650 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
| 651 | desc->status |= IRQ_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 652 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 653 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 654 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 655 | |
| 656 | desc->status |= IRQ_INPROGRESS; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 657 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 658 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 659 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 660 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 661 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 662 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 663 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 664 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 665 | desc->status &= ~IRQ_INPROGRESS; |
| 666 | out: |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 667 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 668 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 669 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | /** |
| 673 | * handle_edge_irq - edge type IRQ handler |
| 674 | * @irq: the interrupt number |
| 675 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 676 | * |
| 677 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 678 | * signal. The occurence is latched into the irq controller hardware |
| 679 | * and must be acked in order to be reenabled. After the ack another |
| 680 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 681 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 682 | * might be necessary to disable (mask) the interrupt depending on the |
| 683 | * controller hardware. This requires to reenable the interrupt inside |
| 684 | * of the loop which handles the interrupts which have arrived while |
| 685 | * the handler was running. If all pending interrupts are handled, the |
| 686 | * loop is left. |
| 687 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 688 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 689 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 690 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 691 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 692 | |
| 693 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
| 694 | |
| 695 | /* |
| 696 | * If we're currently running this IRQ, or its disabled, |
| 697 | * we shouldn't process the IRQ. Mark it pending, handle |
| 698 | * the necessary masking and go out |
| 699 | */ |
| 700 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || |
| 701 | !desc->action)) { |
| 702 | desc->status |= (IRQ_PENDING | IRQ_MASKED); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 703 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 704 | goto out_unlock; |
| 705 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 706 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 707 | |
| 708 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 709 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 710 | |
| 711 | /* Mark the IRQ currently in progress.*/ |
| 712 | desc->status |= IRQ_INPROGRESS; |
| 713 | |
| 714 | do { |
| 715 | struct irqaction *action = desc->action; |
| 716 | irqreturn_t action_ret; |
| 717 | |
| 718 | if (unlikely(!action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 719 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 720 | goto out_unlock; |
| 721 | } |
| 722 | |
| 723 | /* |
| 724 | * When another irq arrived while we were handling |
| 725 | * one, we could have masked the irq. |
| 726 | * Renable it, if it was not disabled in meantime. |
| 727 | */ |
| 728 | if (unlikely((desc->status & |
| 729 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == |
| 730 | (IRQ_PENDING | IRQ_MASKED))) { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 731 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 732 | } |
| 733 | |
| 734 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 735 | raw_spin_unlock(&desc->lock); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 736 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 737 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 738 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 739 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 740 | |
| 741 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); |
| 742 | |
| 743 | desc->status &= ~IRQ_INPROGRESS; |
| 744 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 745 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 746 | } |
| 747 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 748 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 749 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 750 | * @irq: the interrupt number |
| 751 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 752 | * |
| 753 | * Per CPU interrupts on SMP machines without locking requirements |
| 754 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 755 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 756 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 757 | { |
| 758 | irqreturn_t action_ret; |
| 759 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 760 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 761 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 762 | if (desc->irq_data.chip->irq_ack) |
| 763 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 764 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 765 | action_ret = handle_IRQ_event(irq, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 766 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 767 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 768 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 769 | if (desc->irq_data.chip->irq_eoi) |
| 770 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 771 | } |
| 772 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 773 | void |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 774 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 775 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 776 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 777 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 778 | unsigned long flags; |
| 779 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 780 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 781 | printk(KERN_ERR |
| 782 | "Trying to install type control for IRQ%d\n", irq); |
| 783 | return; |
| 784 | } |
| 785 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 786 | if (!handle) |
| 787 | handle = handle_bad_irq; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 788 | else if (desc->irq_data.chip == &no_irq_chip) { |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 789 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
Geert Uytterhoeven | b039db8 | 2006-12-20 15:59:48 +0100 | [diff] [blame] | 790 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 791 | /* |
| 792 | * Some ARM implementations install a handler for really dumb |
| 793 | * interrupt hardware without setting an irq_chip. This worked |
| 794 | * with the ARM no_irq_chip but the check in setup_irq would |
| 795 | * prevent us to setup the interrupt at all. Switch it to |
| 796 | * dummy_irq_chip for easy transition. |
| 797 | */ |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 798 | desc->irq_data.chip = &dummy_irq_chip; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 799 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 800 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 801 | chip_bus_lock(desc); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 802 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 803 | |
| 804 | /* Uninstall? */ |
| 805 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 806 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 807 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 808 | desc->status |= IRQ_DISABLED; |
| 809 | desc->depth = 1; |
| 810 | } |
| 811 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 812 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 813 | |
| 814 | if (handle != handle_bad_irq && is_chained) { |
| 815 | desc->status &= ~IRQ_DISABLED; |
| 816 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
| 817 | desc->depth = 0; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 818 | desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 819 | } |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 820 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 821 | chip_bus_sync_unlock(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 822 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 823 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 824 | |
| 825 | void |
| 826 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 827 | irq_flow_handler_t handle) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 828 | { |
| 829 | set_irq_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 830 | __set_irq_handler(irq, handle, 0, NULL); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 831 | } |
| 832 | |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 833 | void |
| 834 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
| 835 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 836 | { |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 837 | set_irq_chip(irq, chip); |
| 838 | __set_irq_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 839 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 840 | |
Henrik Kretzschmar | 860652b | 2010-03-24 12:59:20 +0100 | [diff] [blame] | 841 | void set_irq_noprobe(unsigned int irq) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 842 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 843 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 844 | unsigned long flags; |
| 845 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 846 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 847 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 848 | return; |
| 849 | } |
| 850 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 851 | raw_spin_lock_irqsave(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 852 | desc->status |= IRQ_NOPROBE; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 853 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 854 | } |
| 855 | |
Henrik Kretzschmar | 860652b | 2010-03-24 12:59:20 +0100 | [diff] [blame] | 856 | void set_irq_probe(unsigned int irq) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 857 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 858 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 859 | unsigned long flags; |
| 860 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 861 | if (!desc) { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 862 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 863 | return; |
| 864 | } |
| 865 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 866 | raw_spin_lock_irqsave(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 867 | desc->status &= ~IRQ_NOPROBE; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 868 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 869 | } |