blob: d53a175dc17a25ad957704674060a8cb93d348d3 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Marc Dietrichcc2afa42011-11-01 10:37:05 +00002/dts-v1/;
3
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05304#include <dt-bindings/input/input.h>
Dmitry Osipenko2e099082021-05-10 23:25:56 +03005#include <dt-bindings/thermal/thermal.h>
6
Stephen Warren1bd0bd42012-10-17 16:38:21 -06007#include "tegra20.dtsi"
Dmitry Osipenko5ac15052019-10-25 01:14:13 +03008#include "tegra20-cpu-opp.dtsi"
9#include "tegra20-cpu-opp-microvolt.dtsi"
Marc Dietrichcc2afa42011-11-01 10:37:05 +000010
11/ {
12 model = "Toshiba AC100 / Dynabook AZ";
13 compatible = "compal,paz00", "nvidia,tegra20";
14
Stephen Warren553c0a22013-12-09 14:43:59 -070015 aliases {
16 rtc0 = "/i2c@7000d000/tps6586x@34";
17 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080018 serial0 = &uarta;
19 serial1 = &uartc;
Stephen Warren553c0a22013-12-09 14:43:59 -070020 };
21
Jon Hunterf5bbb322016-02-09 13:51:59 +000022 chosen {
23 stdout-path = "serial0:115200n8";
24 };
25
Krzysztof Kozlowski48299762018-07-09 18:05:17 +020026 memory@0 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000027 reg = <0x00000000 0x20000000>;
28 };
29
Stephen Warren58ecb232013-11-25 17:53:16 -070030 host1x@50000000 {
Marc Dietrich58168982013-12-21 21:38:13 +010031 dc@54200000 {
32 rgb {
33 status = "okay";
34
35 nvidia,panel = <&panel>;
36 };
37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -070039 hdmi@54280000 {
Stephen Warren11a3c862013-01-02 14:53:22 -070040 status = "okay";
41
42 vdd-supply = <&hdmi_vdd_reg>;
43 pll-supply = <&hdmi_pll_reg>;
44
45 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070046 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
47 GPIO_ACTIVE_HIGH>;
Stephen Warren11a3c862013-01-02 14:53:22 -070048 };
49 };
50
Stephen Warren58ecb232013-11-25 17:53:16 -070051 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060052 pinctrl-names = "default";
53 pinctrl-0 = <&state_default>;
54
55 state_default: pinmux {
56 ata {
57 nvidia,pins = "ata", "atc", "atd", "ate",
58 "dap2", "gmb", "gmc", "gmd", "spia",
59 "spib", "spic", "spid", "spie";
60 nvidia,function = "gmi";
61 };
62 atb {
63 nvidia,pins = "atb", "gma", "gme";
64 nvidia,function = "sdio4";
65 };
66 cdev1 {
67 nvidia,pins = "cdev1";
68 nvidia,function = "plla_out";
69 };
70 cdev2 {
71 nvidia,pins = "cdev2";
72 nvidia,function = "pllp_out4";
73 };
74 crtp {
75 nvidia,pins = "crtp";
76 nvidia,function = "crt";
77 };
78 csus {
79 nvidia,pins = "csus";
80 nvidia,function = "pllc_out1";
81 };
82 dap1 {
83 nvidia,pins = "dap1";
84 nvidia,function = "dap1";
85 };
86 dap3 {
87 nvidia,pins = "dap3";
88 nvidia,function = "dap3";
89 };
90 dap4 {
91 nvidia,pins = "dap4";
92 nvidia,function = "dap4";
93 };
94 ddc {
95 nvidia,pins = "ddc";
96 nvidia,function = "i2c2";
97 };
98 dta {
99 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
100 nvidia,function = "rsvd1";
101 };
102 dtf {
103 nvidia,pins = "dtf";
104 nvidia,function = "i2c3";
105 };
106 gpu {
107 nvidia,pins = "gpu", "sdb", "sdd";
108 nvidia,function = "pwm";
109 };
110 gpu7 {
111 nvidia,pins = "gpu7";
112 nvidia,function = "rtck";
113 };
114 gpv {
115 nvidia,pins = "gpv", "slxa", "slxk";
116 nvidia,function = "pcie";
117 };
118 hdint {
119 nvidia,pins = "hdint", "pta";
120 nvidia,function = "hdmi";
121 };
122 i2cp {
123 nvidia,pins = "i2cp";
124 nvidia,function = "i2cp";
125 };
126 irrx {
127 nvidia,pins = "irrx", "irtx";
128 nvidia,function = "uarta";
129 };
130 kbca {
131 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
132 nvidia,function = "kbc";
133 };
134 kbcb {
135 nvidia,pins = "kbcb", "kbcd";
136 nvidia,function = "sdio2";
137 };
138 lcsn {
139 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
140 "ld3", "ld4", "ld5", "ld6", "ld7",
141 "ld8", "ld9", "ld10", "ld11", "ld12",
142 "ld13", "ld14", "ld15", "ld16", "ld17",
143 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
144 "lhs", "lm0", "lm1", "lpp", "lpw0",
145 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
146 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
147 "lvs";
148 nvidia,function = "displaya";
149 };
150 owc {
151 nvidia,pins = "owc";
152 nvidia,function = "owr";
153 };
154 pmc {
155 nvidia,pins = "pmc";
156 nvidia,function = "pwr_on";
157 };
158 rm {
159 nvidia,pins = "rm";
160 nvidia,function = "i2c1";
161 };
162 sdc {
163 nvidia,pins = "sdc";
164 nvidia,function = "twc";
165 };
166 sdio1 {
167 nvidia,pins = "sdio1";
168 nvidia,function = "sdio1";
169 };
170 slxc {
171 nvidia,pins = "slxc", "slxd";
172 nvidia,function = "spi4";
173 };
174 spdi {
175 nvidia,pins = "spdi", "spdo";
176 nvidia,function = "rsvd2";
177 };
178 spif {
179 nvidia,pins = "spif", "uac";
180 nvidia,function = "rsvd4";
181 };
182 spig {
183 nvidia,pins = "spig", "spih";
184 nvidia,function = "spi2_alt";
185 };
186 uaa {
187 nvidia,pins = "uaa", "uab", "uda";
188 nvidia,function = "ulpi";
189 };
190 uad {
191 nvidia,pins = "uad";
192 nvidia,function = "spdif";
193 };
194 uca {
195 nvidia,pins = "uca", "ucb";
196 nvidia,function = "uartc";
197 };
198 conf_ata {
199 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600200 "cdev1", "cdev2", "dap1", "dap2", "dtf",
201 "gma", "gmb", "gmc", "gmd", "gme",
202 "gpu", "gpu7", "gpv", "i2cp", "pta",
203 "rm", "sdio1", "slxk", "spdo", "uac",
204 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600207 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600208 conf_ck32 {
209 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
210 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600212 };
213 conf_crtp {
214 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
215 "dtc", "dte", "slxa", "slxc", "slxd",
216 "spdi";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600219 };
220 conf_csus {
221 nvidia,pins = "csus", "spia", "spib", "spid",
222 "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600225 };
226 conf_ddc {
227 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
228 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
229 "spic", "spig", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530230 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600232 };
233 conf_dta {
234 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
235 "spie", "spih", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530236 nvidia,pull = <TEGRA_PIN_PULL_UP>;
237 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600238 };
239 conf_hdint {
240 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
241 "ld3", "ld4", "ld5", "ld6", "ld7",
242 "ld8", "ld9", "ld10", "ld11", "ld12",
243 "ld13", "ld14", "ld15", "ld16", "ld17",
244 "ldc", "ldi", "lhs", "lsc0", "lspi",
245 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600247 };
248 conf_lc {
249 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530250 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600251 };
252 conf_lcsn {
253 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
254 "lm0", "lm1", "lpp", "lpw0", "lpw1",
255 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
256 "lvp0", "lvp1", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530257 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600258 };
259 conf_ld17_0 {
260 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
261 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600263 };
264 };
265 };
266
Dmitry Osipenko919be272021-12-04 17:37:25 +0300267 spdif@70002400 {
268 status = "okay";
269
270 nvidia,fixed-parent-rate;
271 };
272
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600273 i2s@70002800 {
274 status = "okay";
Dmitry Osipenko919be272021-12-04 17:37:25 +0300275
276 nvidia,fixed-parent-rate;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600277 };
278
279 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600280 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600281 };
282
Stephen Warrenc04abb32012-05-11 17:03:26 -0600283 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600284 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600285 };
286
Marc Dietrich58168982013-12-21 21:38:13 +0100287 pwm: pwm@7000a000 {
288 status = "okay";
289 };
290
291 lvds_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600292 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000293 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200294
295 alc5632: alc5632@1e {
296 compatible = "realtek,alc5632";
297 reg = <0x1e>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000301 };
302
Stephen Warren11a3c862013-01-02 14:53:22 -0700303 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600304 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700305 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000306 };
307
Stephen Warren58ecb232013-11-25 17:53:16 -0700308 nvec@7000c500 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000309 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600310 reg = <0x7000c500 0x100>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700311 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600312 #address-cells = <1>;
313 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000314 clock-frequency = <80000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700315 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000316 slave-addr = <138>;
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300317 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
Krzysztof Kozlowski06d561c2018-08-30 19:21:53 +0200318 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530319 clock-names = "div-clk", "fast-clk";
Stephen Warren3393d422013-11-06 14:01:16 -0700320 resets = <&tegra_car 67>;
321 reset-names = "i2c";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000322 };
323
Dmitry Osipenko834f1d62019-12-18 21:59:57 +0300324 memory-controller@7000f400 {
325 nvidia,use-ram-code;
326
Thierry Reding86b224b2020-06-11 19:55:48 +0200327 emc-tables@0 {
Dmitry Osipenko834f1d62019-12-18 21:59:57 +0300328 nvidia,ram-code = <0x0>;
329 #address-cells = <1>;
330 #size-cells = <0>;
Dmitry Osipenkob39a16b2021-05-10 23:25:54 +0300331 reg = <0>;
Dmitry Osipenko834f1d62019-12-18 21:59:57 +0300332
333 emc-table@166500 {
334 reg = <166500>;
335 compatible = "nvidia,tegra20-emc-table";
336 clock-frequency = <166500>;
337 nvidia,emc-registers = <0x0000000a 0x00000016
338 0x00000008 0x00000003 0x00000004 0x00000004
339 0x00000002 0x0000000c 0x00000003 0x00000003
340 0x00000002 0x00000001 0x00000004 0x00000005
341 0x00000004 0x00000009 0x0000000d 0x000004df
342 0x00000000 0x00000003 0x00000003 0x00000003
343 0x00000003 0x00000001 0x0000000a 0x000000c8
344 0x00000003 0x00000006 0x00000004 0x00000008
345 0x00000002 0x00000000 0x00000000 0x00000002
346 0x00000000 0x00000000 0x00000083 0xe03b0323
347 0x007fe010 0x00001414 0x00000000 0x00000000
348 0x00000000 0x00000000 0x00000000 0x00000000>;
349 };
350
351 emc-table@333000 {
352 reg = <333000>;
353 compatible = "nvidia,tegra20-emc-table";
354 clock-frequency = <333000>;
355 nvidia,emc-registers = <0x00000018 0x00000033
356 0x00000012 0x00000004 0x00000004 0x00000005
357 0x00000003 0x0000000c 0x00000006 0x00000006
358 0x00000003 0x00000001 0x00000004 0x00000005
359 0x00000004 0x00000009 0x0000000d 0x00000bff
360 0x00000000 0x00000003 0x00000003 0x00000006
361 0x00000006 0x00000001 0x00000011 0x000000c8
362 0x00000003 0x0000000e 0x00000007 0x00000008
363 0x00000002 0x00000000 0x00000000 0x00000002
364 0x00000000 0x00000000 0x00000083 0xf0440303
365 0x007fe010 0x00001414 0x00000000 0x00000000
366 0x00000000 0x00000000 0x00000000 0x00000000>;
367 };
368 };
369 };
370
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000371 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600372 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000373 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100374
Stephen Warren217b8f02012-06-21 14:24:57 -0600375 pmic: tps6586x@34 {
376 compatible = "ti,tps6586x";
377 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700378 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600379
380 #gpio-cells = <2>;
381 gpio-controller;
382
383 sys-supply = <&p5valw_reg>;
384 vin-sm0-supply = <&sys_reg>;
385 vin-sm1-supply = <&sys_reg>;
386 vin-sm2-supply = <&sys_reg>;
387 vinldo01-supply = <&sm2_reg>;
388 vinldo23-supply = <&sm2_reg>;
389 vinldo4-supply = <&sm2_reg>;
390 vinldo678-supply = <&sm2_reg>;
391 vinldo9-supply = <&sm2_reg>;
392
393 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600394 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600395 regulator-name = "vdd_sys";
396 regulator-always-on;
397 };
398
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300399 core_vdd_reg: sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600400 regulator-name = "+1.2vs_sm0,vdd_core";
Dmitry Osipenkod3cd0c32021-03-02 15:09:54 +0300401 regulator-min-microvolt = <950000>;
402 regulator-max-microvolt = <1300000>;
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300403 regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
Dmitry Osipenkod3cd0c32021-03-02 15:09:54 +0300404 regulator-coupled-max-spread = <170000 550000>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600405 regulator-always-on;
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300406
407 nvidia,tegra-core-regulator;
Stephen Warren217b8f02012-06-21 14:24:57 -0600408 };
409
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300410 cpu_vdd_reg: sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600411 regulator-name = "+1.0vs_sm1,vdd_cpu";
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300412 regulator-min-microvolt = <750000>;
413 regulator-max-microvolt = <1100000>;
414 regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
Dmitry Osipenkod3cd0c32021-03-02 15:09:54 +0300415 regulator-coupled-max-spread = <550000 550000>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600416 regulator-always-on;
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300417
418 nvidia,tegra-cpu-regulator;
Stephen Warren217b8f02012-06-21 14:24:57 -0600419 };
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600421 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600422 regulator-name = "+3.7vs_sm2,vin_ldo*";
423 regulator-min-microvolt = <3700000>;
424 regulator-max-microvolt = <3700000>;
425 regulator-always-on;
426 };
427
428 /* LDO0 is not connected to anything */
429
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600430 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600431 regulator-name = "+1.1vs_ldo1,avdd_pll*";
432 regulator-min-microvolt = <1100000>;
433 regulator-max-microvolt = <1100000>;
434 regulator-always-on;
435 };
436
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300437 rtc_vdd_reg: ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600438 regulator-name = "+1.2vs_ldo2,vdd_rtc";
Dmitry Osipenkod3cd0c32021-03-02 15:09:54 +0300439 regulator-min-microvolt = <950000>;
440 regulator-max-microvolt = <1300000>;
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300441 regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
Dmitry Osipenkod3cd0c32021-03-02 15:09:54 +0300442 regulator-coupled-max-spread = <170000 550000>;
Dmitry Osipenkoa60e68f2019-10-25 01:14:12 +0300443 regulator-always-on;
444
445 nvidia,tegra-rtc-regulator;
Stephen Warren217b8f02012-06-21 14:24:57 -0600446 };
447
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600448 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600449 regulator-name = "+3.3vs_ldo3,avdd_usb*";
450 regulator-min-microvolt = <3300000>;
451 regulator-max-microvolt = <3300000>;
452 regulator-always-on;
453 };
454
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600455 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600456 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 regulator-always-on;
460 };
461
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600462 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600463 regulator-name = "+2.85vs_ldo5,vcore_mmc";
464 regulator-min-microvolt = <2850000>;
465 regulator-max-microvolt = <2850000>;
466 regulator-always-on;
467 };
468
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600469 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600470 /*
471 * Research indicates this should be
472 * 1.8v; other boards that use this
473 * rail for the same purpose need it
474 * set to 1.8v. The schematic signal
475 * name is incorrect; perhaps copied
476 * from an incorrect NVIDIA reference.
477 */
478 regulator-name = "+2.85vs_ldo6,avdd_vdac";
479 regulator-min-microvolt = <1800000>;
480 regulator-max-microvolt = <1800000>;
481 };
482
Stephen Warren11a3c862013-01-02 14:53:22 -0700483 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600484 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 };
488
Stephen Warren11a3c862013-01-02 14:53:22 -0700489 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600490 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
491 regulator-min-microvolt = <1800000>;
492 regulator-max-microvolt = <1800000>;
493 };
494
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600495 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600496 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
497 regulator-min-microvolt = <2850000>;
498 regulator-max-microvolt = <2850000>;
499 regulator-always-on;
500 };
501
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600502 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600503 regulator-name = "+3.3vs_rtc";
504 regulator-min-microvolt = <3300000>;
505 regulator-max-microvolt = <3300000>;
506 regulator-always-on;
507 };
508 };
509 };
510
Dmitry Osipenko2e099082021-05-10 23:25:56 +0300511 adt7461: temperature-sensor@4c {
Marc Dietrich1266f892012-01-31 19:53:21 +0100512 compatible = "adi,adt7461";
513 reg = <0x4c>;
Dmitry Osipenko155bfaf2021-08-03 00:19:35 +0300514
515 interrupt-parent = <&gpio>;
516 interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
517
Dmitry Osipenko2e099082021-05-10 23:25:56 +0300518 #thermal-sensor-cells = <1>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100519 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000520 };
521
Stephen Warren58ecb232013-11-25 17:53:16 -0700522 pmc@7000e400 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600523 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800524 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800525 nvidia,cpu-pwr-good-time = <2000>;
526 nvidia,cpu-pwr-off-time = <0>;
527 nvidia,core-pwr-good-time = <3845 3845>;
528 nvidia,core-pwr-off-time = <0>;
529 nvidia,sys-clock-req-active-high;
Dmitry Osipenko83b7f0b2021-12-01 02:23:43 +0300530 core-supply = <&core_vdd_reg>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600531 };
532
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600533 usb@c5000000 {
Dmitry Osipenkoe3ff43b2017-08-16 13:32:45 +0300534 compatible = "nvidia,tegra20-udc";
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600535 status = "okay";
Dmitry Osipenkoe3ff43b2017-08-16 13:32:45 +0300536 dr_mode = "peripheral";
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600537 };
538
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530539 usb-phy@c5000000 {
540 status = "okay";
541 };
542
Stephen Warrenc04abb32012-05-11 17:03:26 -0600543 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600544 status = "okay";
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530545 };
546
547 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530548 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700549 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
550 GPIO_ACTIVE_LOW>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000551 };
552
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600553 usb@c5008000 {
554 status = "okay";
555 };
556
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530557 usb-phy@c5008000 {
558 status = "okay";
559 };
560
Thierry Reding32c096c2020-06-11 19:21:17 +0200561 mmc@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600562 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700563 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
564 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
565 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400566 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000567 };
568
Thierry Reding32c096c2020-06-11 19:21:17 +0200569 mmc@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600570 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400571 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600572 non-removable;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000573 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100574
Marc Dietrich58168982013-12-21 21:38:13 +0100575 backlight: backlight {
576 compatible = "pwm-backlight";
577
578 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
579 pwms = <&pwm 0 5000000>;
580
581 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
582 default-brightness-level = <10>;
Thierry Redingc98167b2021-12-07 13:59:59 +0100583
584 /* close enough */
585 power-supply = <&vdd_pnl_reg>;
Marc Dietrich58168982013-12-21 21:38:13 +0100586 };
587
David Heidelberg4f74ed82021-12-12 00:14:03 +0300588 clk32k_in: clock-32k {
Thierry Reding901c8652020-06-11 19:00:14 +0200589 compatible = "fixed-clock";
590 clock-frequency = <32768>;
591 #clock-cells = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800592 };
593
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100594 gpio-keys {
595 compatible = "gpio-keys";
596
Marc Dietrichebea2a42018-08-02 10:45:40 +0200597 wakeup {
598 label = "Wakeup";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700599 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
Marc Dietrichebea2a42018-08-02 10:45:40 +0200600 linux,code = <KEY_WAKEUP>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000601 wakeup-source;
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100602 };
603 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100604
605 gpio-leds {
606 compatible = "gpio-leds";
607
Thierry Redingeb711492020-06-11 19:56:47 +0200608 led-0 {
Marc Dietrich80c94732012-01-28 20:03:08 +0100609 label = "wifi-led";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700610 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Marc Dietrich80c94732012-01-28 20:03:08 +0100611 linux,default-trigger = "rfkill0";
612 };
613 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600614
Marc Dietrich58168982013-12-21 21:38:13 +0100615 panel: panel {
Rob Herring7860c872020-01-17 17:08:55 -0600616 compatible = "samsung,ltn101nt05";
Marc Dietrich58168982013-12-21 21:38:13 +0100617
618 ddc-i2c-bus = <&lvds_ddc>;
619 power-supply = <&vdd_pnl_reg>;
620 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
621
622 backlight = <&backlight>;
623 };
624
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300625 p5valw_reg: regulator-5v0alw {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200626 compatible = "regulator-fixed";
627 regulator-name = "+5valw";
628 regulator-min-microvolt = <5000000>;
629 regulator-max-microvolt = <5000000>;
630 regulator-always-on;
631 };
Stephen Warren217b8f02012-06-21 14:24:57 -0600632
Dmitry Osipenkoc6291962021-12-12 00:14:04 +0300633 vdd_pnl_reg: regulator-3v0 {
Thierry Reding1cf17aa2020-06-11 19:01:32 +0200634 compatible = "regulator-fixed";
635 regulator-name = "+3VS,vdd_pnl";
636 regulator-min-microvolt = <3300000>;
637 regulator-max-microvolt = <3300000>;
638 regulator-boot-on;
639 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
640 enable-active-high;
Stephen Warren217b8f02012-06-21 14:24:57 -0600641 };
642
Stephen Warrenc04abb32012-05-11 17:03:26 -0600643 sound {
644 compatible = "nvidia,tegra-audio-alc5632-paz00",
645 "nvidia,tegra-audio-alc5632";
646
647 nvidia,model = "Compal PAZ00";
648
649 nvidia,audio-routing =
650 "Int Spk", "SPKOUT",
651 "Int Spk", "SPKOUTN",
652 "Headset Mic", "MICBIAS1",
653 "MIC1", "Headset Mic",
654 "Headset Stereophone", "HPR",
655 "Headset Stereophone", "HPL",
656 "DMICDAT", "Digital Mic";
657
658 nvidia,audio-codec = <&alc5632>;
659 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700660 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
661 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600662
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300663 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
Krzysztof Kozlowski06d561c2018-08-30 19:21:53 +0200664 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
665 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600666 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600667 };
Dmitry Osipenko5ac15052019-10-25 01:14:13 +0300668
669 cpus {
670 cpu0: cpu@0 {
671 cpu-supply = <&cpu_vdd_reg>;
672 operating-points-v2 = <&cpu0_opp_table>;
Dmitry Osipenko2e099082021-05-10 23:25:56 +0300673 #cooling-cells = <2>;
Dmitry Osipenko5ac15052019-10-25 01:14:13 +0300674 };
675
Dmitry Osipenko2e099082021-05-10 23:25:56 +0300676 cpu1: cpu@1 {
Dmitry Osipenko5ac15052019-10-25 01:14:13 +0300677 cpu-supply = <&cpu_vdd_reg>;
678 operating-points-v2 = <&cpu0_opp_table>;
Dmitry Osipenko2e099082021-05-10 23:25:56 +0300679 #cooling-cells = <2>;
680 };
681 };
682
683 thermal-zones {
684 cpu-thermal {
685 polling-delay-passive = <500>; /* milliseconds */
686 polling-delay = <1500>; /* milliseconds */
687
688 thermal-sensors = <&adt7461 1>;
689
690 trips {
691 trip0: cpu-alert0 {
692 /* start throttling at 80C */
693 temperature = <80000>;
694 hysteresis = <200>;
695 type = "passive";
696 };
697
698 trip1: cpu-crit {
699 /* shut down at 85C */
700 temperature = <85000>;
701 hysteresis = <2000>;
702 type = "critical";
703 };
704 };
705
706 cooling-maps {
707 map0 {
708 trip = <&trip0>;
709 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
710 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
711 };
712 };
Dmitry Osipenko5ac15052019-10-25 01:14:13 +0300713 };
714 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000715};
Dmitry Osipenkof5204ac2020-11-23 03:27:21 +0300716
717&emc_icc_dvfs_opp_table {
Dmitry Osipenkoc6d4a892021-12-01 02:23:41 +0300718 /delete-node/ opp-760000000;
Dmitry Osipenkof5204ac2020-11-23 03:27:21 +0300719};