Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 4 | #include "tegra20.dtsi" |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 5 | |
| 6 | / { |
| 7 | model = "Toshiba AC100 / Dynabook AZ"; |
| 8 | compatible = "compal,paz00", "nvidia,tegra20"; |
| 9 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 10 | memory { |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 11 | reg = <0x00000000 0x20000000>; |
| 12 | }; |
| 13 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 14 | host1x@50000000 { |
| 15 | hdmi@54280000 { |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 16 | status = "okay"; |
| 17 | |
| 18 | vdd-supply = <&hdmi_vdd_reg>; |
| 19 | pll-supply = <&hdmi_pll_reg>; |
| 20 | |
| 21 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 22 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 23 | GPIO_ACTIVE_HIGH>; |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 24 | }; |
| 25 | }; |
| 26 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 27 | pinmux@70000014 { |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&state_default>; |
| 30 | |
| 31 | state_default: pinmux { |
| 32 | ata { |
| 33 | nvidia,pins = "ata", "atc", "atd", "ate", |
| 34 | "dap2", "gmb", "gmc", "gmd", "spia", |
| 35 | "spib", "spic", "spid", "spie"; |
| 36 | nvidia,function = "gmi"; |
| 37 | }; |
| 38 | atb { |
| 39 | nvidia,pins = "atb", "gma", "gme"; |
| 40 | nvidia,function = "sdio4"; |
| 41 | }; |
| 42 | cdev1 { |
| 43 | nvidia,pins = "cdev1"; |
| 44 | nvidia,function = "plla_out"; |
| 45 | }; |
| 46 | cdev2 { |
| 47 | nvidia,pins = "cdev2"; |
| 48 | nvidia,function = "pllp_out4"; |
| 49 | }; |
| 50 | crtp { |
| 51 | nvidia,pins = "crtp"; |
| 52 | nvidia,function = "crt"; |
| 53 | }; |
| 54 | csus { |
| 55 | nvidia,pins = "csus"; |
| 56 | nvidia,function = "pllc_out1"; |
| 57 | }; |
| 58 | dap1 { |
| 59 | nvidia,pins = "dap1"; |
| 60 | nvidia,function = "dap1"; |
| 61 | }; |
| 62 | dap3 { |
| 63 | nvidia,pins = "dap3"; |
| 64 | nvidia,function = "dap3"; |
| 65 | }; |
| 66 | dap4 { |
| 67 | nvidia,pins = "dap4"; |
| 68 | nvidia,function = "dap4"; |
| 69 | }; |
| 70 | ddc { |
| 71 | nvidia,pins = "ddc"; |
| 72 | nvidia,function = "i2c2"; |
| 73 | }; |
| 74 | dta { |
| 75 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 76 | nvidia,function = "rsvd1"; |
| 77 | }; |
| 78 | dtf { |
| 79 | nvidia,pins = "dtf"; |
| 80 | nvidia,function = "i2c3"; |
| 81 | }; |
| 82 | gpu { |
| 83 | nvidia,pins = "gpu", "sdb", "sdd"; |
| 84 | nvidia,function = "pwm"; |
| 85 | }; |
| 86 | gpu7 { |
| 87 | nvidia,pins = "gpu7"; |
| 88 | nvidia,function = "rtck"; |
| 89 | }; |
| 90 | gpv { |
| 91 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 92 | nvidia,function = "pcie"; |
| 93 | }; |
| 94 | hdint { |
| 95 | nvidia,pins = "hdint", "pta"; |
| 96 | nvidia,function = "hdmi"; |
| 97 | }; |
| 98 | i2cp { |
| 99 | nvidia,pins = "i2cp"; |
| 100 | nvidia,function = "i2cp"; |
| 101 | }; |
| 102 | irrx { |
| 103 | nvidia,pins = "irrx", "irtx"; |
| 104 | nvidia,function = "uarta"; |
| 105 | }; |
| 106 | kbca { |
| 107 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; |
| 108 | nvidia,function = "kbc"; |
| 109 | }; |
| 110 | kbcb { |
| 111 | nvidia,pins = "kbcb", "kbcd"; |
| 112 | nvidia,function = "sdio2"; |
| 113 | }; |
| 114 | lcsn { |
| 115 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", |
| 116 | "ld3", "ld4", "ld5", "ld6", "ld7", |
| 117 | "ld8", "ld9", "ld10", "ld11", "ld12", |
| 118 | "ld13", "ld14", "ld15", "ld16", "ld17", |
| 119 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", |
| 120 | "lhs", "lm0", "lm1", "lpp", "lpw0", |
| 121 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", |
| 122 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", |
| 123 | "lvs"; |
| 124 | nvidia,function = "displaya"; |
| 125 | }; |
| 126 | owc { |
| 127 | nvidia,pins = "owc"; |
| 128 | nvidia,function = "owr"; |
| 129 | }; |
| 130 | pmc { |
| 131 | nvidia,pins = "pmc"; |
| 132 | nvidia,function = "pwr_on"; |
| 133 | }; |
| 134 | rm { |
| 135 | nvidia,pins = "rm"; |
| 136 | nvidia,function = "i2c1"; |
| 137 | }; |
| 138 | sdc { |
| 139 | nvidia,pins = "sdc"; |
| 140 | nvidia,function = "twc"; |
| 141 | }; |
| 142 | sdio1 { |
| 143 | nvidia,pins = "sdio1"; |
| 144 | nvidia,function = "sdio1"; |
| 145 | }; |
| 146 | slxc { |
| 147 | nvidia,pins = "slxc", "slxd"; |
| 148 | nvidia,function = "spi4"; |
| 149 | }; |
| 150 | spdi { |
| 151 | nvidia,pins = "spdi", "spdo"; |
| 152 | nvidia,function = "rsvd2"; |
| 153 | }; |
| 154 | spif { |
| 155 | nvidia,pins = "spif", "uac"; |
| 156 | nvidia,function = "rsvd4"; |
| 157 | }; |
| 158 | spig { |
| 159 | nvidia,pins = "spig", "spih"; |
| 160 | nvidia,function = "spi2_alt"; |
| 161 | }; |
| 162 | uaa { |
| 163 | nvidia,pins = "uaa", "uab", "uda"; |
| 164 | nvidia,function = "ulpi"; |
| 165 | }; |
| 166 | uad { |
| 167 | nvidia,pins = "uad"; |
| 168 | nvidia,function = "spdif"; |
| 169 | }; |
| 170 | uca { |
| 171 | nvidia,pins = "uca", "ucb"; |
| 172 | nvidia,function = "uartc"; |
| 173 | }; |
| 174 | conf_ata { |
| 175 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 176 | "cdev1", "cdev2", "dap1", "dap2", "dtf", |
| 177 | "gma", "gmb", "gmc", "gmd", "gme", |
| 178 | "gpu", "gpu7", "gpv", "i2cp", "pta", |
| 179 | "rm", "sdio1", "slxk", "spdo", "uac", |
| 180 | "uda"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 183 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 184 | conf_ck32 { |
| 185 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 186 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 187 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 188 | }; |
| 189 | conf_crtp { |
| 190 | nvidia,pins = "crtp", "dap3", "dap4", "dtb", |
| 191 | "dtc", "dte", "slxa", "slxc", "slxd", |
| 192 | "spdi"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 193 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 194 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 195 | }; |
| 196 | conf_csus { |
| 197 | nvidia,pins = "csus", "spia", "spib", "spid", |
| 198 | "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 199 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 200 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 201 | }; |
| 202 | conf_ddc { |
| 203 | nvidia,pins = "ddc", "irrx", "irtx", "kbca", |
| 204 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", |
| 205 | "spic", "spig", "uaa", "uab"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 206 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 208 | }; |
| 209 | conf_dta { |
| 210 | nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", |
| 211 | "spie", "spih", "uad", "uca", "ucb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 212 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 213 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 214 | }; |
| 215 | conf_hdint { |
| 216 | nvidia,pins = "hdint", "ld0", "ld1", "ld2", |
| 217 | "ld3", "ld4", "ld5", "ld6", "ld7", |
| 218 | "ld8", "ld9", "ld10", "ld11", "ld12", |
| 219 | "ld13", "ld14", "ld15", "ld16", "ld17", |
| 220 | "ldc", "ldi", "lhs", "lsc0", "lspi", |
| 221 | "lvs", "pmc"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 222 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 223 | }; |
| 224 | conf_lc { |
| 225 | nvidia,pins = "lc", "ls"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 226 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 227 | }; |
| 228 | conf_lcsn { |
| 229 | nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", |
| 230 | "lm0", "lm1", "lpp", "lpw0", "lpw1", |
| 231 | "lpw2", "lsc1", "lsck", "lsda", "lsdi", |
| 232 | "lvp0", "lvp1", "sdb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 233 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 234 | }; |
| 235 | conf_ld17_0 { |
| 236 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 237 | "ld23_22"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame^] | 238 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 239 | }; |
| 240 | }; |
| 241 | }; |
| 242 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 243 | i2s@70002800 { |
| 244 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | serial@70006000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 248 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 249 | }; |
| 250 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 251 | serial@70006200 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 252 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 253 | }; |
| 254 | |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 255 | i2c@7000c000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 256 | status = "okay"; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 257 | clock-frequency = <400000>; |
Leon Romanovsky | 613e965 | 2012-02-02 22:13:35 +0200 | [diff] [blame] | 258 | |
| 259 | alc5632: alc5632@1e { |
| 260 | compatible = "realtek,alc5632"; |
| 261 | reg = <0x1e>; |
| 262 | gpio-controller; |
| 263 | #gpio-cells = <2>; |
| 264 | }; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 265 | }; |
| 266 | |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 267 | hdmi_ddc: i2c@7000c400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 268 | status = "okay"; |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 269 | clock-frequency = <100000>; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 270 | }; |
| 271 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 272 | nvec@7000c500 { |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 273 | compatible = "nvidia,nvec"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 274 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 275 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 276 | #address-cells = <1>; |
| 277 | #size-cells = <0>; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 278 | clock-frequency = <80000>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 279 | request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 280 | slave-addr = <138>; |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 281 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
| 282 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | d409b3a | 2013-01-11 13:31:23 +0530 | [diff] [blame] | 283 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 284 | resets = <&tegra_car 67>; |
| 285 | reset-names = "i2c"; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 286 | }; |
| 287 | |
| 288 | i2c@7000d000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 289 | status = "okay"; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 290 | clock-frequency = <400000>; |
Marc Dietrich | 1266f89 | 2012-01-31 19:53:21 +0100 | [diff] [blame] | 291 | |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 292 | pmic: tps6586x@34 { |
| 293 | compatible = "ti,tps6586x"; |
| 294 | reg = <0x34>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 295 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 296 | |
| 297 | #gpio-cells = <2>; |
| 298 | gpio-controller; |
| 299 | |
| 300 | sys-supply = <&p5valw_reg>; |
| 301 | vin-sm0-supply = <&sys_reg>; |
| 302 | vin-sm1-supply = <&sys_reg>; |
| 303 | vin-sm2-supply = <&sys_reg>; |
| 304 | vinldo01-supply = <&sm2_reg>; |
| 305 | vinldo23-supply = <&sm2_reg>; |
| 306 | vinldo4-supply = <&sm2_reg>; |
| 307 | vinldo678-supply = <&sm2_reg>; |
| 308 | vinldo9-supply = <&sm2_reg>; |
| 309 | |
| 310 | regulators { |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 311 | sys_reg: sys { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 312 | regulator-name = "vdd_sys"; |
| 313 | regulator-always-on; |
| 314 | }; |
| 315 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 316 | sm0 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 317 | regulator-name = "+1.2vs_sm0,vdd_core"; |
| 318 | regulator-min-microvolt = <1200000>; |
| 319 | regulator-max-microvolt = <1200000>; |
| 320 | regulator-always-on; |
| 321 | }; |
| 322 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 323 | sm1 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 324 | regulator-name = "+1.0vs_sm1,vdd_cpu"; |
| 325 | regulator-min-microvolt = <1000000>; |
| 326 | regulator-max-microvolt = <1000000>; |
| 327 | regulator-always-on; |
| 328 | }; |
| 329 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 330 | sm2_reg: sm2 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 331 | regulator-name = "+3.7vs_sm2,vin_ldo*"; |
| 332 | regulator-min-microvolt = <3700000>; |
| 333 | regulator-max-microvolt = <3700000>; |
| 334 | regulator-always-on; |
| 335 | }; |
| 336 | |
| 337 | /* LDO0 is not connected to anything */ |
| 338 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 339 | ldo1 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 340 | regulator-name = "+1.1vs_ldo1,avdd_pll*"; |
| 341 | regulator-min-microvolt = <1100000>; |
| 342 | regulator-max-microvolt = <1100000>; |
| 343 | regulator-always-on; |
| 344 | }; |
| 345 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 346 | ldo2 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 347 | regulator-name = "+1.2vs_ldo2,vdd_rtc"; |
| 348 | regulator-min-microvolt = <1200000>; |
| 349 | regulator-max-microvolt = <1200000>; |
| 350 | }; |
| 351 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 352 | ldo3 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 353 | regulator-name = "+3.3vs_ldo3,avdd_usb*"; |
| 354 | regulator-min-microvolt = <3300000>; |
| 355 | regulator-max-microvolt = <3300000>; |
| 356 | regulator-always-on; |
| 357 | }; |
| 358 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 359 | ldo4 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 360 | regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; |
| 361 | regulator-min-microvolt = <1800000>; |
| 362 | regulator-max-microvolt = <1800000>; |
| 363 | regulator-always-on; |
| 364 | }; |
| 365 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 366 | ldo5 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 367 | regulator-name = "+2.85vs_ldo5,vcore_mmc"; |
| 368 | regulator-min-microvolt = <2850000>; |
| 369 | regulator-max-microvolt = <2850000>; |
| 370 | regulator-always-on; |
| 371 | }; |
| 372 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 373 | ldo6 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 374 | /* |
| 375 | * Research indicates this should be |
| 376 | * 1.8v; other boards that use this |
| 377 | * rail for the same purpose need it |
| 378 | * set to 1.8v. The schematic signal |
| 379 | * name is incorrect; perhaps copied |
| 380 | * from an incorrect NVIDIA reference. |
| 381 | */ |
| 382 | regulator-name = "+2.85vs_ldo6,avdd_vdac"; |
| 383 | regulator-min-microvolt = <1800000>; |
| 384 | regulator-max-microvolt = <1800000>; |
| 385 | }; |
| 386 | |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 387 | hdmi_vdd_reg: ldo7 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 388 | regulator-name = "+3.3vs_ldo7,avdd_hdmi"; |
| 389 | regulator-min-microvolt = <3300000>; |
| 390 | regulator-max-microvolt = <3300000>; |
| 391 | }; |
| 392 | |
Stephen Warren | 11a3c86 | 2013-01-02 14:53:22 -0700 | [diff] [blame] | 393 | hdmi_pll_reg: ldo8 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 394 | regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; |
| 395 | regulator-min-microvolt = <1800000>; |
| 396 | regulator-max-microvolt = <1800000>; |
| 397 | }; |
| 398 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 399 | ldo9 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 400 | regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; |
| 401 | regulator-min-microvolt = <2850000>; |
| 402 | regulator-max-microvolt = <2850000>; |
| 403 | regulator-always-on; |
| 404 | }; |
| 405 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 406 | ldo_rtc { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 407 | regulator-name = "+3.3vs_rtc"; |
| 408 | regulator-min-microvolt = <3300000>; |
| 409 | regulator-max-microvolt = <3300000>; |
| 410 | regulator-always-on; |
| 411 | }; |
| 412 | }; |
| 413 | }; |
| 414 | |
Marc Dietrich | 1266f89 | 2012-01-31 19:53:21 +0100 | [diff] [blame] | 415 | adt7461@4c { |
| 416 | compatible = "adi,adt7461"; |
| 417 | reg = <0x4c>; |
| 418 | }; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 419 | }; |
| 420 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 421 | pmc@7000e400 { |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 422 | nvidia,invert-interrupt; |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 423 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 424 | nvidia,cpu-pwr-good-time = <2000>; |
| 425 | nvidia,cpu-pwr-off-time = <0>; |
| 426 | nvidia,core-pwr-good-time = <3845 3845>; |
| 427 | nvidia,core-pwr-off-time = <0>; |
| 428 | nvidia,sys-clock-req-active-high; |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 429 | }; |
| 430 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 431 | usb@c5000000 { |
| 432 | status = "okay"; |
| 433 | }; |
| 434 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 435 | usb-phy@c5000000 { |
| 436 | status = "okay"; |
| 437 | }; |
| 438 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 439 | usb@c5004000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 440 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 441 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 442 | GPIO_ACTIVE_LOW>; |
Venu Byravarasu | 9dffe3b | 2013-05-16 19:42:56 +0530 | [diff] [blame] | 443 | }; |
| 444 | |
| 445 | usb-phy@c5004000 { |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 446 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 447 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 448 | GPIO_ACTIVE_LOW>; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 449 | }; |
| 450 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 451 | usb@c5008000 { |
| 452 | status = "okay"; |
| 453 | }; |
| 454 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 455 | usb-phy@c5008000 { |
| 456 | status = "okay"; |
| 457 | }; |
| 458 | |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 459 | sdhci@c8000000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 460 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 461 | cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; |
| 462 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 463 | power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 464 | bus-width = <4>; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 465 | }; |
| 466 | |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 467 | sdhci@c8000600 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 468 | status = "okay"; |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 469 | bus-width = <8>; |
Joseph Lo | 7a2617a | 2013-04-03 14:34:39 -0600 | [diff] [blame] | 470 | non-removable; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 471 | }; |
Marc Dietrich | d8d56c8 | 2012-01-28 20:03:07 +0100 | [diff] [blame] | 472 | |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 473 | clocks { |
| 474 | compatible = "simple-bus"; |
| 475 | #address-cells = <1>; |
| 476 | #size-cells = <0>; |
| 477 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 478 | clk32k_in: clock@0 { |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 479 | compatible = "fixed-clock"; |
| 480 | reg=<0>; |
| 481 | #clock-cells = <0>; |
| 482 | clock-frequency = <32768>; |
| 483 | }; |
| 484 | }; |
| 485 | |
Marc Dietrich | d8d56c8 | 2012-01-28 20:03:07 +0100 | [diff] [blame] | 486 | gpio-keys { |
| 487 | compatible = "gpio-keys"; |
| 488 | |
| 489 | power { |
| 490 | label = "Power"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 491 | gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 492 | linux,code = <KEY_POWER>; |
Marc Dietrich | d8d56c8 | 2012-01-28 20:03:07 +0100 | [diff] [blame] | 493 | gpio-key,wakeup; |
| 494 | }; |
| 495 | }; |
Marc Dietrich | 80c9473 | 2012-01-28 20:03:08 +0100 | [diff] [blame] | 496 | |
| 497 | gpio-leds { |
| 498 | compatible = "gpio-leds"; |
| 499 | |
| 500 | wifi { |
| 501 | label = "wifi-led"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 502 | gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
Marc Dietrich | 80c9473 | 2012-01-28 20:03:08 +0100 | [diff] [blame] | 503 | linux,default-trigger = "rfkill0"; |
| 504 | }; |
| 505 | }; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 506 | |
Stephen Warren | 217b8f0 | 2012-06-21 14:24:57 -0600 | [diff] [blame] | 507 | regulators { |
| 508 | compatible = "simple-bus"; |
| 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
| 511 | |
| 512 | p5valw_reg: regulator@0 { |
| 513 | compatible = "regulator-fixed"; |
| 514 | reg = <0>; |
| 515 | regulator-name = "+5valw"; |
| 516 | regulator-min-microvolt = <5000000>; |
| 517 | regulator-max-microvolt = <5000000>; |
| 518 | regulator-always-on; |
| 519 | }; |
| 520 | }; |
| 521 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 522 | sound { |
| 523 | compatible = "nvidia,tegra-audio-alc5632-paz00", |
| 524 | "nvidia,tegra-audio-alc5632"; |
| 525 | |
| 526 | nvidia,model = "Compal PAZ00"; |
| 527 | |
| 528 | nvidia,audio-routing = |
| 529 | "Int Spk", "SPKOUT", |
| 530 | "Int Spk", "SPKOUTN", |
| 531 | "Headset Mic", "MICBIAS1", |
| 532 | "MIC1", "Headset Mic", |
| 533 | "Headset Stereophone", "HPR", |
| 534 | "Headset Stereophone", "HPL", |
| 535 | "DMICDAT", "Digital Mic"; |
| 536 | |
| 537 | nvidia,audio-codec = <&alc5632>; |
| 538 | nvidia,i2s-controller = <&tegra_i2s1>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 539 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| 540 | GPIO_ACTIVE_HIGH>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 541 | |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 542 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 543 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 544 | <&tegra_car TEGRA20_CLK_CDEV1>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 545 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 546 | }; |
Marc Dietrich | cc2afa4 | 2011-11-01 10:37:05 +0000 | [diff] [blame] | 547 | }; |