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Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030021#include <linux/irqchip/chained_irq.h>
Thomas Petazzonid7df84b2014-04-14 15:54:02 +020022#include <linux/cpu.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020023#include <linux/io.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020026#include <linux/of_pci.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020027#include <linux/irqdomain.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020028#include <linux/slab.h>
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +010029#include <linux/syscore_ops.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020030#include <linux/msi.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020031#include <asm/mach/arch.h>
32#include <asm/exception.h>
Gregory CLEMENT344e8732012-08-02 11:19:12 +030033#include <asm/smp_plat.h>
Thomas Petazzoni9339d432013-04-09 23:26:15 +020034#include <asm/mach/irq.h>
35
36#include "irqchip.h"
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020037
38/* Interrupt Controller Registers Map */
39#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
40#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
41
Ben Dooksf3e16cc2012-06-04 18:50:12 +020042#define ARMADA_370_XP_INT_CONTROL (0x00)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020043#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
44#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010045#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +000046#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +020047#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020048
49#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030050#define ARMADA_375_PPI_CAUSE (0x10)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020051
Gregory CLEMENT344e8732012-08-02 11:19:12 +030052#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
53#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
54#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
55
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010056#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
57
Gregory CLEMENT7f23f622013-03-20 16:09:35 +010058#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
59
Thomas Petazzoni5ec69012013-04-09 23:26:17 +020060#define IPI_DOORBELL_START (0)
61#define IPI_DOORBELL_END (8)
62#define IPI_DOORBELL_MASK 0xFF
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020063#define PCI_MSI_DOORBELL_START (16)
64#define PCI_MSI_DOORBELL_NR (16)
65#define PCI_MSI_DOORBELL_END (32)
66#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
Gregory CLEMENT344e8732012-08-02 11:19:12 +030067
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020068static void __iomem *per_cpu_int_base;
69static void __iomem *main_int_base;
70static struct irq_domain *armada_370_xp_mpic_domain;
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +010071static u32 doorbell_mask_reg;
Maxime Ripard5724be82015-03-03 11:27:23 +010072static int parent_irq;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020073#ifdef CONFIG_PCI_MSI
74static struct irq_domain *armada_370_xp_msi_domain;
75static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
76static DEFINE_MUTEX(msi_used_lock);
77static phys_addr_t msi_doorbell_addr;
78#endif
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020079
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010080static inline bool is_percpu_irq(irq_hw_number_t irq)
81{
82 switch (irq) {
83 case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
84 return true;
85 default:
86 return false;
87 }
88}
89
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010090/*
91 * In SMP mode:
92 * For shared global interrupts, mask/unmask global enable bit
Marek Belisko097ef182013-03-15 23:34:04 +010093 * For CPU interrupts, mask/unmask the calling CPU's bit
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010094 */
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020095static void armada_370_xp_irq_mask(struct irq_data *d)
96{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010097 irq_hw_number_t hwirq = irqd_to_hwirq(d);
98
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010099 if (!is_percpu_irq(hwirq))
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100100 writel(hwirq, main_int_base +
101 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
102 else
103 writel(hwirq, per_cpu_int_base +
104 ARMADA_370_XP_INT_SET_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200105}
106
107static void armada_370_xp_irq_unmask(struct irq_data *d)
108{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100109 irq_hw_number_t hwirq = irqd_to_hwirq(d);
110
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100111 if (!is_percpu_irq(hwirq))
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100112 writel(hwirq, main_int_base +
113 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
114 else
115 writel(hwirq, per_cpu_int_base +
116 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200117}
118
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200119#ifdef CONFIG_PCI_MSI
120
121static int armada_370_xp_alloc_msi(void)
122{
123 int hwirq;
124
125 mutex_lock(&msi_used_lock);
126 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
127 if (hwirq >= PCI_MSI_DOORBELL_NR)
128 hwirq = -ENOSPC;
129 else
130 set_bit(hwirq, msi_used);
131 mutex_unlock(&msi_used_lock);
132
133 return hwirq;
134}
135
136static void armada_370_xp_free_msi(int hwirq)
137{
138 mutex_lock(&msi_used_lock);
139 if (!test_bit(hwirq, msi_used))
140 pr_err("trying to free unused MSI#%d\n", hwirq);
141 else
142 clear_bit(hwirq, msi_used);
143 mutex_unlock(&msi_used_lock);
144}
145
Yijing Wangc2791b82014-11-11 17:45:45 -0700146static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200147 struct pci_dev *pdev,
148 struct msi_desc *desc)
149{
150 struct msi_msg msg;
Thomas Petazzonida343fc2014-04-18 14:19:47 +0200151 int virq, hwirq;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200152
Alexander Gordeev39301152014-09-07 20:57:54 +0200153 /* We support MSI, but not MSI-X */
154 if (desc->msi_attrib.is_msix)
155 return -EINVAL;
156
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200157 hwirq = armada_370_xp_alloc_msi();
158 if (hwirq < 0)
159 return hwirq;
160
161 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
162 if (!virq) {
163 armada_370_xp_free_msi(hwirq);
164 return -EINVAL;
165 }
166
167 irq_set_msi_desc(virq, desc);
168
169 msg.address_lo = msi_doorbell_addr;
170 msg.address_hi = 0;
171 msg.data = 0xf00 | (hwirq + 16);
172
Jiang Liu83a18912014-11-09 23:10:34 +0800173 pci_write_msi_msg(virq, &msg);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200174 return 0;
175}
176
Yijing Wangc2791b82014-11-11 17:45:45 -0700177static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200178 unsigned int irq)
179{
180 struct irq_data *d = irq_get_irq_data(irq);
Neil Greatorexff3c6642014-04-18 14:19:49 +0200181 unsigned long hwirq = d->hwirq;
182
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200183 irq_dispose_mapping(irq);
Neil Greatorexff3c6642014-04-18 14:19:49 +0200184 armada_370_xp_free_msi(hwirq);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200185}
186
187static struct irq_chip armada_370_xp_msi_irq_chip = {
188 .name = "armada_370_xp_msi_irq",
Thomas Gleixner280510f2014-11-23 12:23:20 +0100189 .irq_enable = pci_msi_unmask_irq,
190 .irq_disable = pci_msi_mask_irq,
191 .irq_mask = pci_msi_mask_irq,
192 .irq_unmask = pci_msi_unmask_irq,
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200193};
194
195static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
196 irq_hw_number_t hw)
197{
198 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
199 handle_simple_irq);
200 set_irq_flags(virq, IRQF_VALID);
201
202 return 0;
203}
204
205static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
206 .map = armada_370_xp_msi_map,
207};
208
209static int armada_370_xp_msi_init(struct device_node *node,
210 phys_addr_t main_int_phys_base)
211{
Yijing Wangc2791b82014-11-11 17:45:45 -0700212 struct msi_controller *msi_chip;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200213 u32 reg;
214 int ret;
215
216 msi_doorbell_addr = main_int_phys_base +
217 ARMADA_370_XP_SW_TRIG_INT_OFFS;
218
219 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
220 if (!msi_chip)
221 return -ENOMEM;
222
223 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
224 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
225 msi_chip->of_node = node;
226
227 armada_370_xp_msi_domain =
228 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
229 &armada_370_xp_msi_irq_ops,
230 NULL);
231 if (!armada_370_xp_msi_domain) {
232 kfree(msi_chip);
233 return -ENOMEM;
234 }
235
236 ret = of_pci_msi_chip_add(msi_chip);
237 if (ret < 0) {
238 irq_domain_remove(armada_370_xp_msi_domain);
239 kfree(msi_chip);
240 return ret;
241 }
242
243 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
244 | PCI_MSI_DOORBELL_MASK;
245
246 writel(reg, per_cpu_int_base +
247 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
248
249 /* Unmask IPI interrupt */
250 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
251
252 return 0;
253}
254#else
255static inline int armada_370_xp_msi_init(struct device_node *node,
256 phys_addr_t main_int_phys_base)
257{
258 return 0;
259}
260#endif
261
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300262#ifdef CONFIG_SMP
Arnaud Ebalard19e61d42014-01-20 22:52:05 +0100263static DEFINE_RAW_SPINLOCK(irq_controller_lock);
264
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300265static int armada_xp_set_affinity(struct irq_data *d,
266 const struct cpumask *mask_val, bool force)
267{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100268 irq_hw_number_t hwirq = irqd_to_hwirq(d);
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000269 unsigned long reg, mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100270 int cpu;
271
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000272 /* Select a single core from the affinity mask which is online */
273 cpu = cpumask_any_and(mask_val, cpu_online_mask);
274 mask = 1UL << cpu_logical_map(cpu);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100275
276 raw_spin_lock(&irq_controller_lock);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100277 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000278 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100279 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100280 raw_spin_unlock(&irq_controller_lock);
281
Thomas Petazzoni1dacf192014-10-24 13:59:16 +0200282 return IRQ_SET_MASK_OK;
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300283}
284#endif
285
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200286static struct irq_chip armada_370_xp_irq_chip = {
287 .name = "armada_370_xp_irq",
288 .irq_mask = armada_370_xp_irq_mask,
289 .irq_mask_ack = armada_370_xp_irq_mask,
290 .irq_unmask = armada_370_xp_irq_unmask,
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300291#ifdef CONFIG_SMP
292 .irq_set_affinity = armada_xp_set_affinity,
293#endif
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200294};
295
296static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
297 unsigned int virq, irq_hw_number_t hw)
298{
299 armada_370_xp_irq_mask(irq_get_irq_data(virq));
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100300 if (!is_percpu_irq(hw))
Gregory CLEMENT600468d2013-04-05 14:32:52 +0200301 writel(hw, per_cpu_int_base +
302 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
303 else
304 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200305 irq_set_status_flags(virq, IRQ_LEVEL);
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100306
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100307 if (is_percpu_irq(hw)) {
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100308 irq_set_percpu_devid(virq);
309 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
310 handle_percpu_devid_irq);
311
312 } else {
313 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
314 handle_level_irq);
315 }
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200316 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
317
318 return 0;
319}
320
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200321static void armada_xp_mpic_smp_cpu_init(void)
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300322{
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200323 u32 control;
324 int nr_irqs, i;
325
326 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
327 nr_irqs = (control >> 2) & 0x3ff;
328
329 for (i = 0; i < nr_irqs; i++)
330 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
331
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300332 /* Clear pending IPIs */
333 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
334
335 /* Enable first 8 IPIs */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200336 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300337 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
338
339 /* Unmask IPI interrupt */
340 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
341}
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200342
Ezequiel Garcia933a24b2015-03-03 11:43:14 +0100343#ifdef CONFIG_SMP
344static void armada_mpic_send_doorbell(const struct cpumask *mask,
345 unsigned int irq)
346{
347 int cpu;
348 unsigned long map = 0;
349
350 /* Convert our logical CPU mask into a physical one. */
351 for_each_cpu(cpu, mask)
352 map |= 1 << cpu_logical_map(cpu);
353
354 /*
355 * Ensure that stores to Normal memory are visible to the
356 * other CPUs before issuing the IPI.
357 */
358 dsb();
359
360 /* submit softirq */
361 writel((map << 8) | irq, main_int_base +
362 ARMADA_370_XP_SW_TRIG_INT_OFFS);
363}
364
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200365static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
366 unsigned long action, void *hcpu)
367{
368 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
369 armada_xp_mpic_smp_cpu_init();
Maxime Ripard5724be82015-03-03 11:27:23 +0100370
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200371 return NOTIFY_OK;
372}
373
374static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
375 .notifier_call = armada_xp_mpic_secondary_init,
376 .priority = 100,
377};
378
Maxime Ripard5724be82015-03-03 11:27:23 +0100379static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
380 unsigned long action, void *hcpu)
381{
382 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
383 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
384
385 return NOTIFY_OK;
386}
387
388static struct notifier_block mpic_cascaded_cpu_notifier = {
389 .notifier_call = mpic_cascaded_secondary_init,
390 .priority = 100,
391};
392
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300393#endif /* CONFIG_SMP */
394
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200395static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
396 .map = armada_370_xp_mpic_irq_map,
397 .xlate = irq_domain_xlate_onecell,
398};
399
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300400#ifdef CONFIG_PCI_MSI
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300401static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300402{
403 u32 msimask, msinr;
404
405 msimask = readl_relaxed(per_cpu_int_base +
406 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
407 & PCI_MSI_DOORBELL_MASK;
408
409 writel(~msimask, per_cpu_int_base +
410 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
411
412 for (msinr = PCI_MSI_DOORBELL_START;
413 msinr < PCI_MSI_DOORBELL_END; msinr++) {
414 int irq;
415
416 if (!(msimask & BIT(msinr)))
417 continue;
418
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100419 if (is_chained) {
420 irq = irq_find_mapping(armada_370_xp_msi_domain,
421 msinr - 16);
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300422 generic_handle_irq(irq);
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100423 } else {
424 irq = msinr - 16;
425 handle_domain_irq(armada_370_xp_msi_domain,
426 irq, regs);
427 }
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300428 }
429}
430#else
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300431static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300432#endif
433
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300434static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
435 struct irq_desc *desc)
436{
437 struct irq_chip *chip = irq_get_chip(irq);
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200438 unsigned long irqmap, irqn, irqsrc, cpuid;
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300439 unsigned int cascade_irq;
440
441 chained_irq_enter(chip, desc);
442
443 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200444 cpuid = cpu_logical_map(smp_processor_id());
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300445
446 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200447 irqsrc = readl_relaxed(main_int_base +
448 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
449
450 /* Check if the interrupt is not masked on current CPU.
451 * Test IRQ (0-1) and FIQ (8-9) mask bits.
452 */
453 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
454 continue;
455
456 if (irqn == 1) {
457 armada_370_xp_handle_msi_irq(NULL, true);
458 continue;
459 }
460
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300461 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
462 generic_handle_irq(cascade_irq);
463 }
464
465 chained_irq_exit(chip, desc);
466}
467
Stephen Boyd8783dd32014-03-04 16:40:30 -0800468static void __exception_irq_entry
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200469armada_370_xp_handle_irq(struct pt_regs *regs)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200470{
471 u32 irqstat, irqnr;
472
473 do {
474 irqstat = readl_relaxed(per_cpu_int_base +
475 ARMADA_370_XP_CPU_INTACK_OFFS);
476 irqnr = irqstat & 0x3FF;
477
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300478 if (irqnr > 1022)
479 break;
480
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200481 if (irqnr > 1) {
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100482 handle_domain_irq(armada_370_xp_mpic_domain,
483 irqnr, regs);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200484 continue;
485 }
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200486
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200487 /* MSI handling */
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300488 if (irqnr == 1)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300489 armada_370_xp_handle_msi_irq(regs, false);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200490
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300491#ifdef CONFIG_SMP
492 /* IPI Handling */
493 if (irqnr == 0) {
494 u32 ipimask, ipinr;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200495
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300496 ipimask = readl_relaxed(per_cpu_int_base +
497 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200498 & IPI_DOORBELL_MASK;
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300499
Lior Amsalema6f089e2013-11-25 17:26:44 +0100500 writel(~ipimask, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300501 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
502
503 /* Handle all pending doorbells */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200504 for (ipinr = IPI_DOORBELL_START;
505 ipinr < IPI_DOORBELL_END; ipinr++) {
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300506 if (ipimask & (0x1 << ipinr))
507 handle_IPI(ipinr, regs);
508 }
509 continue;
510 }
511#endif
512
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200513 } while (1);
514}
515
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100516static int armada_370_xp_mpic_suspend(void)
517{
518 doorbell_mask_reg = readl(per_cpu_int_base +
519 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
520 return 0;
521}
522
523static void armada_370_xp_mpic_resume(void)
524{
525 int nirqs;
526 irq_hw_number_t irq;
527
528 /* Re-enable interrupts */
529 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
530 for (irq = 0; irq < nirqs; irq++) {
531 struct irq_data *data;
532 int virq;
533
534 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
535 if (virq == 0)
536 continue;
537
538 if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
539 writel(irq, per_cpu_int_base +
540 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
541 else
542 writel(irq, main_int_base +
543 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
544
545 data = irq_get_irq_data(virq);
546 if (!irqd_irq_disabled(data))
547 armada_370_xp_irq_unmask(data);
548 }
549
550 /* Reconfigure doorbells for IPIs and MSIs */
551 writel(doorbell_mask_reg,
552 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
553 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
554 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
555 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
556 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
557}
558
559struct syscore_ops armada_370_xp_mpic_syscore_ops = {
560 .suspend = armada_370_xp_mpic_suspend,
561 .resume = armada_370_xp_mpic_resume,
562};
563
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200564static int __init armada_370_xp_mpic_of_init(struct device_node *node,
565 struct device_node *parent)
566{
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200567 struct resource main_int_res, per_cpu_int_res;
Maxime Ripard5724be82015-03-03 11:27:23 +0100568 int nr_irqs, i;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200569 u32 control;
570
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200571 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
572 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200573
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200574 BUG_ON(!request_mem_region(main_int_res.start,
575 resource_size(&main_int_res),
576 node->full_name));
577 BUG_ON(!request_mem_region(per_cpu_int_res.start,
578 resource_size(&per_cpu_int_res),
579 node->full_name));
580
581 main_int_base = ioremap(main_int_res.start,
582 resource_size(&main_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200583 BUG_ON(!main_int_base);
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200584
585 per_cpu_int_base = ioremap(per_cpu_int_res.start,
586 resource_size(&per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200587 BUG_ON(!per_cpu_int_base);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200588
589 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200590 nr_irqs = (control >> 2) & 0x3ff;
591
592 for (i = 0; i < nr_irqs; i++)
593 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200594
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200595 armada_370_xp_mpic_domain =
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200596 irq_domain_add_linear(node, nr_irqs,
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200597 &armada_370_xp_mpic_irq_ops, NULL);
598
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200599 BUG_ON(!armada_370_xp_mpic_domain);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200600
Ezequiel Garcia933a24b2015-03-03 11:43:14 +0100601 /* Setup for the boot CPU */
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200602 armada_xp_mpic_smp_cpu_init();
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200603
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200604 armada_370_xp_msi_init(node, main_int_res.start);
605
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300606 parent_irq = irq_of_parse_and_map(node, 0);
607 if (parent_irq <= 0) {
608 irq_set_default_host(armada_370_xp_mpic_domain);
609 set_handle_irq(armada_370_xp_handle_irq);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200610#ifdef CONFIG_SMP
611 set_smp_cross_call(armada_mpic_send_doorbell);
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200612 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200613#endif
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300614 } else {
Maxime Ripard5724be82015-03-03 11:27:23 +0100615#ifdef CONFIG_SMP
616 register_cpu_notifier(&mpic_cascaded_cpu_notifier);
617#endif
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300618 irq_set_chained_handler(parent_irq,
619 armada_370_xp_mpic_handle_cascade_irq);
620 }
Thomas Petazzonib313ada2013-04-09 23:26:16 +0200621
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100622 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
623
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200624 return 0;
625}
626
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200627IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);