Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 9ae6f740b49f933eeff972a79fd2a8b7e4592cf5 / . / arch / arm / mach-mvebu / irq-armada-370-xp.c
blob: 645a8d3698eb06b68825b34de3922aa5a466a99f [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame^]1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/irqdomain.h>
25#include <asm/mach/arch.h>
26#include <asm/exception.h>
27
28/* Interrupt Controller Registers Map */
29#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
30#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
31
32#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
33#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
34
35#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
36
37#define ARMADA_370_XP_NR_IRQS (115)
38
39static void __iomem *per_cpu_int_base;
40static void __iomem *main_int_base;
41static struct irq_domain *armada_370_xp_mpic_domain;
42
43static void armada_370_xp_irq_mask(struct irq_data *d)
44{
45 writel(irqd_to_hwirq(d),
46 per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
47}
48
49static void armada_370_xp_irq_unmask(struct irq_data *d)
50{
51 writel(irqd_to_hwirq(d),
52 per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
53}
54
55static struct irq_chip armada_370_xp_irq_chip = {
56 .name = "armada_370_xp_irq",
57 .irq_mask = armada_370_xp_irq_mask,
58 .irq_mask_ack = armada_370_xp_irq_mask,
59 .irq_unmask = armada_370_xp_irq_unmask,
60};
61
62static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
63 unsigned int virq, irq_hw_number_t hw)
64{
65 armada_370_xp_irq_mask(irq_get_irq_data(virq));
66 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
67
68 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
69 handle_level_irq);
70 irq_set_status_flags(virq, IRQ_LEVEL);
71 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
72
73 return 0;
74}
75
76static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
77 .map = armada_370_xp_mpic_irq_map,
78 .xlate = irq_domain_xlate_onecell,
79};
80
81static int __init armada_370_xp_mpic_of_init(struct device_node *node,
82 struct device_node *parent)
83{
84 main_int_base = of_iomap(node, 0);
85 per_cpu_int_base = of_iomap(node, 1);
86
87 BUG_ON(!main_int_base);
88 BUG_ON(!per_cpu_int_base);
89
90 armada_370_xp_mpic_domain =
91 irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
92 &armada_370_xp_mpic_irq_ops, NULL);
93
94 if (!armada_370_xp_mpic_domain)
95 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
96
97 irq_set_default_host(armada_370_xp_mpic_domain);
98 return 0;
99}
100
101asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
102 *regs)
103{
104 u32 irqstat, irqnr;
105
106 do {
107 irqstat = readl_relaxed(per_cpu_int_base +
108 ARMADA_370_XP_CPU_INTACK_OFFS);
109 irqnr = irqstat & 0x3FF;
110
111 if (irqnr < 1023) {
112 irqnr =
113 irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
114 handle_IRQ(irqnr, regs);
115 continue;
116 }
117
118 break;
119 } while (1);
120}
121
122static const struct of_device_id mpic_of_match[] __initconst = {
123 {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
124 {},
125};
126
127void __init armada_370_xp_init_irq(void)
128{
129 of_irq_init(mpic_of_match);
130}