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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2874c5fd284268364ece81a7bd936f3c8168e567 / . / drivers / net / dsa / mv88e6xxx / global1.h
blob: 7bd5ab733a3f7ab9a4a176a75fae0cf8a98dbde6 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]2/*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
Vivien Didelot4333d612017-03-28 15:10:36 -0400[diff] [blame]7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]9 */
10
11#ifndef _MV88E6XXX_GLOBAL1_H
12#define _MV88E6XXX_GLOBAL1_H
13
Vivien Didelot4d5f2ba72017-06-02 17:06:15 -0400[diff] [blame]14#include "chip.h"
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]15
Vivien Didelot82466922017-06-15 12:13:59 -0400[diff] [blame]16/* Offset 0x00: Switch Global Status Register */
17#define MV88E6XXX_G1_STS 0x00
18#define MV88E6352_G1_STS_PPU_STATE 0x8000
19#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24#define MV88E6XXX_G1_STS_INIT_READY 0x0800
25#define MV88E6XXX_G1_STS_IRQ_AVB 8
26#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
27#define MV88E6XXX_G1_STS_IRQ_STATS 6
Andrew Lunn62eb1162018-01-14 02:32:45 +0100[diff] [blame]28#define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5
Vivien Didelot82466922017-06-15 12:13:59 -0400[diff] [blame]29#define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
Andrew Lunn09776442018-01-14 02:32:44 +0100[diff] [blame]30#define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3
Vivien Didelot82466922017-06-15 12:13:59 -0400[diff] [blame]31#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
32#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
33#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
34
Vivien Didelot4b0c4812017-06-15 12:14:00 -0400[diff] [blame]35/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
36 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
37 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
38 */
39#define MV88E6XXX_G1_MAC_01 0x01
40#define MV88E6XXX_G1_MAC_23 0x02
41#define MV88E6XXX_G1_MAC_45 0x03
42
Vivien Didelot27c0e602017-06-15 12:14:01 -0400[diff] [blame]43/* Offset 0x01: ATU FID Register */
44#define MV88E6352_G1_ATU_FID 0x01
45
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -0400[diff] [blame]46/* Offset 0x02: VTU FID Register */
47#define MV88E6352_G1_VTU_FID 0x02
48#define MV88E6352_G1_VTU_FID_MASK 0x0fff
49
50/* Offset 0x03: VTU SID Register */
51#define MV88E6352_G1_VTU_SID 0x03
52#define MV88E6352_G1_VTU_SID_MASK 0x3f
53
Vivien Didelotd77f4322017-06-15 12:14:03 -0400[diff] [blame]54/* Offset 0x04: Switch Global Control Register */
55#define MV88E6XXX_G1_CTL1 0x04
56#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
57#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
58#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
59#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
60#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
61#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
62#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
63#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
64#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
65#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
66#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
67#define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
68#define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
69#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -0400[diff] [blame]70
71/* Offset 0x05: VTU Operation Register */
72#define MV88E6XXX_G1_VTU_OP 0x05
73#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
74#define MV88E6XXX_G1_VTU_OP_MASK 0x7000
75#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
76#define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
77#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
78#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
79#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
80#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
Andrew Lunn62eb1162018-01-14 02:32:45 +0100[diff] [blame]81#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
82#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)
83#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)
84#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
Vivien Didelot7ec60d6e2017-06-15 12:14:02 -0400[diff] [blame]85
86/* Offset 0x06: VTU VID Register */
87#define MV88E6XXX_G1_VTU_VID 0x06
88#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
89#define MV88E6390_G1_VTU_VID_PAGE 0x2000
90#define MV88E6XXX_G1_VTU_VID_VALID 0x1000
91
92/* Offset 0x07: VTU/STU Data Register 1
93 * Offset 0x08: VTU/STU Data Register 2
94 * Offset 0x09: VTU/STU Data Register 3
95 */
96#define MV88E6XXX_G1_VTU_DATA1 0x07
97#define MV88E6XXX_G1_VTU_DATA2 0x08
98#define MV88E6XXX_G1_VTU_DATA3 0x09
99#define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
100#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
101#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
102#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
103#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
104#define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
105#define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
106#define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
107#define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
Vivien Didelot27c0e602017-06-15 12:14:01 -0400[diff] [blame]108
109/* Offset 0x0A: ATU Control Register */
110#define MV88E6XXX_G1_ATU_CTL 0x0a
111#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
112
113/* Offset 0x0B: ATU Operation Register */
114#define MV88E6XXX_G1_ATU_OP 0x0b
115#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
116#define MV88E6XXX_G1_ATU_OP_MASK 0x7000
117#define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
118#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
119#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
120#define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
121#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
122#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
123#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
124#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
Andrew Lunn09776442018-01-14 02:32:44 +0100[diff] [blame]125#define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7)
126#define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6)
Andrew Lunnddca24d2018-09-14 23:46:12 +0200[diff] [blame]127#define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5)
Andrew Lunn09776442018-01-14 02:32:44 +0100[diff] [blame]128#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4)
Vivien Didelot27c0e602017-06-15 12:14:01 -0400[diff] [blame]129
130/* Offset 0x0C: ATU Data Register */
131#define MV88E6XXX_G1_ATU_DATA 0x0c
132#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
133#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
134#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
135#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
136#define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000
137#define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d
138#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
139#define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER 0x000f
140#define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE 0x0005
141#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
142#define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT 0x000e
143#define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER 0x000f
144
145/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
146 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
147 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
148 */
149#define MV88E6XXX_G1_ATU_MAC01 0x0d
150#define MV88E6XXX_G1_ATU_MAC23 0x0e
151#define MV88E6XXX_G1_ATU_MAC45 0x0f
152
Vivien Didelotccba8f32017-06-15 12:14:06 -0400[diff] [blame]153/* Offset 0x10: IP-PRI Mapping Register 0
154 * Offset 0x11: IP-PRI Mapping Register 1
155 * Offset 0x12: IP-PRI Mapping Register 2
156 * Offset 0x13: IP-PRI Mapping Register 3
157 * Offset 0x14: IP-PRI Mapping Register 4
158 * Offset 0x15: IP-PRI Mapping Register 5
159 * Offset 0x16: IP-PRI Mapping Register 6
160 * Offset 0x17: IP-PRI Mapping Register 7
161 */
162#define MV88E6XXX_G1_IP_PRI_0 0x10
163#define MV88E6XXX_G1_IP_PRI_1 0x11
164#define MV88E6XXX_G1_IP_PRI_2 0x12
165#define MV88E6XXX_G1_IP_PRI_3 0x13
166#define MV88E6XXX_G1_IP_PRI_4 0x14
167#define MV88E6XXX_G1_IP_PRI_5 0x15
168#define MV88E6XXX_G1_IP_PRI_6 0x16
169#define MV88E6XXX_G1_IP_PRI_7 0x17
170
171/* Offset 0x18: IEEE-PRI Register */
172#define MV88E6XXX_G1_IEEE_PRI 0x18
173
174/* Offset 0x19: Core Tag Type */
175#define MV88E6185_G1_CORE_TAG_TYPE 0x19
Vivien Didelot101515c2017-06-15 12:14:04 -0400[diff] [blame]176
177/* Offset 0x1A: Monitor Control */
178#define MV88E6185_G1_MONITOR_CTL 0x1a
179#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
180#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
181#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
182#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
183#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
184
185/* Offset 0x1A: Monitor & MGMT Control Register */
186#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
187#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
188#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
189#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
190#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
191#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO 0x0200
192#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI 0x0300
193#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
194#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
195#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
196#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
Vivien Didelotd77f4322017-06-15 12:14:03 -0400[diff] [blame]197
198/* Offset 0x1C: Global Control 2 */
199#define MV88E6XXX_G1_CTL2 0x1c
Vivien Didelot02317e62018-05-09 11:38:49 -0400[diff] [blame]200#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
201#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
202#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
Vivien Didelot408d2de2018-05-11 17:16:34 -0400[diff] [blame]203#define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000
204#define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000
205#define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000
206#define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000
Vivien Didelot9e5baf92018-05-09 11:38:51 -0400[diff] [blame]207#define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
208#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
209#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
210#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
211#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
212#define MV88E6085_G1_CTL2_DA_CHECK 0x4000
213#define MV88E6085_G1_CTL2_P10RM 0x2000
214#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
215#define MV88E6352_G1_CTL2_DA_CHECK 0x0800
216#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
217#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
218#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
219#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
220#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
221#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
222#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
Vivien Didelot408d2de2018-05-11 17:16:34 -0400[diff] [blame]223#define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0
224#define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040
225#define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080
226#define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060
227#define MV88E6390_G1_CTL2_CTR_MODE 0x0020
Vivien Didelot23c98912018-05-09 11:38:50 -0400[diff] [blame]228#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
Vivien Didelotd77f4322017-06-15 12:14:03 -0400[diff] [blame]229
Vivien Didelot57d1ef32017-06-15 12:14:05 -0400[diff] [blame]230/* Offset 0x1D: Stats Operation Register */
231#define MV88E6XXX_G1_STATS_OP 0x1d
232#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
233#define MV88E6XXX_G1_STATS_OP_NOP 0x0000
234#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
235#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
236#define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
237#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
238#define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
239#define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
240#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
241#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
242#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
243
244/* Offset 0x1E: Stats Counter Register Bytes 3 & 2
245 * Offset 0x1F: Stats Counter Register Bytes 1 & 0
246 */
247#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
248#define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
Vivien Didelote0970972017-06-02 17:06:18 -0400[diff] [blame]249
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]250int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
251int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
252int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
Vivien Didelot17e708b2016-12-05 17:30:27 -0500[diff] [blame]253
Vivien Didelot4b0c4812017-06-15 12:14:00 -0400[diff] [blame]254int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
255
Vivien Didelot17e708b2016-12-05 17:30:27 -0500[diff] [blame]256int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
257int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
258
Vivien Didelota199d8b2016-12-05 17:30:28 -0500[diff] [blame]259int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
260int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
261
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100[diff] [blame]262int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
Andrew Lunna605a0f2016-11-21 23:26:58 +0100[diff] [blame]263int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
264int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn79523472016-11-21 23:27:00 +0100[diff] [blame]265int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn40cff8f2017-11-10 00:36:41 +0100[diff] [blame]266int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
Andrew Lunnde2273872016-11-21 23:27:01 +0100[diff] [blame]267int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +0100[diff] [blame]268void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
Andrew Lunn40cff8f2017-11-10 00:36:41 +0100[diff] [blame]269int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
Andrew Lunn33641992016-12-03 04:35:17 +0100[diff] [blame]270int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
271int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
272int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
273int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn6e55f692016-12-03 04:45:16 +0100[diff] [blame]274int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]275
Vivien Didelot93e18d62018-05-11 17:16:35 -0400[diff] [blame]276int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
277int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
278
Vivien Didelot02317e62018-05-09 11:38:49 -0400[diff] [blame]279int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
280
Vivien Didelot9e5baf92018-05-09 11:38:51 -0400[diff] [blame]281int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
282int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
283int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
284
Vivien Didelot23c98912018-05-09 11:38:50 -0400[diff] [blame]285int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
286
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -0500[diff] [blame]287int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
Vivien Didelot720c6342017-03-11 16:12:48 -0500[diff] [blame]288int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
289 unsigned int msecs);
Vivien Didelotdabc1a92017-03-11 16:12:53 -0500[diff] [blame]290int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
291 struct mv88e6xxx_atu_entry *entry);
Vivien Didelot9c13c022017-03-11 16:12:52 -0500[diff] [blame]292int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
293 struct mv88e6xxx_atu_entry *entry);
Vivien Didelotdaefc942017-03-11 16:12:54 -0500[diff] [blame]294int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
Vivien Didelote606ca32017-03-11 16:12:55 -0500[diff] [blame]295int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
296 bool all);
Andrew Lunn09776442018-01-14 02:32:44 +0100[diff] [blame]297int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
298void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
Vivien Didelot720c6342017-03-11 16:12:48 -0500[diff] [blame]299
Vivien Didelotf1394b782017-05-01 14:05:22 -0400[diff] [blame]300int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
301 struct mv88e6xxx_vtu_entry *entry);
Vivien Didelot0ad5daf2017-05-01 14:05:23 -0400[diff] [blame]302int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
303 struct mv88e6xxx_vtu_entry *entry);
Vivien Didelotf1394b782017-05-01 14:05:22 -0400[diff] [blame]304int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
305 struct mv88e6xxx_vtu_entry *entry);
Vivien Didelot0ad5daf2017-05-01 14:05:23 -0400[diff] [blame]306int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
307 struct mv88e6xxx_vtu_entry *entry);
Vivien Didelot931d1822017-05-01 14:05:27 -0400[diff] [blame]308int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
309 struct mv88e6xxx_vtu_entry *entry);
310int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
311 struct mv88e6xxx_vtu_entry *entry);
Vivien Didelotb486d7c2017-05-01 14:05:13 -0400[diff] [blame]312int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
Andrew Lunn62eb1162018-01-14 02:32:45 +0100[diff] [blame]313int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
314void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
Vivien Didelot332aa5c2017-05-01 14:05:12 -0400[diff] [blame]315
Vivien Didelota935c052016-09-29 12:21:53 -0400[diff] [blame]316#endif /* _MV88E6XXX_GLOBAL1_H */