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Vivien Didelota935c052016-09-29 12:21:53 -04001/*
2 * Marvell 88E6xxx Switch Global (1) Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef _MV88E6XXX_GLOBAL1_H
15#define _MV88E6XXX_GLOBAL1_H
16
17#include "mv88e6xxx.h"
18
19int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
20int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
21int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
Vivien Didelot17e708b2016-12-05 17:30:27 -050022
23int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
24int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
25
Vivien Didelota199d8b2016-12-05 17:30:28 -050026int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
27int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
28
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +010029int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
Andrew Lunna605a0f2016-11-21 23:26:58 +010030int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
31int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn79523472016-11-21 23:27:00 +010032int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
Andrew Lunnde2273872016-11-21 23:27:01 +010033int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
Andrew Lunn7f9ef3a2016-11-21 23:27:05 +010034void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
Andrew Lunn33641992016-12-03 04:35:17 +010035int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
36int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
37int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
38int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
Andrew Lunn6e55f692016-12-03 04:45:16 +010039int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
Vivien Didelota935c052016-09-29 12:21:53 -040040
Vivien Didelotc3a7d4a2017-03-11 16:12:51 -050041int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
Vivien Didelot720c6342017-03-11 16:12:48 -050042int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
43 unsigned int msecs);
Vivien Didelotdabc1a92017-03-11 16:12:53 -050044int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
45 struct mv88e6xxx_atu_entry *entry);
Vivien Didelot9c13c022017-03-11 16:12:52 -050046int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
47 struct mv88e6xxx_atu_entry *entry);
Vivien Didelot720c6342017-03-11 16:12:48 -050048
Vivien Didelota935c052016-09-29 12:21:53 -040049#endif /* _MV88E6XXX_GLOBAL1_H */